High Frequency Oscillator Design Using the Technique of

Negative Resistance

S.D. MacPherson
Dept. of Electronic Engineering, Technikon Natal
.Durban, 400 1, South Africa

An alternative method of analysing an oscillator, based upon the technique of modelling it as a one-port network
exhibiting negative resistance, is used to design an oscillator for use in the 915 MHz ISM band. CAD software
is used to optimize an active network for a suitable value of negative resistance before an external resonator is
used to set the frequency of oscillation. The oscillator is constructed and simulated results are compared with
measured results, showing that the procedure is both valid and practical.

1. Introduction I rL

through the device results in a decrease in potential RL

difference across it. An example of a low frequency
device which exhibits negative resistance is the
unijunction transistor or UJT. At microwave
T w

examples of devices whlch exhibit negative resistance.

Figure I Negative resistance
Since a positive resistance dissipates power, it is
reasonable to assume that a device which exhibits If oscillation is occurring, such that the RF current I is
negative resistance could be used to generate an RF non-zero, then the following conditions must be
signal. satisfied.

With a potentially unstable transistor, a negative RL + R, = 0 and XL + Xi, = 0 (2)

resistance can effectively be created by terminating the
device with an impedance designed to drive it into an
unstable region [11.
When a resonator is connected to a network exhibiting
negative resistance oscillation builds until limiting
reduces the net resistance to zero. This technique is
often used at higher frequencies, typically UHF and
above, where oscillator operation using the feedback
method is more dflicult to predict accurately [2].
2. Principle of operation
Since the load is passive, R, > 0 and thus R, < 0.
Thus, while a positive resistance implies power
dissipation, a negative resistance implies a power
source. The condition that X, = -Andetermines the
frequency of oscdlation. The process of oscillation
depends on the nonlinear behaviour of the input
impedance 2, as follows:
Initially, it is necessary for the overall circuit to be
unstable at the design frequency such that

The basic principle of operation of a one-port negative

resistance oscillator is illustrated in Figure 1. The
impedance Z, =R, +jXinis the input impedance to the
active device. The device is terminated with a passive
load impedance 2, = RL+jXL. Applying Kirchhoff s
voltage law yields
(ZL +Z*,) I= 0
R, (I,a) + RL < 0 (3)
In practice a value of R, = I R, I 3 I is commonly used
to satisfy equation 3 [11. Any transient excitation or
noise now causes oscillation to build at the frequency
o. As I increases, the value of R, becomes less
(1) negative until the value o f R , + R, = 0. The oscillator
is now operating in a stable state.

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 The block diagram of a typical negative resistance
oscillator is shown in Figure 2.
Figure 2 Negative resisiance oscillaior
The termination Z, could be the output load resistance,
or alternatively this termination could be purely
reactive and power could be extracted from the
resonator port -This option however generally requires
very loose coupling in order that the loss resistance as
seen by the active device does not exceed the
magnitude of the negative resistance value. Note that
if the resonator is h e a d y loaded phase noise
performance will also be degraded.
The design procedure for a negative resistance
oscillator thus proceeds as follows:
0 Select an active device having adequate
frequency response, capable of generating the_-
: required output power.
- ..
0 Add external feedback to make lSlll > 1. A
value of approximately 2 is often used. The
magnitude of S,, of a common base oscillator
can usually be increased by adding an inductor
in the common base lead. Common emitter
oscillators generally use a capacitor across a
resistor.
0 The load stab& circle is plotted. A value of
I', is selected in the unstable area of the load
stability circle plane such that II'J > 1. This
will be a passive real value.
0 The value of I'," is then computed from
equation 4 [3].
rl, = s,, + -
SI2 s21r7
i-snrr -
(4)
0 The value of Z,, can then be calculated from
equation 5. - applications in the UHF band.
1 Designing an oscillator for a specific output power is
z,, = - +'in
zo (5)
1 -L
The value of 2,"should now take the form
Z, = R + jX where R is sufficietitly negative.
- only from low power circuits [4].
0 Typically, the value of Z, is now chosen such
that
-
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zR = /RI - jx
3
In practice, the resonator resistance, which
really represents loss in the resonator circuit
and loss due to radiation, can often be set to
zero. The output is then taken from the
opposite port. It should also be noted that
phase noise can be reduced by increasing the
loaded Q of the resonator.
0 Ifthe output is to be taken from the terminated
port, and I', is a value other than the required
load reflection coefficient, then Z, can be
designed as an impedance matching network to
match to the required load impedance.
Once the circuit design has been completed, it
is checked by looking through the resonator,
and noting the resultant input impedance which
should be negative and real at the required
frequency of oscillation.
0 It should be noted that the frequency of
oscillation is determined as the frequency at
which the resultant reactive component of the .
input impedance is zero, provided that
suflcient negative resistance exists at this
frequency. This is the equivalent of the
feedback approach where the frequency of
oscillation is determined as the frequency at
which the resultant open-loop phase shift is
zero, provided that suflcient open-loop gain
exbts at this fiequenqu.
The design approach will be illustrated using-an
example of an oscillator designed for the 915 MHz
ISM band. It is proposed that the oscillator will be
used to generate the camer in a simple ASK data link.
The output power of the oscillator is specified as being
0 dBm into a 50 CJ load. The supply voltage is 12 V.
3. Desim of the oscillator
-
The Avantek device AT 41485 BJT was selected for
the active device on the basis of the manufacturer's
description as being suitable for low cost oscillator
ditficult There is general disagreement in the
literature about how much RF power can be obtained
from the specified dc bias. Estimates vary from 10Y0
to 50% ofdc bias, with the highest efficiency available
The device was biased from a 12 V supply using a
 standard highhquency common emitter bias network 100
that provides good temperature stability [5]. The bias
point was initially selected at Vm = 6 V and I, = 6 mA 50

A parallel resistor/capacitor combination was inserted 0

between the emitter and ground and the circuit was
optimized for IS1,l-2. A 180 0 resistor in parallel -50
with a 5,6 pF capacitor yields an S,, value of
1,8L-32”. A plot of the load stability circle indicates -100
that any passive resistive termination will lie in the 900 905 910 915 920 925 930
r,
unstable region of the plane. In order not to load
the oscillator excessively, a 180 0 resistive termination
too
was chosen for the collector. With this termination in
place, the input impedance was computed using 80
equations 4 and 5 as Zb= -58,4 - j 5 5 Q.
60

Assuming that the total loss resistance is

40
approximately 0,3IR,I then the loaded Q of the
oscillator will be given by 20

0
(7) 900 905 910 915 920 925 930

For a selected QLof 20 the required external resonator
reactance is calculated using equation 7 as +390 0.
The inductance required is thus 68 nH.
To ensure a net reactance of 0 0,when looking
through the resonator, an external series capacitive
reactance value of -335 0 is required. This equates to
a 0.5 pF capacitor. For convenience, a 1pF capacitor
was selected, and the inductance optimized for
resonance at 915 to a value of 41 nH. The basic
topology of the oscillator is shown in Figure 3.
Figure 4 SI,phase and magnitude response
The S,,response indicates that the circuit should
oscillate at approximately 915 M H z The input port
termination can now be removed and the resonator
inductor lead grounded. This is the equivalent of
“closing the loop” with regard to the feedback method
of oscillator analysis.
Initial closed-loop simulated results indicated that the
oscillator would oscillate at approximately 1 GHz The
resonator inductor was then optimized to 52 nH for
oscillation at the required design frequency.

The final circuit diagram of the oscillator is shown in

Figure 5. The L matching network comprises of the
components C5 and L2.

Figure 3 Basic oscillator topologv
An S parameter simulation, looking through the
resonator into the oscillator now yields an input
impedance at 915 MHz of approximately -51+]0 0.
The 180 0 terminating resistor was now removed and
replaced with a simple L matching network to
transform the required 180 0 terminating impedance
to the final 50 0 output impedance of the oscillator.
The resultant S,,phase and magnitude response for the
oscillator, as seen looking through the resonator, is
shown in Figure 4, for the frequency range 900 MHz
to 930 M H z
Simulated frequency and time domain results for the
oscillator are shown in Figure 6. The simulator
predicts an output power, across the 50 0 load resistor,
of approximately 7 3 dBm at the fundamental
frequency of 914.4 M H z The second harmonic is
approximately 15 dB down at - 7.6 dBm. The time
domain representation indicates a peak output voltage
across the load of approximately 0,7 V.
At this point a prototype of the oscillator was
constructed and tested. High frequency ATC chip
capacitors were used for both the resonator and
negative resistance generating capacitors.
After slight adjustment of the resonator inductor the

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 oscillator was tuned to the correct fundamental
hquency of 915 M H z The measured response of the 1 0 1 0 6 t 5 4 MfiR 29, 1399
MKR 915.80 MMz
&
REF 1 0 . 0 d 0 m nT 2 0 d0 dB.
oscillator is shown in Figure 7. The output power at -.49

the fundamental is approximately -03 dBm.

.. .. ..

c - 5 6 OF

. . . , . . .
CEWTER 9 1 5 . 0 0 tIHz S P f i H 18.88 M W Z
R E S B Y 188 I W z VBY 38 k w z S U P 2 8 . 8 .*.E

Figure 7 Measured resulys

3. Conclusion
Fkure 5 Finalschematic of oscihtor An osciIlator has been designed using small signal S
parameters and the technique of negative resistance.
rnl It has been shown that the technique is both valid and
'0
practical. Measured results indicate the hquency of
3 oscillation has been correctly determined Although
-10 the measured output power is less than the predicted
-20
simulated result, a more accurate simulated response
could be obtained by taking into account stray
-30
parasitics, such as transistor emitter lead inductance.
- 10 Additional circuit losses, due to, for example, the k i t e
-5: unloaded Q of the inductors could also be taken into
c 1 2 3 A 5 account.

A major disadvantage of the design is the difficulty in

obtaining a high loaded Q, with the result that short
term stability and phase noise performance are poor.
This type of oscillator would however be well suited as
a broadly tunable VCO where varactor noise
rnl dominates, and intrinsic oscillator nois+ not as
horrninderrl important.
d€Irn(ofr ~ c o n J . . H B . o u l p u t ) - 7 . 4 6 5 4 8 1

2.9
References
3.5
0.1 111 D.M Pozar, Microwave Engineering, Addison
0.2 Wesley, 1990.
;. . 3 R. W. Rhea, Oscillator Design and Computer
-(J. 2
121
-:.-I
Simulafion,McGraw-Hill, 1995.
-0.6 131 G. Gonzalet. Microwave TransistorAmplflers
-0.3
-1.0 1
U
I '
I . '
A
I
I
, I
6
, I
E
, _
10
I
141
Analvsb and Design, Prentice Hall, 1984.
P.VmuUer, RF Design Guide, Artech House,
1995.
151 Hewlett Packard Application Note 944- 1,
Microwave TransbtorBias Consideratiom.
Figure 4
Simulatedfrequency and time domain resuh

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