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n g.i
GATE SOLVED PAPER
Electronics & Communication
Network Analysis
e eri
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Copyright © By NODIA & COMPANY
En
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Information contained in this book has been obtained by authors, from sources believes to be reliable. However,
neither Nodia nor its authors guarantee the accuracy or completeness of any information herein, and Nodia nor its
authors shall be responsible for any error, omissions, or damages arising out of use of this information. This book
is published with the understanding that Nodia and its authors are supplying information but are not attempting
.Le
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, the elements of the corresponding star equivalent will be scaled by a factor of
n g.i
eri
(A) k2
(B) k
(C) 1/k
e
(D) k
gin
V2 ^s h
Q. 2 The transfer function of the circuit shown below is
V1 ^s h
En
arn
(C) s 2+ (D) s 1+
s 1+ s 2+
Q. 3 A source vs ^ t h =V cos 100 t phas an internal impedance of ^4 j+3h .WIf a purely
resistive load connected to this source has to extract the maximum power out of
w
(B) 4
(C) 5
(D) 7
Q. 4 In the circuit shown below, if the source voltage VS = 100+53.13c V then the
Thevenin’s equivalent voltage in Volts as seen by the load resistance RL is
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
which attenuates by a factor of 0.8. An ac voltage VWX1 = 100 V is applied
g.i
across WX to get an open circuit voltage VYZ1 across YZ. Next, an ac voltage
VYZ2 = 100 V is applied across YZ to get an open circuit voltage VWX2 across WX.
Then, VYZ1 /VWX1 , VWX2 /VYZ2 are respectively,
n
e eri
gin
(A) 125/100 and 80/100 (B) 100/100 and 80/100
(C) 100/100 and 100/100 (D) 80/100 and 80/100
Q. 6 Two magnetically uncoupled inductive coils have Q factors q1 and q2 at the chosen
En
Q. 7 Three capacitors C1 , C2 and C 3 whose values are 10 Fm, 5 Fm, and 2 Fmrespectively,
have breakdown voltages of 10 V, 5 V and 2 V respectively. For the interconnection
shown below, the maximum safe voltage in Volts that can be applied across the
combination, and the corresponding total charge in Cm stored in the effective
w
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
Q. 8 The current IS in Amps in the voltage source, and voltage VS in Volts across the
g.i
current source respectively, are
(A) 13, 20-
(B) 8, 10-
n
(C) 8-, 20
(D) 13- , 20
Q. 10 In the following figure, C1 and C2 are ideal capacitors. C1 has been charged to
12 V before the ideal switch S is closed at t =0. The current i (t) for all t is
arn
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(A) zero
w
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
g.i
(A) 2 A (B) 1- A
n
1 j+ 1 j+
1
eri
(C) A (D) 0 A
1 j+
Q. 14 If VA VB - 6 V then V
=C -D is
V
w
ww
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
Q. 16 For the same network, with 6 V dc connected at port A, 1 W connected at port
B draws 7/3 A. If 8 V dc is connected to port A, the open circuit voltage at port
g.i
B is
(A) 6 V (B) 7 V
(C) 8 V (D) 9 V
n
Q. 17
2011
In the circuit shown below, the Norton equivalent current in amperes with respect
to the terminals P and Q is
e
gin
En
Q. 18 In the circuit shown below, the value of RL such that the power transferred to
RL is maximum is
w .Le
ww
(A) 5 W (B) 10 W
(C) 15 W (D) 20 W
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
(A) (Vp /3) cos (t/RC ) (B) (Vp /3) sin (t/RC )
(C) (Vp /2) cos (t/RC ) (D) (Vp /2) sin (t/RC )
n
n g.i
(A) 1.4+0c A (B) 2.0+0c A
(C) 2.8+0c A (D) 3.2+0c A
Q. 21
Y >=
0.1 S 0-.01 S
0.01 S 0.1 SH
e eri
In the circuit shown below, the network N is described by the following Y matrix:
. the voltage gain V2 is
V1
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En
arn
Q. 22 In the circuit shown below, the initial charge on the capacitor is 2.5 mC, with the
.Le
voltage polarity as indicated. The switch is closed at time t =.0 The current i (t)
at a time t after the switch is closed is
w
ww
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 23 For the two-port network shown below, the short-circuit admittance parameter
matrix is
4 2- 1 0-.5
(A) >
4H
(B) >
1H
n
S S
2- 0-.5
g.i
1 0. 5 4 2
(C) >
1H
(D) >
4H
S S
0.5 2
Q. 24 For parallel RLC circuit, which one of the following statements is NOT correct ?
n
(A) The bandwidth of the circuit decreases if R is increased
eri
(B) The bandwidth of the circuit remains same if L is increased
(C) At resonance, input impedance is a real quantity
(D) At resonance, the magnitude of input impedance attains its minimum
e
value.
gin
Q. 25 In the circuit shown, the switch S is open for a long time and is closed at t =.
0
The current i (t) for t $ 0 +is
arn
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- t
1000
(A) i (t) 0.5 =0.125e -
A
- t
1000
(B) i (t) 1.5 =0.125e -
A
w
- t
(C) i (t) 0.5 =0.5e 1000 A-
- t
1000
(D) i (t) =
0.375e A
ww
(A) j-
1A (B) j1 A
(C) 0 A (D) 20 A
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
(A) 0 W (B) 5 W
g.i
(C) 10 W (D) 100 W
n
GATE 2009 ONE MARK
eri
Q. 28 In the interconnection of ideal sources shown in the figure, it is known that the
60 V source is absorbing power. e
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En
(C) 15 A (D) 18 A
Vi (s) 2 sCR+
w
ww
Q. 30 A fully charged mobile phone with a 12 V battery is good for a 10 minute talk-
time. Assume that, during the talk-time the battery delivers a constant current of
2 A and its voltage drops linearly from 12 V to 10 V as shown in the figure. How
much energy does the battery deliver during this talk-time?
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
GATE 2009 TWO MARK
g.i
Q. 31 An AC source of RMS voltage 20 V with internal impedance Zs (1 =2j) W +
feeds a load of impedance ZL (7 =4j) W + figure below. The reactive power
in the
consumed by the load is
n
e eri
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(A) 8 VAR (B) 16 VAR
(C) 28 VAR (D) 32 VAR
En
Q. 32 The switch in the circuit shown was on position a for a long time, and is move to
position b at time t =.0 The current i (t) for t >
0 is given by
arn
.Le
- t
125 - t
1250
(A) 0.2e u (t) mA (B) 20e u (t) mA
- t
1250 - t
1000
(C) 0.2e u (t) mA (D) 20e u (t) mA
w
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
GATE 2008 ONE MARK
g.i
Q. 35 In the following graph, the number of trees (P) and the number of cut-set (Q) are
n
(A) P 2, Q = 2 =
e eri
(B) P 2, Q = 6 =
4, Q = 6 = 4, Q = 10 =
gin
(C) P (D) P
(A) 0 (B) Rs Is
L
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(R +s) Is
R
(C) (D) 3
L
Q. 37 The Thevenin equivalent impedance Zth between the nodes P and Q in the
following circuit is
ww
(A) 1 (B) 1 s +1 +
s
2
(C) 2 s +1 + (D) s2 s +1 +
s s 2s +1 +
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
(B) L 0.1 H, R = 0.5 ,WC 5F = =
g.i
(C) L 5 H, R = 2 ,WC 0.1 F = =
(D) L 0.1 H, R = 2 ,WC 5F = =
n
Q. 39 The circuit shown in the figure is used to charge the capacitor C alternately
from two current sources as indicated. The switches S1 and S2 are mechanically
coupled and connected as follows:
For 2nT # t # (2n 1+) T , (n =
eri
0, 1, 2,..) S1 to P1 and S2 to P2
For (2n 1) T # t # (2n +2) T, (n = 0, 1, 2,...) S1 to Q1 and+S2 to Q2
e
gin
En
Assume that the capacitor has zero initial charge. Given that u (t) is a unit step
arn
3
(B) u (t) 2 / ( +1) n u (t nT)- -
n 1=
3
(C) tu (t) 2 / ( +1) n u (t nT)-
(t nT) - -
n 1=
w
(D) / 60.5 T@
3
(t -2nT) - (t 2nT) - -
e -0.5e + -
n 1=
ww
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
(A) 2 ^e t e- t h (B) 2 te 2 t
1- 3 1-
2 2
3 3
(C) 2 e 2 t cos c 3 t m (D) 2 e 2 t sin c 3 t m
-
1 1-
3 2 3 2
Q. 41 For t >,0 the voltage across the resistor is
(A) 1 _e e- 2-t i
3t 1
2
3
3
=cos c 2 t m -1 sin c 3 t mG
1-t
(B) e 2
n
3 2
(C) 2 e 2 t sin c 3 t m
1-
g.i
3 2
(D) 2 e 2 t cos c 3 t m
1-
3 2
n
Statement for linked Answers Questions 42 and 43:
e eri
A two-port network shown below is excited by external DC source. The voltage
and the current are measured with voltmeters V1, V2 and ammeters. A1, A2 (all
assumed to be ideal), as indicated
gin
En
1. 5 1. 5 1.5 4. 5
(A) =
1. 5 G
(B) =
4. 5 1.5 4. 5 G
1.5 4. 5 4. 5 1.5
(C) =
1. 5 G
(D) =
1.5 1. 5 4.5G
w
3 3 3 1
(C) =
1 0.67 G
(D) =
3 -0.67 G -
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
g.i
GATE 2007 TWO MARKS
Q. 46 Two series resonant filters are as shown in the figure. Let the 3-dB bandwidth of
Filter 1 be B1 and that of Filter 2 be B2 . the value B1 is
n
B2
e eri
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(A) 4 (B) 1
(C) 1/2 (D) 1/4
En
Q. 47 For the circuit shown in the figure, the Thevenin voltage and resistance looking
into X Y - are
arn
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(A) 4
3 V, 2 W (B) 4 V, 23 W
(C) 4
3 V, 23 W (D) 4 V, 2 W
w
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 49 In the ac network shown in the figure, the phasor voltage VAB (in Volts) is
n
g.i
GATE 2006 TWO MARKS
n
1 2
eri
If port-2 is terminated by RL , the input impedance seen at port-1 is given by
(A) A BR + L (B) ARL C +
C DR + L BRL D +
e
(C) DRL +
A (D) B + L
AR
gin
BRL +
C D + L
CR
Q. 51 In the two port network shown in the figure below, Z12 and Z21 and respectively
En
arn
Q. 52 The first and the last critical frequencies (singularities) of a driving point
impedance function of a passive network having two kinds of elements, are a pole
and a zero respectively. The above property will be satisfied by
w
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 54 In the figure shown below, assume that all the capacitors are initially uncharged.
If vi (t) =
10u (t) Volts, vo (t) is given by
n
(C) 8u (t) Volts (D) 8 Volts
g.i
Q. 55 A negative resistance Rneg is connected to a passive network N having driving
point impedance as shown below. For Z2 (s) to be positive real,
n
e eri
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(A) Rneg # Re Z1 (j ), 6 w w (B) Rneg # Z1 (j ) , 6 w w
(C) Rneg # Im Z1 (j ), 6 w w (D) Rneg # +Z1 (j ), 6 w w
En
Q. 56 The condition on R, L and C such that the step response y (t) in the figure has
arn
no oscillations, is
.Le
L
w
(A) R $ 1 L (B) R $
2 C C
L (D) R = 1
ww
(C) R $ 2
C LC
Q. 57 The ABCD parameters of an ideal n: 1 transformer shown in the figure are
n 0
>0 x H
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
(A) n (B) 1
n
(C) n2 (D) 12
n
Q. 58 In a series RLC circuit, R =
2 k ,WL =
1 H, and C =1 Fm The resonant
400
frequency is
(A) 2 # 10 4 Hz (B) 1 # 10 4 Hz
p
(C) 10 4 Hz (D) 2 #p 10 4 Hz
Q. 59 The maximum power that can be transferred to the load resistor RL from the
n
voltage source in the figure is
n g.i
(A) 1 W
(C) 0.25 W
e eri
(B) 10 W
(D) 0.5 W
gin
Q. 60 The first and the last critical frequency of an RC -driving point impedance
function must respectively be
(A) a zero and a pole (B) a zero and a zero
En
Q. 61 For the circuit shown in the figure, the instantaneous current i1 (t) is
w .Le
2 2
(C) 5 60c A (D) 5 - A
60c
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 63 For the circuit shown in the figure, Thevenin’s voltage and Thevenin’s equivalent
resistance at terminals a b - is
n
g.i
Q. 64 If R1 R2 = R4 R and = R3 = 1.1=R in the bridge circuit shown in the figure, then
the reading in the ideal voltmeter connected between a and b is
n
e eri
gin
(A) 0.238 V (B) 0.138 V
(C) 0-.238 V (D) 1 V
0 . 1 0. 1 10 1-
(A) =
0-.1 0.3G
(B) =
1 0.05G
.Le
30 20 10 1
(C) =
20 20G
(D) =
1- 0.05G
w
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 67 Consider the network graph shown in the figure. Which one of the following is
NOT a ‘tree’ of this graph ?
n
n g.i
(A) a
(B) b
(C) c
e eri
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(D) d
Q. 68 The equivalent inductance measured between the terminals 1 and 2 for the circuit
shown in the figure is
En
arn
(A) L1 L2 +M +
.Le
(B) L1 L2 +M -
(C) L1 L2 +2M +
(D)L1 L2 +2M -
w
+ .1c)
(A) 5 sin (2t 53
- .1c)
(B) 5 sin (2t 53
+ .1c)
(C) 25 sin (2t 53
- .1c)
(D) 25 sin (2t 53
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 70 For the circuit shown in the figure, the time constant RC = 1 ms. The input
voltage is vi (t) = 2 sin 103 t . The output voltage vo (t) is equal to
n
(A) sin (103 t - c)
45 (B) sin (103 t + c)
45
(C) sin (103 t - c)
53 (D) sin (103 t + c)
53
g.i
Q. 71 For the R L - circuit shown in the figure, the input voltage vi (t) =
u (t). The
n
current i (t) is
e eri
gin
En
arn
.Le
1 j- 1 j+ 1 j- 1 j+
(A) =
j+G
(B) =
1 j+ 1 1 +G
-j 1 j-
1 j+ 1 j+ 1 j+ 1 -j +
(C) =
j-G
(D) =
1 j- 1 1 -j 1 +j+ G
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 73 The circuit shown in the figure has initial current iL (0 )- = 1 A through the
-
inductor and an initial voltage vC (0 ) =1 V - across the capacitor. For input
v (t) =
u (t), the Laplace transform of the current i (t) for t $ 0 is
(A) s (B) s 2+
n
s2s +1 + s2 s +1 +
s 2- 1
g.i
(C) 2 (D)
s s +1 + s2 s +1 +
Vo (s)
n
Q. 74 The transfer function H (s) = of an RLC circuit is given by
Vi (s)
eri
6
=2
H (s) 10
s 20s +106 +
The Quality factor (Q-factor) of this circuit is
e
(A) 25 (B) 50
gin
(C) 100 (D) 5000
Q. 75 For the circuit shown in the figure, the initial conditions are zero. Its transfer
V (s)
function H (s) =c is
Vi (s)
En
arn
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 77 The minimum number of equations required to analyze the circuit shown in the
figure is
n
(A) 3 (B) 4
g.i
(C) 6 (D) 7
n
resistance in series with 1 H inductance. The load that will obtain the maximum
power transfer is
(A) 1 W
(B) 1 W
(C) 1 W
(D) 1
resistance
W
e eri
resistance in parallel with 1 H inductance
resistance in series with 1 F capacitor
resistance in parallel with 1 F capacitor
gin
Q. 79 A series RLC circuit has a resonance frequency of 1 kHz and a quality factor
Q = 100 . If each of R, L and C is doubled from its original value, the new Q of
the circuit is
En
(A) 25
(B) 50
(C) 100
arn
(D) 200
Q. 80 The differential equation for the current i (t) in the circuit of the figure is
w .Le
2 2
(A) 2 d 2i 2 di +i (t) (B)= d 2i 2 di +2i (t)
ww
sin t + cos t + =
dt dt dt dt
2 2
(C) 2 d 2i 2 di +i (t) cos t + = d 2i
(D) 2 di +2i (t) sin t + =
dt dt dt dt
Q. 81 Twelve 1 W resistance are used as edges to form a cube. The resistance between
two diagonally opposite corners of the cube is
(A) 5 W (B) 1 W
6
(C) 6 W (D) 3 W
5 2
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 82 The current flowing through the resistance R in the circuit in the figure has the
form P cos 4t where P is
n
g.i
Common Data For Q. 83 and 84 :
Assume that the switch S is in position 1 for a long time and thrown to position
2 at t =.
0
n
e eri
gin
Q. 83 At t 0+ , the current i1 is
=
(A) -
V (B) V -
En
2R R
(C) V - (D) zero
4R
arn
Q. 84 I1 (s) and I2 (s) are the Laplace transforms of i1 (t) and i2 (t) respectively. The
equations for the loop currents I1 (s) and I2 (s) for the circuit shown in the figure,
after the switch is brought from position 1 to position 2 at t =, 0 are
R Ls + Cs 1
- + I1 (s)
Ls V
(A) > 1 H= G == G
s
.Le
-
Ls R + Cs I 2 (s) 0
R Ls + Cs1 - + I1 (s)
Ls -
V
(B) > 1 H= G == G
s
-
Ls R +Cs I2 (s) 0
w
R Ls + Cs1 +
-
Ls I1 (s) -
V
(C) > 1 H= G = G
=
s
-
Ls R Ls + Cs I2 (s) + 0
ww
R Ls + Cs1 +
-
Cs I1 (s) V
(D) >
Ls + Cs1 H I2 (s) + 0 G
= G =
s
=
-
Ls R
Q. 85 The driving point impedance Z (s) of a network has the pole-zero locations as
shown in the figure. If Z (0) =,
3 then Z (s) is
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
3 (s 3+) 2 (s 3+)
(A) 2
(B) 2
s 2s +3 + s 2s +2 +
3 (s 3+) 2 (s 3-)
(C) 2 (D) 2
s 2s +2 + s 2s -3 -
n
2
(C) 10 cos (t 35c) -10 cos (2t 10+c tan 1-2) + -
g.i
(D) 10 cos (t 35c) - 3
2 cos (2t +
35c) -
Q. 87 The impedance parameters z11 and z12 of the two-port network in the figure are
n
(A) z11 =
2.75 Wand z12 = 0.25 W
e eri (B) z11 =
3 W and z12 =0.5 W
gin
(C) z11 =
3 W and z12 =0.25 W (D) z11 =
2.25 Wand z12 = 0.5 W
Q. 89 In the figure, the switch was closed for a long time before opening at t =.
0 The
w
voltage vx at t = 0+ is
ww
(A) 25 V (B) 50 V
(C) 5-0 V (D) 0 V
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 90 In the network of the fig, the maximum power is delivered to RL if its value is
(A) 16 W (B) 40 W
3
n
(C) 60 W (D) 20 W
g.i
Q. 91 If the 3-phase balanced source in the figure delivers 1500 W at a leading power
factor 0.844 then the value of ZL (in ohm) is approximately
n
(A) 90+32.44c
e eri
(B) 80+32.44c
gin
(C) 80+ 32- .44c (D) 90+ 32- .44c
Q. 93 If each branch of Delta circuit has impedance 3 Z , then each branch of the
w
(C) 3 3 Z (D) Z
3
Q. 94 The admittance parameter Y12 in the 2-port network in Figure is
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
(A) 48 V (B) 24 V
n
(C) 36 V (D) 28 V
g.i
Q. 96 When the angular frequency w
in the figure is varied 0 to 3, the locus of the
current phasor I2 is given by
n
e eri
gin
En
arn
w .Le
In the figure, the value of the load resistor RL which maximizes the power delivered
ww
Q. 97
to it is
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 98 The z parameters z11 and z21 for the 2-port network in the figure are
6 ; z = 16 W 4W -
; z21 = 4 W
n
(C) z11 21 = z11
(D) = W
11 11 11 11
g.i
GATE 2000 ONE MARK
n
Q. 99 The circuit of the figure represents a
e eri
gin
Q. 101 In the circuit of the figure, the value of the voltage source E is
ww
(A) - V
16 (B) 4 V
(C) 6-V (D) 16 V
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 102 Use the data of the figure (a). The current i in the circuit of the figure (b)
n
g.i
(A) 2-A (B) 2 A
(C) 4-A (D) 4 A
n
GATE 1999 ONE MARK
Q. 103
figure is
e eri
Identify which of the following is NOT a tree of the graph shown in the given
gin
En
Q. 104 A 2-port network is shown in the given figure. The parameter h21 for this network
can be given by
w .Le
Q. 105 The Thevenin equivalent voltage VTH appearing between the terminals A and B
of the network shown in the given figure is given by
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 106 The value of R (in ohms) required for maximum power transfer in the network
shown in the given figure is
n
(A) 2 (B) 4
g.i
(C) 8 (D) 16
Q. 107 A Delta-connected network with its Wye-equivalent is shown in the given figure.
n
The resistance R1, R2 and R3 (in ohms) are respectively
e eri
gin
(A) 1.5, 3 and 9 (B) 3, 9 and 1.5
(C) 9, 3 and 1.5 (D) 3, 1.5 and 9
En
Q. 108 A network has 7 nodes and 5 independent loops. The number of branches in the
arn
network is
(A) 13 (B) 12
(C) 11 (D) 10
.Le
Q. 111 The parallel RLC circuit shown in the figure is in resonance. In this circuit
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
0 1-/2
The short-circuit admittance matrix a two-port network is >
1/2 0 H
Q. 112
The two-port network is
(A) non-reciprocal and passive (B) non-reciprocal and active
(C) reciprocal and passive (D) reciprocal and active
n
g.i
(A) 0.5 V (B) 3.0 V
n
(C) 3.5 V (D) 4.0 V
eri
Q. 114 A high-Q quartz crystal exhibits series resonance at the frequency sw
and parallel
resonance at the frequency p w . Then
(A) s wis very close to, but less than p w
(B) s < wp< w
e
(C) s wis very close to, but greater than p w
gin
(D) s > wp> w
(A) 12 A - A
(B) 12
(C) 4 A (D) None or these
w
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
(A) 9 V (B) 5 V
(C) 1 V (D) None of the above
n
Q. 118 The voltage V in the figure is
n g.i
(A) 10 V
(C) 5 V
e eri
(B) 15 V
(D) None of the above
gin
Q. 119 In the circuit of the figure is the energy absorbed by the 4 W
resistor in the time
interval (0, 3) is
En
arn
Q. 120 In the circuit of the figure the equivalent impedance seen across terminals a, b, is
w
ww
(A) b 16 l W (B) b 8 l W
3 3
(C) b 8 12+ jl W (D) None of the above
3
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Q. 121 In the given figure, A1, A2 and A3 are ideal ammeters. If A2 and A3 read 3 A and
4 A respectively, then A1 should read
n
(A) 1 A (B) 5 A
g.i
(C) 7 A (D) None of these
Q. 122 The number of independent loops for a network with n nodes and b branches is
n
(A) n 1-
eri
(B) b n-
(C) b n -1 +
(D) independent of the number of nodes
e
gin
GATE 1996 TWO MARKS
Q. 123 The voltages VC1, VC2, and VC3 across the capacitors in the circuit in the given
figure, under steady state, are respectively.
En
arn
(A) 80 V, 32 V, 48 V (B) 80 V, 48 V, 32 V
.Le
(C) 20 V, 8 V, 12 V (D) 20 V, 12 V, 8 V
w
***********
ww
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
SOLUTIONS
n
RB = Ra Rc
Ra Rb +Rc +
g.i
RA = Rb Rc
Ra Rb +Rc +
So, if the delta connection components Ra , Rb and Rc are scaled by a factor k
n
then
eri
^k Rb h^k Rc h k2 Rb Rc
RAl = = =
k RA
kRa kRb +kRc k R+
a Rb +Rc +
Hence, it is also scaled by a factor k
e
Sol. 2 Option (D) is correct.
gin
For the given capacitance, C = 100 Fm in the circuit, we have the reactance.
XC =1 = 1 10 4
=
sc s # 100 # 10 6- s
So,
En
10 4 10
V2 ^s h s
+4 s 1+
= 4 =
V1 ^s h 10 4 10 4 s 2+
10 + +
s s
arn
Hence, we obtain
RL 42 =32 5 W +
Sol. 4 Option (C) is correct.
w
For evaluating the equivalent thevenin voltage seen by the load RL , we open the
circuit across it (also if it consist dependent source).
ww
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
n g.i
eri
Since, VYZ =
0.8 (attenuation factor)
V
So, VYZ
VWX ^0.8h^1.25h = 1 =
e
or, VYZ =
VWX
gin
VYZ 100
at VWX =
100 V ; 1
=
1
VWX 1
100
V 100
at VWZ 100 V ; WX
= 2
=
2
VYZ 2
100
En
R1
and q2 =Lw2
R2
So, in series circuit, the effective quality factor is given by
.Le
XLeq
Q = L1 +wL2 = w
Req R1 R+2
q1 q
L1 +wL2 +2 w q R q+ R
R 1 R2 R 1 R2 R R
w
= = 2 2
=1 1 2 2
1 +1 1 +1 R1 R+2
R 2 R1 R 2 R1
Sol. 7 Option (C) is correct.
ww
Consider that the voltage across the three capacitors C1 , C2 and C 3 are V1 , V2 and
V3 respectively. So, we can write
V2 C =3 ....(1)
V3 C2
Since, Voltage is inversely proportional to capacitance
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
Hence, this is the voltage at C2 . Therefore,
V3 = 2 volt
g.i
V2 = 0.8 volt
and V1 V2 =V3 2.8 volt + =
Now, equivalent capacitance across the terminal is
n
Ceq =C2 C 3 +1 =
C 5 # 2 10+ 80 Fm
=
C2 C +3 5 2+ 7
Equivalent voltage is (max. value)
Vmax V1 = 2.8
Q =
e =
eri
So, charge stored in the effective capacitance is
Ceq Vmax b=80 l # ^2.8h = 32 Cm
gin
7
Sol. 8 Option (D) is correct.
En
arn
.Le
2 1
IS 10 +10 2 + 0 - =
2 1
ww
IS =13 -A
Also, from the circuit,
VS 5-# 2 = V1 & VS 10 =V1 = +
20 volt
Sol. 9 Option (C) is correct.
Again from the shown circuit, the current in 1 W resistor is
I V1
= 10 10 A= =
1 1
Sol. 10 Option (D) is correct.
The s -domain equivalent circuit is shown as below.
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
v (0) /s v (0)
I (s) =c = c
1 +1 1 + 1
C1 s C 2 s C1 C 2
n
C1 C2 (12 V) =
b=C1 C +2 l
g.i
I (s) 12Ceq vC (0) =
12 V
Taking inverse Laplace transform for the current in time domain,
i (t) 12Ceq (td)
= (Impulse)
n
eri
Sol. 11 Option (B) is correct.
In phasor form, Z 4 =j 3 5 -=36.86c W
-
I =
5 100c A
e
Average power delivered.
gin
1 I 2 Z cos
Pavg. = 1 25 5 cos 36.86c
q = =
50 W
2 2# #
Alternate Method:
Z (4 =j3) ,W -I 5 cos (100 t p=100) A +
En
2# " , 12 # 100 = 50 W
Pavg 1 Re $ I 2 Z .
= 1 Re (5) 2 (4 =j3) =
-
2 #
1+ 0c -1 1+
V1 1 j+ j
Current I1 = = = =1 A
j1 j1 (1 j+) j 1 j+
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Thevenin Impedance :
n
g.i
ZTh =
R
n
Thevenin Voltage :
eri
VTh =
3 0c V
Now, circuit becomes as e
gin
En
or P = 42 70 +R
(2 R +) 2
dP (2 R) 2 70 +(42 70R) 2 (2 -R) + +
= =
0
w
dR (2 R+) 4
(2 R) [(2 +R) 70 (42 70+R) 2] = 0 & -
R =
0.8 W +
ww
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
For a one port network current entering one terminal, equals the current leaving
the second terminal. Thus the outgoing current from A to B will be equal to the
n
incoming current from D to C as shown
g.i
i.e. IDC IAB = 3 A =
n
e eri
The total current in the resistor 1 Wwill be
gin
I1 2 =IDC + (By writing KCL at node D )
2 =3 5 A+ =
So, VCD 1 # ( =I1) =5 V- -
En
Now, we obtain Thevenin equivalent for the circuit seen at load terminal, let
Thevenin voltage is VTh, 10 V with 10 V applied at port A and Thevenin resistance
ww
is RTh .
V
IL = Th,10 V
RTh R +L
For RL =
1 ,WIL =
3A
V
3 =Th,10 V ...(i)
RTh 1+
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
For RL =
2.5 ,WIL =
2A
V
2 = Th,10 V ...(ii)
RTh 2+.5
Dividing above two
3 RTh 2+.5
=
2 RTh 1+
3RTh 3+ 2RTh =5 +
RTh = 2 W
Substituting RTh into equation (i)
VTh,10 V 3 (2 =1) 9 V + =
n
Note that it is a non reciprocal two port network. Thevenin voltage seen at port
g.i
B depends on the voltage connected at port A. Therefore we took subscript
VTh,10 V . This is Thevenin voltage only when 10 V source is connected at input port
A. If the voltage connected to port A is different, then Thevenin voltage will be
n
different. However, Thevenin’s resistance remains same.
eri
Now, the circuit is as shown below :
e
gin
V
For RL =
7 ,W IL =Th,10 V =9 =
1A
2 R +L 2 7+
En
. Here RL = 1 W and IL =
3
.Le
RTh # 7 =1 # 7 2 # 7 =7 +7 V
w
VTh, 6 V + =
3 3 3 3
This is a linear network, so VTh at port B can be written as
ww
VTh V1 = a b+
where V1 is the input applied at port A.
We have V1 = 10 V , VTh,10 V =9V
` 9 10 = a b+ ...(i)
When V1 = 6 V , VTh, 6 V =9V
` 7 6 =a +
b ...(ii)
Solving (i) and (ii)
a =0.5 , b =
4
Thus, with any voltage V1 applied at port A, Thevenin voltage or open circuit
voltage at port B will be
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
So, VTh, V
1
0.5V1 =4 +
For V1 =
8V
VTh,8 V 0.5 # 8 =4 8 Voc + = voltage) =
(open circuit
Sol. 17 Option (A) is correct.
Replacing P Q - by short circuit as shown below we have
n
g.i
Using current divider rule the current Isc is
25
n
ISC = (16 0 ) (6.4 =j4.8) A -
25 15 +j30 +
eri
Sol. 18 Option (C) is correct.
Power transferred to RL will be maximum when RL is equal to the Thevenin
resistance. We determine Thevenin resistance by killing all source as follows :
e
gin
En
RTH 10 # 10
= +
10 =
15 W
10 10+
arn
R$ 1
j Cw
Zp = = R
R + 1 1 j+ RCw
j Cw
Transfer function can be written as
R
Vout = Z p w
1 j+ RC
=
Vin Zs Z +p R 1 + R +
j C 1 j+wRC w
w
j RC
=
j RC (1 +j wRC) 2 + w
j
= Here w 1 =
j (1 +j) 2 + RC
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
Vout j 1
= =
Vin (1 j) 2 +j 3 +
Vp
Thus v out b=3 l cos (t/RC)
n
g.i
= Ra Rb = 6.6
n
Thus R1 =
2 W
Ra Rb +Rc 6 +6 +6 +
eri
Here R1 R 2 = R 3 2 W = =
Replacing in circuit we have the circuit shown below :
e
gin
En
(2 j4) (2 +j4) -
Z = 2 +7 W =
(2 j4) (2 +j4) -
Current I 14+0c = 2+0c =
7
.Le
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
3-
Q
VC (0 )- = - =2.5- # 10 =
50 V -
C 50 # 10 6-
Thus VC (0 )+ =50 - V
In steady state capacitor behave as open circuit thus
V (3) =
100 V
Now, VC (t) VC (3) =(VC (0 ) e +t/RC
VC (3)) + - -
t-
100 =( 50 100+
) e 10 # 50 # 10- -
6-
2 # 103 t)
(-
100 =150e -
n
Now ic (t) C dV
=
dt
g.i
3
50 # 10 6 # 150 # 2 # 103 e -2 # 10 t A
=
3
15e 2-# 10 t
=
ic (t) 15 exp ( =2 # 103 t) A -
n
Sol. 23 Option (A) is correct.
Given circuit is as shown below
e eri
gin
Input impedance Z in = 1
1 1 +j Cw +
R j Lw
At resonance 1 =Cw
Lw
So, Z in 1 =R = (maximum at resonance)
1/R
Thus (D) is not true.
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
g.i
At t =,
0 inductor current does not change simultaneously, So the circuit is
n
Current is resistor (AB)
e eri
i (0) 0.75 = 0.375 A
gin
=
2
Similarly for steady state the circuit is as shown below
En
arn
i (3) 15 = 0.5 A =
3
3-
t =L = 15 # 10 10 3-sec
=
.Le
- t
1000
Hence i (t) 0.5 =0.125e -A
Sol. 26 Option (A) is correct.
Circuit is redrawn as shown below
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
- j)
1 ( 20
Z2 = R =
1 W
-j
1 20
Voltage across Z2
-j
20
c1 -jm
20
VZ = Z2 : 20 0 = : 20
Z1 Z+2 20j
c 20j -jm
2
-
1 20
- j)
( 20
c=20j 400 +20j m
: 20 =j -
-
n
Current in resistor R is
VZ j
g.i
I = 2
= - j A= -
R 1
Sol. 27 Option (A) is correct.
n
The circuit can be redrawn as
e eri
gin
En
2 2
2VA 10 -2 0 =V+4 =
4V =
Current, I1 10 4-
= =
3A
2
.Le
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
I is always less then 12 A So, only option (A) satisfies this conditions.
Sol. 29 Option (C) is correct.
For given network we have
(RL XC ) Vi
V0 =
R (+RL XC )
RL
V0 (s) 1 + LC
sR RL
= =
Vi (s) R + RL R RRL sC +RL +
1 sR+ LC
= RL = 1
n
R RRL sC +RL 1 +
R +RsC +
RL
g.i
But we have been given
V (s)
T.F. =0 = 1
Vi (s) +
2 sCR
n
Comparing, we get
R
eri
1 + =
2 & RL = R
RL
Sol. 30 Option (C) is correct.
The energy delivered in 10 minutes is
e
t t
#0 VIdt = I # Vdt =
I # Area =
gin
E
0
- where f=
5 10+ f 4
The voltage across load is
VL = IL ZL
.Le
V (0 )- = 100 V
Thus V (0 )+ = 100 V
+
At t =
0 , the circuit is as shown below
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
I (0+) 100 = 20 mA =
5k
At steady state i.e. at t =
3 is I (3) =
0
n
+RCteq -
Now i (t) =
I (0 ) e u (t)
g.i
(0.5 0+.3 m) 0.2 m m
Ceq = =
0.16 Fm
0. 5 0.3 m +0.2 m+ m
1 1 = 1250
RCeq 5 # 103 # 0.16 # 10 6-
n
- t
i (t) 20e 1250
= u (t) mA
Sol. 33 Option (C) is correct.
eri
For Pmax the load resistance RL must be equal to thevenin resistance Req i.e. RL
=
Req . The open circuit and short circuit is as shown below
e
gin
En
arn
8
Vx =4 #-12.5 50 V= -
I2 100 V
= +x 100
= -
50 =
12.5 A
4 4
w
Isc I1 =I2 25 +
A =
Rth Voc = 100 4 =
W =
ww
Isc 25
Thus for maximum power transfer RL Req = 4 W =
Sol. 34 Option (A) is correct.
Steady state all transient effect die out and inductor act as short circuits and
forced response acts only. It doesn’t depend on initial current state. From the
given time domain behavior we get that circuit has only R and L in series with
V0 . Thus at steady state
i (t) " i (3) V=0
R
Sol. 35 Option (C) is correct.
The given graph is
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
There can be four possible tree of this graph which are as follows:
n
There can be 6 different possible cut-set.
n g.i
Option (B) is correct.
eri
Sol. 36
Initially i (0 )- =
0 therefore due to inductor i (0 )+ =0 . Thus all current Is will
flow in resistor R and voltage across resistor will be Is Rs . The voltage across
inductor will be equal to voltage across Rs as no current flow through R.
e
gin
En
Thus vL (0+) =
Is Rs
arn
di (0 )+
but vL (0+) =
L
dt
di (0+) vL (0 )+ Is Rs
Thus = =
dt L L
.Le
Zth (1 =s) ( s1 1+
) +
(1 s)( s +1)
1
[ s1 1 ++1 s] + +
= =
(1 s) +( s1 1) + s s ++
1
1 1 + +
or Zth =
1
Alternative :
Here at DC source capacitor act as open circuit and inductor act as short
circuit. Thus we can directly calculate thevenin Impedance as 1 W
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
RC
g.i
1 2 or L =
= 0.1 H
LC
Sol. 39 Option (C) is correct.
n
Voltage across capacitor is
1 tidt
#
eri
Vc =
C 0
Here C =
1 F and i =
1 A. Therefore
t
# dt
Vc =
e
0
gin
For 0 t < T , capacitor
< will be charged from 0 V
t
Vc #0 dt =t =
At t T, Vc = T Volts =
En
At t 2T, Vc = 0 volts =
For 2T t < 3T , capacitor
< will be charged from 0 V
t
Vc #2Tdt =t 2T = -
.Le
At t 3T, Vc = T Volts =
For 3T t < 4T , capacitor
< will be discharged from T Volts
t
Vc T = # dt 4-
T t = -
w
3T
At t 4T, Vc = 0 Volts =
ww
At t 5T, Vc = T Volts =
Thus the output waveform is
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
3 (s 12 ) 2 + 43 +
Taking inverse Laplace transform we have
g.i
=2 e -sin c 3 t m
t
Vt 2
3 2
n
Sol. 41 Option (B) is correct.
Let voltage across resistor be vR
Since vs
VR (s)
VS (s)
=1 1
( s s +1)
(td) " Vs (s) = 1 we get
e eri
=2 s
(+
s s +1) +
=
VR (s) = 2 s = s
gin
1 2
(s s +1) (+
s 2) + 43 +
(s +1
2)
1
= 1 2
- 2
1 2
2) +4 2+ + 43 +
3
(s (s )
En
or vR (t) e cos
1
2
3 t =1 2 e - sin 3 t
1
2
- -
2 2# 3 2
arn
t- 3 1 sin 3 t
e 2
=cos 2 t = 2 G
-
3
Sol. 42 Option (C) is correct.
From the problem statement we have
.Le
z11 v1 = 6 1.5 W = =
i1 i = 0 4 2
z21 v2
= 6 1.5 W = =
i1 i = 0 4 2
ww
h22 i2 = 1 0.67 = =
v2 i = 0 1.5
1
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
v1 z11 i1 =z12 i2 +
v2 z21 i1 =z22 i2 +
If v2 =
0 then i2 = z- 21
= 1-.5 =1 -h21 =
i1 z22 1.5
or i2 =i1 -
Putting in equation for v1, we get
v1 (z11 =z12) i1 -
v1 h11 = z11 z12 =1.5 =4.5 - 3 - = -
i1 v2 = 0
-
Hence h parameter will be
n
h11 h12 3- 3
=h h G == 1- 0.67 G
g.i
21 22
n
ZL Zs* = (Rs jXs)= -
Sol. 45 Option (C) is correct.
At "
eri
w 3 , capacitor acts as short circuited and circuit acts as shown in fig below
e
gin
Here we get V0 =
0
Vi
En
At " w 0 , capacitor acts as open circuited and circuit look like as shown in fig
below
arn
.Le
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
But from circuit i Vth = V =
th
1
g.i
Therefore
Vth Vth +Vth 2-Vth + =
2
2 1 1
n
or Vth = 4 volt
At t =3, VC (3) = 5V
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
dVC (t)
Now IC (t) =
C
dt
4 # 10 6 # ( =5 # 25e -25t) =
0.5e -t
25
mA - -
n
Option (D) is correct.
g.i
Sol. 50
n
Now V1 AV2 =BI2
e eri - ...(1)
and I1 CV2 =DI2 - ...(2)
gin
also V2 =I2 R-L ...(3)
From (1) and (2) we get
Thus V1 = -2
AV2 BI
En
I1 -2
CV2 DI
Substituting value of V2 from (3) we get
Input Impedance Zin = A # I2 RL -BI2 -
arn
C # I2 RL -DI2 -
or Zin = ARL B +
CRL D +
Sol. 51 Option (B) is correct.
.Le
At input port V1 = re I1
At output port V2 r0 (I2 = I1) r0 bI1- r0 I2 = b - +
Comparing standard equation
V1 z11 I1 =z12 I2 +
V2 z21 I1 =z22 I2 +
z12 =
0 and z21 =r0 -b
Sol. 52 Option (B) is correct.
For series RC network input impedance is
Zins 1 =R 1 sRC ++ =
sC sC
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
We know v Ldi
=
g.i
dt
Taking Laplace transform we get
V (s) sLI (s) =Li (0+) -
n
As per given in question
eri
- (0+) =1 mV
Li -
Thus i (0+) 1 mV = 0.5 A =
2 mH
e
Sol. 54 Option (B) is correct.
gin
At initial all voltage are zero. So output is also zero.
Thus v0 (0+) =0
At steady state capacitor act as open circuit.
En
arn
.Le
Thus, v0 (3) 4 # v = 4 # 10 8 = =
i
5 5
The equivalent resistance and capacitance can be calculate after killing all
source
w
ww
Req 1 4 = 0.8 k W =
Ceq 4 1 = 5 Fm =
t Req Ceq = 0.8k #
W 5 Fm 4 =
ms =
+t/ t -
v0 (t) v 0 (3) =[v 0 (3) v 0 (0 )] e- -
8 =(8 0)- e t-/0.004 -
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
t-
/0.004
v0 (t) 8 (1 =e -
) Volts
Sol. 55 Option (A) is correct.
Here Z2 (s) Rneg =Z1 (s) +
or Z2 (s) Rneg =Re Z1 (s) j Im + Z1 (s) +
For Z2 (s) to be positive real, Re Z2 (s) $ 0
Thus Rneg Re+ Z1 (s) $ 0
or Re Z1 (s) $ R -neg
But Rneg is negative quantity and R -neg is positive quantity. Therefore
n
Re Z1 (s) $ Rneg
or Rneg # Re Z1 (j )w For all .w
g.i
Sol. 56 Option (C) is correct.
Transfer function is
n
1 1
Y (s) sC 1 LC
= =2 =
eri
U (s) R sL + 1 s LC
+ scR +1 s2 R+s + 1 +
sC L LC
Comparing with s2 w n2 0 wwe have+
2 xn s + =
R,
e
Here 2 xn w=
L
gin
1
and nw =
LC
Thus x R LC = R C =
2L 2 L
En
For no oscillations, $x 1
Thus R C $1
2 L
arn
or R $2 L
C
Sol. 57 Option (B) is correct.
For given transformer
.Le
I2 V1 = n =
I1 V2 1
or I1 =I2 and V =
nV2
1
n
w
I1 CV2 =DI2 +
A B n 0
=C D G ==0 1 G
n
Thus x =1
n
Sol. 58 Option (B) is correct.
We have L =
1H and C =1 # 10 6-
400
Resonant frequency
f0 1 = = 1 =
2 pLC 2 p 1 # 1 # 10 - 6
400
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
103 # 20 = 10 4 Hz =
2 p p
Sol. 59 Option (C) is correct.
Maximum power will be transferred when RL Rs = 100 W =
In this case voltage across RL is 5 V, therefore
Pmax V2 = 5 # 5 0.=
25 W =
R 100
Sol. 60 Option (C) is correct.
For stability poles and zero interlace on real axis. In RC series network the
n
driving point impedance is
Zins R = 1 +
1 + sRC =
g.i
Cs sC
Here pole is at origin and zero is at s =1/RC - , therefore first critical
frequency is a pole and last critical frequency is a zero.
n
For RC parallel network the driving point impedance is
i1 (t) 5++0c =
10+60c
or i1 (t) 10+60c =5+0c -5
5 =5 3j + -
or i1 (t) 5 3 +90c = 10 3 +90c =
arn
2
Sol. 62 Option (B) is correct.
If L1 = j5 Wand L3 = j2 Wthe mutual induction is subtractive because current
enters from dotted terminal of j2 W coil and exit from dotted terminal of j5 .WIf
.Le
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
Thus Rth Vth = 7.5 2.5 =W =
g.i
Isc 3
Here current source being in series with dependent voltage source make it
ineffective.
n
Sol. 64 Option (C) is correct.
eri
Here Va =5 V because R1 =R2 and total voltage drop is 10 V.
Now Vb = R3 # 10 1.1 # 10 = 5.238 V =
R3 R+4 2.1
e
V Va =Vb 5 =-.
5 238 -=0.238
- V
gin
Sol. 65 Option (D) is correct.
For h parameters we have to write V1 and I2 in terms of I1 and V2 .
V1 h11 I1 =h12 V2 +
I2 h21 I1 =h22 V2 +
En
20
Thus from above equation we get
h11 h12 10 1
=h h G == 1- 0.05G
12 22
w
Since time constant RC is very small, so steady state will be reached in 2 sec.
At t = 2 sec the circuit is as shown in fig.
Vc =
3V
V2 =Vc - =3 V-
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
Here w = 2 and V = 1+0c
1 =j Cw 1+
g.i
Y +
R j Lw
= 3 + j2 # 3 + 1 1 = 3 + j4
j2 # 4
n
5+ tan - 1 4 = 5+53.11c =
3
Sol. 70
Thus
I
i (t)
Option (A) is correct.
5 sin (2t =53.1c)
e eri
V * Y = (1+0c)( 5+53.1c)= 5+53.1c
+
=
gin
vi (t) = 2 sin 103 t
Here 103 rad and Vi
w = = 2 +0c
1
j Cw 1
Now V0 = .Vt = V
En
R +1 1 w i
j+ CR
j Cw
= 1 2 +0c
arn
1 j+# 103 # 10 - 3
1 =45c -
v0 (t) sin (103 t =45c) -
Sol. 71 Option (C) is correct.
.Le
Impedance Z (s) s =2 +
Vi (s)
I (s) = = 1
s 2+ s (s 2+)
ww
1 1 = 1
2 ; s s 2+E
or I (s) -
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
z21 V
=2
I1 I 0=
1
n
the circuit for the current I1. So I =
2 1
n g.i
For z11 applying KVL at input port we get
V1
e
I (Za =Zb)
eri +
gin
Thus V1 1 I (Z =Z ) +
2 1 a b
Thus V2 -
2 1 a b
z21 1 (Z =Z ) -
2 a b
R V
SZa Z +b Za Z -b W
z11 z12 S 2 2 W
=z z G = SZa Z -b Za Z +b W
21 22
S 2 2 W
w
T X
Here Za =
2j and Zb = 2 W
z11 z12 1 j+ j 1-
ww
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
1 I (s) 1
Hence I (s) =sI (s) 1 + - + -
s s s
2 I (s) 2
1+ 6s =s 1@ + +
s s
or I (s) =2 s 2+
s s +1 +
Sol. 74 Option (B) is correct.
Characteristics equation is
s2 20s +106 =
0 +
2 2
Comparing with s 2 xn s +
w 0 wwe have+ =
n
n
6 3
nw10 = 10 =
g.i
2 x w=
20
Thus 2 x 203 = 0.02 =
10
n
Now Q 1 = 1 50 = =
2 x 0.02
Sol. 75 Option (D) is correct.
H (s)
V0 (s)
=
Vi (s)
=
R sL +
1
sC
1
e
=2
s LC
+
eri
1
sCR +1 +
gin
sC
=2 1
s (10 2 # 10 -4) s (10 4 # 10 - 4
) +1 -
+
6
= 6- 2 1 = 10
En
10 s s +1 s2 + 106 s +106 +
Sol. 76 Option (D) is correct.
Impedance of series RLC circuit at resonant frequency is minimum, not zero.
arn
Number of loops b =n 1 - +
= minimum number of equation
Number of branches b = 8 =
Number of nodes n = 5 =
Minimum number of equation 8 =5 1 -4 + =
Sol. 78 Option (C) is correct.
For maximum power transfer
ZL ZS*
= Rs =jXs -
Thus ZL 1 =1j -
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
di (t) 1
sin t Ri (t) =L # i +(t) dt +
g.i
dt C
di (t)
or sin t 2i (t) =2
dt
# i (t)+dt +
n
Differentiating with respect to t , we get
2di (t) 2d2 i (t)
eri
cos t = + i+(t)
dt dt2
Sol. 81 Option (A) is correct.
e
For current i there is 3 similar path. So current will be divide in three path
gin
En
arn
so, we get
.Le
i i 1
Vab b 3 # 1l -b 6 # 1l b 3 # 1l -=0 -
Vab Req = 1 1 1 = = 5 W + +
i 3 6 3 6
w
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
At t 0-,
= i1 (0 -) i2 (0 -) = 0 =
-
vc (0 ) =V
+
At t = 0 the circuit is as shown in fig. The voltage across capacitor and
current in inductor can’t be changed instantaneously. Thus
n
g.i
At t 0+ ,
= i1 i2 = V = -
2R
n
Sol. 84 Option (C) is correct.
eri
When switch is in position 2, as shown in fig in question, applying KVL in loop
(1),
RI1 (s) V + 1 I1 (s) + sL [I1 (s) I2 (s)]
+ = 0 -
s sC
e
) sL = V
I1 (s) 8R 1 +sL B I2 (s+ --
gin
or
sc s
z11 I1 z+12 I2 =
V1
Applying KVL in loop 2,
En
or sL 0
21 22 2
we get
R V
SR sL + 1 +sL
- W I1 (s) V
-
>
= sH
sC W=
S G
-
sL R sL + 1 WW I2 (s)+
w
SS 0
sC
T X
Sol. 85 Option (B) is correct.
ww
Zeros =3 -
=1 -j
Pole1 +
=1 -j
Pole 2 -
K (s 3+) K (s 3+) K (s 3+)
Z (s) = = =
(s 1 +j)( s 1+ j) (s+ 1) 2 +-
j2 (s 1-) 2 +1 +
From problem statement Z (0) =w 0 =3
Thus 3 K =
3 and we get K = 2
2
2 (s 3+)
Z (s) =2
s 2s +2 +
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
1 2+2 + tan 1 1 1 2+2 tan -1 2 -
g.i
10 2 cos (t 10 + c) 10 5 cos (2t 10 + c)
= +
2 + tan 1 45c 5 tan -1 2 -
n
Sol. 87 Option (A) is correct.
eri
Using 3 Y- conversion
e
gin
R1 = 2#1 2 = 0. 5 =
En
2 1 +1 4 +
R2 = 1#1 1 = 0.25 =
2 1 +1 4 +
= 2#1
arn
R3 =
0.5
2 1 +1 +
Now the circuit is as shown in figure below.
w .Le
I2 = 0
z12 R3 = 0.25 =
Sol. 88 Option (A) is correct.
Applying KCL at for node 2,
V2 V
+2 -1
V V
=1
5 5 5
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
or V2 V1 = 20 V =
Voltage across dependent current source is 20 thus power delivered by it is
PV2 # V1 20 # 20 = 80 W =
5 5
It deliver power because current flows from its +ive terminals.
Sol. 89 Option (C) is correct.
When switch was closed, in steady state, iL (0 -) =
2.5 A
n
n g.i
Sol. 90
At t = 0 ,+ iL (0+)
resistor. Thus
=
50 V -
W
gin
For maximum power delivered, RL must be equal to Rth across same terminal.
En
arn
or Vth + I1
10 =
0
but I1 V
=th -
50
40
Thus Vth V
+th -
50 =
0
w
4
or Vth = 10 V
ww
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
also V
IL c= L m
g.i
3 ZL
1500 3 c VL mc VL m cos
= q
3 3 ZL
n
(400) 2 (.844)
ZL = 90 W =
eri
1500
As power factor is leading
So, cos q 0.844 " = q 32.44 =
e
As phase current leads phase voltage
gin
ZL 90+ = q 90+ 32-
.44c = -
Sol. 92 Option (C) is correct.
Applying KCL, we get
En
e0 12- e0 + e0 +
=
0
4 4 2 2+
or e0 =
4V
arn
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
y12 =y3 -
y12 =1 - 0.05=mho
-
20
Sol. 95 Option (D) is correct.
We apply source conversion the circuit as shown in fig below.
n
g.i
Now applying nodal analysis we have
n
-
e0 80 e0 +e0 16 - += 0
10 2+ 12 6
Sol. 96
or
eri
112
112 = 28 V
4
=
gin
j Cw
I2 =Em +01c =
Em +0c
R2 + j Cw
1 j+ CR
w 2
+I2 = +90c
En
+ tan 1- CR w 2
I2 = E m Cw -
+ (90c tan 1-
w 2)
CR
1 +2 C w 2 R 22
At w = 0 I2 =0
arn
and at w = 3, I2 =Em
R2
Only figure given in option (A) satisfies both conditions.
.Le
RL + 14.14 =W + =
Sol. 98 Option (C) is correct.
ww
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
V0 = RL
n
(finite value)
Vs RL R +s
g.i
At w =
3 , circuit act as shown in figure below:
n
V0
e eri
= RL (finite value)
gin
Vs RL R +s
At resonant frequency w = 1 circuit acts as shown in fig and V0 =.
0
LC
En
arn
dt dt
Sol. 101 Option (A) is correct.
ww
Going from 10 V to 0 V
10 5 +E 1 +=
0 +
or E =16 -
V
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
V =20 - V, i =4 A-
g.i
Sol. 103 Option (C) is correct.
Tree is the set of those branch which does not make any loop and connects all
the nodes.
n
abfg is not a tree because it contains a loop l node (4) is not connected
e eri
gin
h21 = I2
I1 V 0=(short circuit)
2
arn
.Le
3Va = V1 & Va V =1
3
ww
V
-1
Now I1 V =1 V -a V 1
= 3 2V1
=
R R 3R
0 V -a = 0 V -1 -1
and I2 = 3 =V
R R 3R
-1 /3R
V
Thus I2 h21 = == 1-
I1 V 0=
2
2V1 /3R 2
Sol. 105 Option (A) is correct.
Applying node equation at node A
Vth 100 (1 -j0) Vth 0- +
+ =
0
3 4j
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
n
so, equivalent Resistor of the circuit is
n g.i
Req
Req
5
=5.20
5 20+
20 W =4
e
4+
eri
4 =4
W
=
8 +W
W+
gin
Sol. 107 Option (D) is correct.
Delta to star conversion
R1 = Rab Rac = 5 # 30 150 = 3 W =
En
=
9 W
Rab Rac +Rbc 5 30+ +15 +
Sol. 108 Option (C) is correct.
No. of branches n =l 1 +
7 =5 -
1 +=
11 -
.Le
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
or Vab 6
= 1+ =
3. 5 V
2
Sol. 114 Option (A) is correct.
Sol. 115 Option (B) is correct.
The given figure is shown below.
n
g.i
Applying KCL at node a we have
n
I i 0 =i1 7 +5 12 A= + =
Applying KCL at node f
Sol. 116
so
I
i4
=i 4 -
=12 -
Option (A) is correct.
amp
e eri
gin
En
arn
so V 3 =0 -
3 volt =
Sol. 117 Option (D) is correct.
Can not determined V without knowing the elements in box.
.Le
t-
VC (t) VC (3) =(VC (0) VC (3)) e+
RC -
ww
Here VC (3) =
10 V and (VC (0) =
6 V. Thus
t -t t -
VC (t) 10 =(6 10) e+
RC 10 -
4e RC 10 4e =
8 - =
Now VR (t) 10 =VC (t) -
t -t -
10 =10 4e RC- 4e RC + =
Energy absorbed by resistor
2 t-
#0 3V RR(t) #0 3 164e 4
t-
= # 4e 4
3
E 16 J = =
0
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
so equivalent circuit is
Zeq =
(4 8 W) 4 #W
= 8 8
=
n
4 8+ 3
g.i
Sol. 121 Option (B) is correct.
Current in A2 , I2 = 3 amp
Inductor current can be defined as I2 =3j -
n
Current in A 3 , I3 = 4
eri
Total current I1 I2 =I 3 4 =
+3j -
2 2
I e (4) =(3) 5 amp + =
In the steady state condition all capacitors behaves as open circuit & Inductors
behaves as short circuits as shown below :
w .Le
1
10 40+
Now the circuit faced by capacitor C2 and C 3 can be drawn as below :
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GATE SOLVED PAPER - EC NETWORK ANALYSIS
VC =
80 C2 80 # 2 = 32 volt =
3
C2 +3
C 5
***********
n
n g.i
e eri
gin
En
arn
w .Le
ww
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