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Improved electrical stability of CdS thin film transistors through hydrogen-based thermal

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2014 Semicond. Sci. Technol. 29 085001

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 Semiconductor Science and Technology

Semicond. Sci. Technol. 29 (2014) 085001 (5pp) doi:10.1088/0268-1242/29/8/085001

Improved electrical stability of CdS thin film

transistors through hydrogen-based thermal
treatments
A L Salas-Villasenor1, I Mejia1, M Sotelo-Lerma2, Z B Guo3,
H N Alshareef3 and M A Quevedo-Lopez1,2
1
Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, Texas,
75080, USA
2
Department of Polymer and Materials Science, University of Sonora, Hermosillo, Mexico
3
King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900, Saudi Arabia

E-mail: mquevedo@utdallas.edu

Received 28 February 2014, revised 24 April 2014

Accepted for publication 6 May 2014
Published 6 June 2014

Abstract
Thin film transistors (TFTs) with a bottom-gate configuration were fabricated using a
photolithography process with chemically bath deposited (CBD) cadmium sulfide (CdS) films as
the active channel. Thermal annealing in hydrogen was used to improve electrical stability and
performance of the resulting CdS TFTs. Hydrogen thermal treatments results in significant VT
instability (VT shift) improvement while increasing the Ion/Ioff ratio without degrading carrier
mobility. It is demonstrated that after annealing VT shift and Ion/Ioff improves from 10 V to 4.6 V
and from 105 to 109, respectively. Carrier mobility remains in the order of 14.5 cm2 V s−1. The
reduced VT shift and performance is attributed to a reduction in oxygen species in the CdS after
hydrogen annealing, as evaluated by Fourier transform infrared spectroscopy (FTIR).
Keywords: thin film transistors, electrical stability, solution-based
(Some figures may appear in colour only in the online journal)

Introduction stages of the deposition process using solution-based methods

The ability to deposit semiconductor materials over large
areas using inexpensive deposition techniques with mobilities
higher than a:Si-H (0.1–1 cm2 V s−1) [1, 2] enables the pos-
sibility to fabricate high performance and low-cost thin film
transistors (TFTs) for large area and flexible electronics
applications. In this sense, and opposite to organic TFTs,
TFTs fabricated with cadmium sulfide (CdS) will not degrade
when exposed to oxygen and moisture [3, 4]. Recently, much
progress has been made in several solution-based methods to
fabricate CdS devices at low temperature; however, device
stability has been addressed only in a limited manner [5–11].
It is important to note that most solution-processed films, such
as CdS, might have impurities that could lead to device
reliability issues [7, 9]. In the case of CdS, some of these
impurities include hydroxides from the aqueous media,
unsatisfied sulfur or carbon bonds, and cyanamide formation
as a result of incomplete thiourea hydrolysis during the initial
[12]. Thus, it is essential to investigate the electrical stability
of solution-processed CdS TFTs to estimate device lifetime
and further understand instability mechanisms in these devi-
ces. In particular, in this paper we report CdS films deposited
by chemical bath deposition (CBD) methods [9, 12].
Electrical instability in TFTs is typically evaluated by
measuring the threshold voltage shift (ΔVT) that occurs when
the device is subjected to constant voltage or drain current
stress for a period of time [13]. Such instability is generally
ascribed to charge trapping [14] in either the gate dielectric,
semiconductor, or both [15]. Therefore, the physical
mechanisms responsible for charge trapping depended not
only in the semiconductor and gate dielectric used in the TFT,
but also in the deposition method used to grow or deposit
these films. For example, studies in TFTs with hydrogenated
amorphous silicon (a:Si-H) as the semiconductor and silicon
nitride as the gate dielectric suggested that carriers are trapped
in the gate dielectric [14]. However, it was later demonstrated

0268-1242/14/085001+05$33.00 1 © 2014 IOP Publishing Ltd Printed in the UK

Semicond. Sci. Technol. 29 (2014) 085001
that bias stress also modifies the a-Si:H microstructure by
creating unsaturated valence states into which electrons are
trapped [14, 15]. Carriers trapped in these valence states
remained trapped after removing the gate bias and the VT shift
is persistent. To reverse this bias-induced threshold voltage
shift, annealing at temperature above 180 °C is
required [16, 17].
In contrast, bias stress-induced VT shift in organic TFTs
is usually not persistent, i.e., carriers trapped during bias
stress are released after removing the gate-source bias without
the need of additional thermal annealing. A number of studies
have shown that the bias stress effect in organic TFTs is
relatively independent of the gate dielectric material. These
studies concluded that the bias stress-induced carrier trapping
in organic TFTs occurs only in the semiconductor or at the
semiconductor/dielectric interface [18]. However, distin-
guishing between volume effects and trapping at the semi-
conductor/dielectric interface is complicated. On the other
hand, studies in CBD-deposited CdS films reported substantial
improvement in the electrical properties of CdCl2-thiourea
bath deposited CdS after thermal annealing [10, 19–21]. The
improvement in the electrical properties is attributed to the
change in larger grain size, lattice parameter and crystalline
structure along with a reduction in series resistance (contact
resistance) of the CdS/electrode structure. Hence, the oppor-
tunity to control electrical properties of CBD-deposited CdS
by using a proper heat-treatment is of great interest.
In particular, this paper evaluates the impact of thermal
annealing on the final electrical properties of TFT transistors
fabricated using CBD-deposited CdS films. The effect of
thermal treatments and its correlation with the resulting TFT
performance and reliability is evaluated. The chemical and
structural correlation between the CdS thin films before and
after post-deposition annealing treatment and the character-
istics of TFTs is reported. Three different conditions were
evaluated: as-deposited, 150 °C and 300 °C annealing in
forming gas, (FG, 10%H2 + 90%N2) atmosphere for 1 h. The
maximum annealing temperature was maintained at 300 °C
due to potential CdS decomposition at higher temperatures.
The results indicate that improved device performance and
reliability is achieved after annealing in hydrogen as a con-
sequence of reduced oxygen species in the films. Fourier-
transform infrared spectroscopy (FTIR) shows that thermally
treated CdS has a lower concentration of oxygen species than
as-deposited samples, which results in an improvement in VT
stability and Ion/Ioff ratio without compromising device
performance.
Materials and methods
The CdS TFTs used for the studies reported here were fab-
ricated on Si wafers with 500 nm of SiO2. The TFTs were
fabricated using an inverted staggered with bottom-gate, top-
contact structure using a photolithography process previously
reported by our group (figure 1) [10]. In this process, 10 nm/
100 nm Cr/Au thin film is used as the gate electrode with
90 nm HfO2 films deposited by atomic layer deposition
2
A L Salas-Villasenor et al
Figure 1. Schematic cross section of the CdS TFT fabricated for this
study.
(ALD) as the gate dielectric. The CdS active layer was
deposited immediately after the gate dielectric by CBD in a
cadmium chloride/sodium citrate/thiourea solution system
[8, 9]. For the CdS deposition by CBD, the substrates were
immersed in the chemical bath solution at 70 °C. The
resulting CdS films have a thickness of approximately 70 nm.
After CdS deposition, 500 nm a hard mask of parylene-C
(poly-p-xylylene) was deposited by chemical vapor deposi-
tion (at room temperature). 100 nm thick Al film deposited by
e-beam evaporation was used as S/D electrodes. After the
TFT structure is completed, the substrate is cleaved in three
pieces to maintain the same dielectric/semiconductor interface
and compare three conditions: as-deposited, 150 °C and
300 °C annealing. Post-annealing of the devices was per-
formed in a Thermco MiniBrute atmospheric furnace system
in forming gas (10%H2 + 90%N2) atmosphere at 150 °C and
300 °C for one hour.
Electrical characteristics of the TFTs before and after
annealing were measured using current–voltage (I–V) mea-
surements at room temperature in a Keithley 4200 semi-
conductor characterization system. In order to have a
consistent methodology to assess the reliability of the TFTs, a
measurement procedure previously reported by our group was
used [22]. In this method, the (ID–VG) characteristics are
initially measured three consecutive times, followed by the
output characteristic (ID–VD) measurements. Then, the same
(ID–VG) sequence is used to obtain measurements three
additional ID–VG 4 measurements. This procedure allows
detecting the bias stress effect on the device by monitoring the
VT change between the 1st and 6th ID–VG electrical mea-
surement. In the CdS devices reported here the threshold
voltage reached a quasi-steady-state with no further changes
observed after the fourth ID–VG measurement.
The CdS films before and after annealing were studied
using scanning electron microscopy (SEM), crystalline
structure was studied using x-ray diffraction (XRD) and film
composition was determined using Fourier transform infrared
spectroscopy (FTIR).
Results and discussion
The XRD results for as-deposited, 150 and 300 °C annealed
films are shown in figure 2(a). Regardless of the annealing
temperature all the films showed hexagonal phase with pre-
ferential orientation in the (002) direction with no significant
Semicond. Sci. Technol. 29 (2014) 085001
Figure 2. (a) XRD spectra and (b) SEM pictures for the CdS films annealed under different temperatures for one hour in forming gas. CdS
films show no change in crystalline structure or morphology after annealing.
difference between 150 and 300 °C annealing. Crystallite
size, as evaluated from the XRD results, is independent of the
annealing conditions. The evolution of the CdS surface
morphology was also analyzed as a function of the annealing
conditions. Figure 2(b) shows the SEM results of the CdS
films before and after annealing. No significant change in the
morphology or grain size was observed. This indicates that
neither the crystalline structure nor the film’s morphology is
affected by the thermal annealing and that any changes
observed in the resulting TFT behavior can be attributed to
chemical changes in the CdS films as a result of the annealing
process.
To further study the impact of annealing temperature in
the CdS films FTIR analyses were carried out using a Nicolet
6700 Thermo Fisher Scientific Inc. spectrophotometer in the
range of 4000–400 cm−1. Each spectrum was obtained using
500 scans with 4 cm−1 resolution. The FTIR spectra of the
CdS films are shown in figure 3. The broad absorption band in
the range from 3600–3000 cm−1 is attributed to OH−1
stretching [23] and is consistent with other reports [24–28].
figure 3 shows that the amount of OH−1 is reduced after
3
A L Salas-Villasenor et al
forming gas annealing (3600–3000 cm−1). The CBD method
uses an alkaline aqueous solution and, therefore, the solution
contains OH−1 ions. From this fact, it is easy to explain the
presence of OH−1 in the CdS films, as demonstrated by the
FTIR results in figure 3. Reduction of this OH−1 at the
interface is desired to minimize VT shift; however, at this
point we cannot identify if the OH−1 groups are located at the
interface between the dielectric/CdS [12] and/or the bulk of
the CdS films [23, 29–31]. We discuss this later in the paper.
The peak at 2300 cm−1 in figure 3 is attributed to S-H
stretching. This S-H bond is only observed in annealed CdS
films, suggesting incorporation of hydrogen species in the
CdS films after annealing. The hydrogen incorporation can be
due to the passivation of oxygen containing species such as
sulfur bonds in the CdS film. The formation of SO2− 4 in sulfide
materials deposited by CBD has already been observed by
other authors [24, 28, 32, 33]. Therefore, after annealing in H2
rich environment, the reduction and passivation of this oxy-
gen species is expected. The peak at about 2000 cm−1 is
attributed to the carbon-nitrogen (C-N) stretching vibrations
of cyanamide [23, 29–31, 34]. Recently, we proposed the
Semicond. Sci. Technol. 29 (2014) 085001
Figure 3. FTIR absorption spectra of CdS film for different thickness
showing three regions: 3600–3000 cm−1 attributed to OH-1 stretch-
ing at the dielectric/CdS interface, 2200 cm−1 attributed to the C-N
stretching vibrations of cyanamide in the bulk of the CdS film and
2400 cm−1 attributed to S-H in the bulk of CdS film.
formation of cadmium cyanamide as a possible impurity
phase in the CBD grown CdS films due to the decomposition
reaction of thiourea during initial stages of the CBD [12]. The
presence of C-N does not affect the performance of CdS
TFTs, as previously reported [32]. Nevertheless, the reduction
in the band intensity after annealing at 300 °C indicates that
the cadmium cyanamide might be reduced when annealing
the films at 300 °C.
The CdS TFT transfer curves for as deposited, 150 °C,
and 300 °C annealed for 1 h in forming gas (10%H2 + 90%N2,
FG) are shown in figure 4. The two curves correspond to the
first and sixth ID–VG measurement cycles. Gate current for all
the cases remained in the range of 10 pA to 100 pA for the
entire voltage sweep, which means the gate dielectric leakage
current is not affected by the thermal annealings. In general,
the ID–VG showed a shift to positive voltages after con-
secutive ID–VG measurements indicating negative charge
trapping in the TFTs. Clearly, the VT shift (ΔVT) is greatly
reduced after annealing at 300 °C. No higher temperature
anneals were performed because annealing at higher tem-
perature (>300 °C) decomposes the CdS films and no TFT
(channel modulation) behavior was observed [35]. Since
reduced ΔVT and better sub-threshold slope (SS) is observed
in devices annealed at 300 °C, then the reduction in the OH−
species and additional S-H bonding is occurring at the
interface between the dielectric and the semiconductor films
(HfO2/CdS) [14, 15, 36]. The OH− species affect the devices
properties by either doping the CdS film [35] or acting as trap
sites [23, 29–31] for the carriers resulting in increased ΔVT
and SS. Therefore, the reduction in OH−1 and the increase in
4
A L Salas-Villasenor et al
the S-H bonds are indicative of effective defect reduction
during the annealing in forming gas.
Field-effect mobility and threshold voltage, for devices
before and after annealing were evaluated from a linear fitting
of a plot of VG versus the square root of ID using the fol-
lowing equation [37]:
W 2
ID = Ci μ ( VG − VT ) (1)
2L FET
where VG is the gate voltage and Ci is the capacitance per unit
area of the gate dielectric. Table 1 summarizes these
characteristics.
The improved Ion/Ioff ratio, shown in table 1, for annealed
devices is the result of the combination of the reduced Ioff
current, smaller subthreshold slope (SS) and the reduction in
VT that results in higher saturation current when the transistor
is in saturation regime. Oxygen species can act as donors in
CdS film [35]. Therefore, we attribute the reduction in Ioff to a
reduction in the CdS film conductivity. At this point, the
reduction in oxygen species is likely happening throughout
the entire CdS film, affecting the grain boundaries [10], the
semiconductor/contact interface [10, 38] and at the dielectric/
semiconductor interface [12, 39]. Subthreshold slope is also
reduced from 1.21 to 0.21 V dec−1 due to the reduced defects
(traps) at the semiconductor/dielectric interface after anneal-
ing. The VT for the first ID–VG measurement (before electrical
stress) was similar for all three conditions (1 V). However,
after electrical stress, reduced VT is observed for annealed
devices when compared with not-annealed devices. This is
also consistent with the reduction of semiconductor/dielectric
interface traps with the FG gas thermal treatment. More
importantly, ΔVT was reduced from 10 V (no annealing) to
7.4 V and 4 V for films annealed at 150 and 300 °C, respec-
tively. The residual VT shift after annealing indicates that
some defects are still present in the TFTs and longer
annealing times might be necessary to eliminate oxygen
species still trapped at the grain boundaries resulting in
interface traps that affect VT and, potentially, ΔVT.
Conclusions
In summary, the effect of thermal annealing on the electrical
stability of CdS TFTs was studied. Thermal annealing
improves the device characteristics due to the reduction in
oxygen species and incorporation of S-H bonds in the CdS
films. Annealing results in excellent SS of 0.21 V dec−1 and
high Ion/Ioff ratio of 109, as well as high mobility of 14.6
cm2 V s−1 and reduced ΔVT (4.6 V). This annealing is a
simple and efficient method to improve reliability in
CdS TFTs.
Acknowledgements
Authors would like to thank CONACyT project 158281, The
AFOSR project FA9550-10-1-0183, and COSMOS for par-
tially supporting this work.
Semicond. Sci. Technol. 29 (2014) 085001
Figure 4. Output and transfer characteristics for CdS TFT with HfO2 gate dielectric and Al S/D electrodes for (a) as deposited, (b) after
150 °C for 1 h in FG, and (c) 300 °C for 1 h in FG. Leakage current is in the order of 10–11 A.
Table 1. Electrical characteristics for CdS TFTs under various annealing conditions extracted after the annealing. VT before stress was about
1 V for all three conditions.
Annealing conditions μ (cm2 Vs−1) VT (V)
As deposited 14.8 ± 3.1 11.9 ± 1.2
150 °C 14.2 ± 3.6 8.7 ± 2.0
300 °C 14.6 ± 3.1 5.9 ± 0.5
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