ELSEVIER Thin Solid Films 296 (1997) 82-90

Polycrystalline silicon thin-film transistors: A continuous evolving

technology
G. Formnato
IESS-CNR, Via Cineto Romano 42, 00156 Roma, Italy

Abstract

Polysilicon thin-film transistors (TF-I's) are of great interest for their application in large area microelectronics and in particular for active
matrix liquid crystal displays. This is owing to the improved performances of polysilicon TKFs that allow the fabrication of active matrix
devices with integrated driving circuitry. The progressive improvement of this technology has been related to the optimization of the polysilicon
active layer, first deposited by LPCVD, then obtained by solid phase crystallization of amorphous silicon and, more recently, by excimer laser
crystallization of amorphous silicon. For circuit application there is a strong demand for high performances, high stability and low noise
devices. Some specific aspects of the electrical characteristics of the polysilicon TFTs and related to their circuit application are also discussed,
including the electrical instabilities induced by hot-carrier effects, the anomalous drain current increase occurring at high source-drain voltages
(called "kink" effect) and the low-frequency noise performances. © 1997 Elsevier Science S.A.

Keywords: Circuit application; Electrical instabilities; Noise performance

1. Introduction the most widely used polysilicon TFT structure closely

Polycrystalline silicon (polysilicon) thin film transistor
(TFT) technology is very attractive for future active matrix
liquid crystal displays ( A M L C D ) , since polysilicon TFTs
can be applied not only as switching elements of the active
matrix but also for the integrated driving circuitry. In fact,
field effect mobilities in both n- and p-channel polysilicon
TFTs nowadays exceed 100 cm 2 V s - 1, the limit for a suc-
cessful integration of row and column drive circuits on the
active plate [ 1]. These performances have been achieved
through a continuous evolution of the formation process of
the polysilicon active layer. In the first part of this paper the
principal techniques used for the formation of potysilicon
will be reviewed.
In the second part some aspects concerning the electrical
characteristics of polysilicon TFTs and related to their circuit
application will be discussed including: (a) hot-carrier
effects; (b) " k i n k " effect; (c) noise performances.
2. Polysilicon active layer formation
In spite of the various techniques used for the polysilicon
active layer formation a rather conservative approach on the
TFT structure has been adopted over the last decade. In fact,
0040-6090/97/$17.00 © 1997 Elsevier Science S.A. All rights reserved
P//S0040-6090(96) 09378-9
resembles the silicon-island polysilicon gate process
employed in silicon-on-insulator (SOI) devices, where self-
aligned source and drain contacts are formed by ion-implan-
tation. The main technological effort has been devoted to the
optimization of the properties of the polysilicon active layer
and in the following sections the three main techniques
applied to the polysilicon TFTs process are discussed: low
pressure chemical vapour deposition (LPCVD), solid phase
crystallization (SPC) of amorphous silicon (a-Si) and exci-
mer laser crystallization (ELC) of a-Si.
2.1. Deposited polysilicon
Originally, the polysilicon active layer was deposited by
LPCVD from silane gas. Typical deposition parameters are:
silane pressure p - - 100-200 mTorr; deposition temperature
Ta = 580-630 °C; growth rate 10-5 nm min - i. In Fig. 1 (a)
a cross-sectional view of a film deposited at Ta = 630 °C and
p = 100 mTorr is presented. As can be seen, the crystallites
have a V appearance starting from the substrate interface and
form a mean angle with the normal of 15 ° [ 2 ]. The crystallites
have, for these deposition conditions, a preferential (110)
orientation [2,3] and contain a high density of thin laminar
(111 ) microtwins [2]. As a result of this structure, the thicker
the film is, the larger the grain size at the top-surface will be,
 G. Fortunato / Thin Solid Films 296 (1997) 82-90 83

Fig. 1. Cross-sectional views of polysilicon films deposited by LPCVD at 630 °C and different silane pressures: (a) 100 mTorr; (b) 10 mTorr; (c) 1 mTorr
(by courtesy of J. Stoemenos).

10-4 be precisely determined from transport properties. However,

:pot,. Vth (V) /J (crnZ/V-sec)
a 1.5,urn 9 II it has been shown that the characteristics ofpolysilicon TFTs
lO'S b 1'O,um 18 3 can be adequately described by assuming a uniform effective
-- c 0,6,urn 21 2 / , b.~ • -'~. DOS [7,8]. The measurement of the DOS is an essential tool
for the material characterization and process control. The
effective DOS can be determined by field-effect analysis of
%x : I000,~ // ,J
/ the transfer characteristics at fixed temperature [7] or from
the temperature dependence of the field-effect [9] or, alter-
natively, by DLTS measurements [ 10]. By combining the
measurements of both n- and p-channel TFTs, a continuous
and U-shaped DOS has been determined [7]. In Fig. 3 the
10-10
-7
I f
0
? I
7
I
14
I I i
21 28
DOS in the upper half of the gap is shown for different
GATE VOLTAGE (V)
Fig. 2. Transfer characteristics of n-channeI TFTs for different polysilicon /
active layer thicknesses (after Ref. [6] ).

where the channel is formed in a TFT. In Fig. 2 the transfer

/;
characteristics of TFTs obtained with different thicknesses of 1020
o

the polysilicon active layer are shown. As can be seen, the

-7
polysilicon TFTs performances are clearly improved by
"7
increasing the active layer thickness. On the contrary, the off-
current is also degraded by the thickness increase [4], limi- , / //
ting the benefits of this approach. The field-effect mobility
values for n-channel TFTs with deposited polysilicon and
active layer thickness below 1 txm are around 5-10 cm z V
° I ?/
s -I [5,6].
This is owing to the high density of silicon dangling bonds 10~ V." /. . . .
and distorted bonds, associated with structural defects such 0 O.i 0.2 0.3 0.4 0.5
E-EFo (eVl
as incoherent microtwins that induce localized states in the Fig. 3. Densityof states in the upper half of the polysilicongap derived from
band gap. In general, the gap density of states (DOS) is field-effect analysis: (a) 0.6 p.m polysilicon; (b) 1.5 Ixm poIysilicon; (c)
spacially non-uniform and, therefore, it is rather complex to (a) after plasma hydrogenation. (after Ref. [7] ).
84 G. Fortunato / Thin Solid Films 296 (1997) 82-90

polysilicon thicknesses and after plasma hydrogenation. The
DOS is reduced by increasing active layer thickness in agree-
ment with the structural analysis, and by plasma hydrogena-
tion, owing to the passivation of silicon dangling bonds.
Significant improvement in the grain size can be achieved
by reducing the deposition pressure, as shown in Fig. l(b)
and (c) [2]. However, the presence of large grains is accom-
panied by a considerable surface roughness, which has been
demonstrated to degrade carrier mobility [ 11] as well as the
electrical stability [ 12,13]. Although this work [2] has con-
siderably increased the understanding of the grain growth
mechanism the film roughness has limited its application.
2.2. Solid phase crystallization of a-Si
(electrically inactive) is related to other defects, such as
incoherent steps or second and higher order twins that are
electrically active [20]. This implies that a high density of
localised states is expected not only at the grain boundaries
but also within the grain. This explains how, even in large
grain (up to 5 pom) polysilicon TFTs, the electron field-effect
mobility is limited to values of 120 cm 2 V s - 1 [ 19].
In Fig. 5 the transfer characteristics of polysilicon TFTs
employing SPC material deposited at 480 °C and annealed at
580 °C for 65 h are shown. As can be seen a considerable
improvement in the device characteristics is obtained, if com-
pared with the data reported in Fig. 2 for deposited potysili-
con. This improvement is reflected in a sensible reduction of
the DOS, shown in Fig. 6, if compared with the data shown

A remarkable improvement in polysilicon TFTs perform-

ances was achieved by the introduction of polysilicon active
layers obtained by SPC of a-Si films, deposited by LPCVD
[ 14,15]. In fact, typical values of field-effect mobility in n-
channel TFTs using optimized SPC films were reported in
the range of 30--40 cm a Vs- t [ 14,15].
The a-Si films, deposited by LPCVD at temperatures below
600 °C from silane, can be converted into polysilicon by
prolonged (10-100 h) thermal annealing at temperatures
between 530-600 °C [16]. The SPC takes place by nuclea-
tion of crystalline clusters which grow spontaneously when
a critical size is reached. The growth progress by displace- Fig. 4. TEM plane view ofSPC polysiIicon annealed at 600 °C (by courtesy
ment of atoms from the amorphous phase to the crystalline ofJ. Stoemenos).
phase. The crystallization can be described by the Avrami-
Johnson-Mehl equation [ 17]:
1 0 "s ~ . . . . . . . . . . . . . . . . . . .
X(t) = 1 - exp[ - ( t - to)31r2] (1)
-=. . . . . . . ,. . . . . . . . . .
where X(t) is the crystalline fraction, to is the so-called incu-
bation time, i.e. the time required for the formation of the
first crystallites with a critical size, and to is the characteristic
crystallization time. The grain size is in the range of 0.2-1 1 0 "1o ...................

txm, much larger than in deposited polysilicon films, and

depends on both annealing temperature and deposition tem-
perature [ 16]. It has been also shown that field-effect mobil-
ity in TFTs increases as the grain size increases [ 14]. Further
1 0 -14
grain size increase can be obtained by using a-Si deposited -20 - 10 10 20 30
from disilane [ 18,19]. For a-Si deposited at 460-480 °C from
disilane and annealed for 65 h at 580-600 °C, grain sizes up Hydroganated : Not Hydrogenated
to 3-5 Ixm have been obtained [ 18,19]. This is related to the 8 10 .6 F,E. Mobility -50 cm=/Vs -50 cm=/V8 ~ - ~ ,
formation of few nuclei in the a-Si, so that they can grow Mr! 4V 11,5V | .~v *

larger before impinging on their neighbours. A disadvantage , lO., i............ -~ ..... I /J

of the SPC process of a-Si deposited from disilane is repre-
sented by the much longer incubation time and characteristic "~ 4 104 .I "?
crystallization time if compared with those for a-Si deposited
from silane [ 18]. The grains resulting from the SPC-process
2 10 "~ ....................................
are generally elliptical in shape (see Fig. 4) and present a
high density of microtwins. The generation of microtwins
0 , , r
allows a fast incorporation of the atoms in the crystal lattice -20 -10 0 10 20 30
during the SPC process, resulting in a fast reduction of the Vg (v)
free energy of the system by creating large and highly twinned Fig. 5. Transfercharacteristicsof TFTs using SPC polysiliconbeforeand
grains. On the contrary, the presence of first order twins afterhydrogenation.
 G. Fortunato / Thin Solid Films 296 (1997) 82-90 85

1 0 aa
. . . . . . . . . . . . . . . .
I I I
i . . . . . heat diffusion length during the laser pulse ( ~ 100 nm)
. ,ot.y ,ogena,--I I Z_ implies that high temperatures can be developed in the Si-
1 0 •' --'1 - - - o - - H y d r o g e n a t e d I---f---7[ ........ surface region, causing melting, without appreciable heating
....... i .... ;---1-- JJ ! ...........
( < 400 °C) of the substrate. This makes the ELC-process
compatible with glass substrates, one of the major advantage
";"E 1 0 ~; ..................... ~ . . . . . of this technique. Another advantage is that the polysilicon
obtained has a good crystallinity (see Fig. 7) with very few
0 018 ..................... ..r-. . . . . . . . . ~''{'. . . . . . . .
in-grain defects owing to the melt-regrowth process.
° ' . . . . . . .
. . . . . . . . . . . . . . .
T i;i
1 l
Depending on the laser energy density, different transfor-
mations can occur. As the energy density is increased above
1016 , , , , I , , , , I , , , , I , , , , l , , , , i .... the energy required to melt the surface of the Si-film the
0.1 0.2 0.3 0.4 0.5 0.6 amorphous layer undergoes partial melting. The resulting
E-E F (eV) structure consists roughly of two layers: an upper large
Fig. 6. Densityof states in the upperhalf of the polysilicongap for the TFTs grained layer (whose thickness is related to the primary melt
shown in Fig. 5 before (O) and after (O) hydrogenation. induced by the laser) and a lower fine grained layer (related
to the explosive crystallization) [27]. As the energy density
in Fig. 3. A further reduction of the DOS, especially in the is increased the grain size increases (see Fig. 7) reaching a
so-called deep states associated to silicon dangling bonds, maximum when the Si film is almost totally melted and only
can be achieved by plasma hydrogenation (see Fig. 6). few crystalline clusters, sparsely distributed, remain
unmelted. When this condition occurs the grains grow later-
2.3. Excimer laser crystallization of a-Si ally around the seeds, until they impinge on each other and
grain size in excess of 1 ~m can be reached (see Fig. 7(c) ).
Further improvement in the polysilicon TFTs perform- This particular condition is often referred to as super lateral
ances has been obtained by the introduction of ELC polysil- growth (SLG) [28]. At higher energy densities the film
icon active layers leading to electron field-effect mobilities completely melts and substantial undercooling of the liquid
> 100 cm 2 V s - i [21-26]. Excimer lasers emit in the UV occurs before solidification via homogeneous nucleation and
region (output wavelengths 193 nm, 248 nm and 308 nm for growth can take place, resulting in a small grain structure
ArF, KrF and XeCI gas mixtures, respectively) with a short [28].
pulse duration (10--30 ns). The combination in Si of strong Since in polysilicon TFTs electron field-effect mobility is
optical absorption of the UV light (oe> 106 c m - 1) and small found to increase with increasing grain size [ 29] it is obvious

Fig. 7. SEM images of Secco etched 80 nm thick polysiliconfilms for differentexcimerlaser irradition conditions: (a) 360 mJ cm-2; (b) 460 mJ cm-2 and
(c) 520 mJ cm-a. During laser irradiation the substratetemperaturewas kept at 340 °C.
86
W/L = I0 gm/gp, m Vds = 0.1, 0.3, I, 3, 6 V
0.001 .........i...........i::::::i:::::
1 0 "~ ........t . . . . "
~.
l O ~v,..z~v
. ~ ~lii
10 .9 ............. i ............ ÷ ............ i.......... "I
1°11
104 s
-20 -15 -10 -5 0 5
Vg, PC]
Fig, 8, Transfer characteristics of both n- and p-channeI TFTs fabricated on
polysilicon film obtained by ELC in the SLG regime (after Ref. [30] ).
that the most attractive regime is represented by the SLG. In
fact, excellent performances in TFTs employing such mate-
rial can be obtained, as shown in Fig. 8, with electron-field
effect mobilities in the 300-400 cm 2 V s-1 range [30-32].
However, owing to its peculiar mechanism, the SLG regime
corresponds to a narrow processing window and large non-
uniformities in the grain size distribution and, consequently,
in the device performances are observed. In fact, when
unmelted crystalline clusters are sufficiently apart, homoge-
neous nucleation will be triggered between the grains leading
to a situation depicted in Fig. 7(c) with a mixture of very
large grains and small grains.
Several approches to control the lateral solidification by
inducing lateral thermal gradients [33,34] or by sequential
lateral solidification [ 35 ] have been recently reported. These
techniques, often directly related to techniques developed in
the middle 1980s for SOI devices [36], although have pro-
duced further insight on the SLG-process, are still far from
representing practical solutions for large area fabrication.
Another very promising approach is the combined use of
SPC and ELC techniques [37]. When very large and highly
defected grains, obtained by SPC, are partially melted by
excimer laser irradiation, the bottom unmelted layer will act
as seed during the regrowth process. Most of the in-grain
defects are eliminated in the melted region by the melt-
regrowth process, as shown in Fig. 9, while the grain size
remains unaffected. In this way large grains with good crys-
tatlinity, extending from the free-surface down to the melt-
depth, can be obtained, as shown in Fig. 9, combining the
beneficial aspects of the two techniques. It should also be
pointed out that, since in field-effect devices the channel
region is confined within a few nanometers beneath the insu-
lator/semiconductor interface, the two-step annealing proc-
ess appears to be a very robust process for TFT fabrication.
In fact, as long as the melt-depth is larger than a few nano-
meters and smaller than the film thickness, the top-surface
structure and defect density of the polysilicon film should be
G. Fortunato / Thin Solid Films 296 (1997) 82-90
.............i
.....=:............i..........
Fig. 9. Cross-sectional view of 160 nm thick polysilicon film sequentially
vt.L~vi
~............ }............i..........4. annealed by SPC at 600 °C for 12 h and subsequently by ELC at 350 mJ
cm -2. It is evident that in the upper part of the film (where primary melt
o', ! induced by the laser irradiation occurs) a much lower defect density is
present.
the same, therefore, insensible to pulse-to-pulse fluctuations
or beam non-uniformities. This should allow a large process
window and TFT fabrication to verify this point are currently
in progress [38].
10 15 20
3. Some relevant electrical characteristics of polysilicon
TFTs for circuit application
For circuit application there is a strong demand for high
performance, high stability and low-noise devices. We have
already discussed in the previous section how the material
properties can influence the device characteristics as well as
the technological aspects to achieve high performances.
Some specific aspects of the electrical characteristics of the
polysilicon TFTs and related to their circuit application will
be now discussed. It should be pointed out that a successful
circuit design clearly relies on the understanding of the elec-
trical properties. The results presented here are relative to
TFTs employing SPC-polysilicon, which represent the
devices currently more established and well characterized,
made at THOMSON-CSF, according to a fabrication process
described in Ref. [ 39]. The devices used for the experiments
were not post-hydrogenated and the transfer characteristics
have been already shown in Fig. 5.
3.1. Hot-carrier effects
Since supply voltages applied to circuits employing poly-
silicon TFTs tend to be relatively high (10-30 V), the pres-
ence of high electric fields can induce hot-carrier effects
(HCE). The HCE in polysilicon TFTs have been recently
investigated, both in n-channel [40-43] and p-channel
devices [44,45], and appear to be the predominant mecha-
nism for device degradation. In view of the application of
such devices in active matrix LCD driving circuitry or
SRAMs, the stability of the electrical characteristics becomes
an important issue. Therefore, it is mandatory to investigate
the HCE in order to determine the long-term reliability of
polysilicon TFTs. Indeed, the application of prolonged bias-
stress in n-channel TFTs, operated at high source/drain volt-
age, Vds, and different gate voltage, Vv can greatly affect the
transconductance gm as well as the off-current [41]. Tran-
sconductance degradation is commonly related, in n-channel
MOSFETs, to a negative effective oxide charge, controlled
by the generation of acceptor-type interface states
 G. Fortunato / Thin Solid Films 295 (1997) 82-90
o.8!
0.4
0 . Vs < - 20 V. At these stresses, Vs, a dramatic degradation
-40 -20 6 2'0 40
Vs (V)
co)
< 2
-40 -20 6 2'0 40
vs (v)
Fig. 10. (a) Relative transconductance variation, A Grn/Gm, vs. stressing
gate bias V~, after stressing for 12 h at fixed source-drain voltage Vd~= 2 0 V
(each point is relative to a different sample). (b) Variation of (log I~- log
If), vs. stressing gate bias Vs, where Ii and It are the off-current measured at
Vg= - 1 2 V and Vds= I0 V, before and after bias-stressing for 12 h at
V ~ = 2 0 V, respectively (each point is relative to a different sample).
[41,46,47]. On the contrary, the off-current in polysilicon
TFTs at high Vds,depends on field enhanced generation mech-
anisms. Therefore the off-current reduction (increase) has to
be related to a reduction (increase) in the local electric field.
The electric field variations, in turn, have to be related to the
injected charge into the oxide near the drain region, where
the electric field is higher and the carriers can gain enough
energy to be injected into the oxide. In particular, in n-channel
TFTs the presence of positive charges at the oxide/semicon-
ductor interface will cause an off-current reduction [41,42],
since oxide positive charges partially screen the negative
charges on the gate electrode. By analogy, hot-electron injec-
tion (negative oxide charge) results in off-current increase
[41,42].
In Fig. 10(a) and (b) the relative variation of the tran-
sconductance A g m / g m (where A g m = g m -- gf, with gm and gr
the before and after stress transconductance respectively) and
the variation of the leakage current A/off = (Log Ii - Log If)
(where Ii and If are the off-current measured at Vg = - 12 V
and Vds= 10 V before and after stress respectively), after
stressing for 12 h at Vds = 20 V are shown as a function of
stressing gate bias Vs. From the data in Fig. 10(a) three
regions can be distinguished:
1. Vs>0 V. In this case the transconductance variations
resemble those observed in n-channel c-Si MOSFETs with
a maximum degradation around Vs = Vds/2 [46,47]. Fur-
thermore, as Vs increases in this region, the off-current
increases too, owing to electron injection near the drain
junction.
2. - 20 V< V~< 0 V. In this region the off-current is signif-
icantly reduced owing to hot-hole injection, as already
discussed. This off-current reduction is accompanied by
only a very small gm degradation. This suggests that hot-
hole injection mainly causes, in this bias-regime, the for-
87
mation of oxide hole traps that are charged positively
during the bias-stress [47]. It is important to note that for
- 2 0 V< Vs < - 1 0 V the off-current after stress can be
reduced up to 2 orders of magnitude without any appre-
ciable degradation in gm ( < 5%).
in gm Occurs, along with off-current reduction. This
implies that the formation of oxide hole traps is now
accompanied by the creation of interface states, respon-
sible for the gm degradation.
3.2. "Kink"effect
The output characteristics of polysilicon TFTs show, at
high Ve~, an anomalous current increase, often called "kink"
effect [48-50] in analogy with SOI devices [51,52]. To be
more precise the term " k i n k " effect in SOI devices is referred
to a bend in the output characteristics caused, in n-channel
devices, by the injection of holes into the floating substrate
[51,52]. Vice versa, the "kink" effect in polysilicon TFTs
is rather an avalanche-induced drain-source breakdown, as
shown in Fig. 11. This avalanche breakdown is also present
in SOI MOSFETs and is commonly ascribed to the effect of
a parasitic bipolar transistor [52]. In particular, owing to the
impact ionization occurring in the high electric field region
close to the drain, holes are injected into the floating body
(base) forcing further electron injection from the source
(emitter), then collected by the drain (collector). This added
drain current augments the impact ionization, which in turn
drives the floating body harder, thereby causing a regenera-
tive action leading to a premature breakdown. This effect
results in an increase of the output conductance and, therefore,
increases, in digital circuits, the power dissipation and
slightly degrades the switching characteristics, while in ana-
logue circuit applications, it reduces the maximum attainable
gain as well as the common mode rejection ratio.
To analyse the "kink" effect in polysilicon TFTs, two-
dimensional numerical simulations can be used [53 ]. In par-
ticular, the device analysis program called HFIELD has been
suitably modified to take into account the presence of a den-
sity of states in the semiconductor as well as impact ionization
phenomena [53]. The DOS-parameters were adjusted by
• measureddata • "~
1.5 -- simulations
0.5
0 5 10 I5 20
Vds(V)
Fig. 11. Output characteristics, measured at different V~, for a polysilicon
TFT with L = 20 tzm.
88
10000
,,,f
1000
100
,,/
,/'"
10
1
o.~.o~ie.,.o~o,.4.o~io~.~.o~ioo
E (V/cm)
Fig. 12. E l e c t r o n i m p a c t i o n i z a t i o n rate, G, vs. electric field, E, for c-Si
( c o n t i n u o u s line, after Ref. [ 5 4 ] ) a n d for p o l y s i l i c o n ( d a s h e d line), as
deduced by 2-D simulations.
fitting the experimental transfer characteristics, measured at
low source/drain voltage Vd~ [53]. Fig. 11 shows both the
experimental and simulated output characteristics of the
device, which are largely influenced by impact ionization
occurring at the drain end of the channel, for different values
of Vg. The optimised impact ionization rate, modelled accord-
ing to the Chynoweth expression [53] and shown in Fig. 12,
was found to give a good agreement with experimental data.
It is worth pointing out that, in order to fit the data at different
temperatures, there was no need to modify the room temper-
ature impact ionization parameters. In particular, this is in
contrast with the temperature dependence usually observed
for the impact ionization rate in c-Si [54], where increasing
temperature implies a rate decrease, as a result of increased
thermal scattering. A possible explanation could be related to
the relatively lower impact ionization rate found in polysili-
con than in c-Si, as shown in Fig. 12. This suggests that the
scattering with defects (such as silicon dangling bonds, impu-
rities, etc.) is the limiting process of impact ionization in
polysilicon.
3.3. Noise performances
Although the noise performance is a critical device param-
eter for analogue circuits, the noise characterization of poly-
silicon TFTs has received little attention. It has been recently
shown that polysilicon TFTs are characterized by a strong 1/f
noise [55], commonly observed in c-Si MOSFETs [56,57].
The origin of the low frequency noise in MOSFETs has
been related to either carrier, fluctuation or carrier mobility
fluctuation. In the carrier number fluctuation model, based on
the Mc Worther theory [56], the fluctuations of the drain
current are induced by fluctuations of the interfacial oxide
charge owing to the dynamic trapping and detrapping of free
carriers into slow oxide traps. In other words, owing to the
interface charge fluctuations the flat-band voltage, V~, fluc-
tuates and, therefore, also the charge induced in the semicon-
ductor fluctuates. In the mobility fluctuation model, the
fluctuations of the drain current arise from the fluctuations of
the carrier mobility possibly through a fluctuation of the scat-
tering cross-section. This results in a 1/fnoise whose inten-
sity is inversely proportional to the total number of carriers
G. Fortunato /Thin Solid Films 295 (1997) 82-90
10.7
;zl0,t
10.,0t
10"N [ ~ ~ t ) ,
1040 104 I04 I0"(
I d (A)
Fig. 13. Normalizeddrain current spectraldensity, (S~/Ia)2, at 20 Hz vs. the
mean value of the drain current, Id, for TFTs with channel lengthL = 5 ~m
(0), L=20 txm (11) and L=40 ~m ( • ). Continuous line are the best fit
to Eq. (2).
in the system. In order to discriminate between the two mech-
anisms the normalized drain current spectral density can be
analysed. In fact, according to the carrier number fluctuations,
at low values of the drain current (S~/Id) 2 shows a plateau
before decreasing as I~-2 as the TFT is turned on [57]. Vice
versa, in the case of mobility fluctuations, (S~/Id) 2 is expected
to be inversely proportional to Id [57]. Fig. 13 shows (SI/
Id) 2 vs. Id for different channel lengths [55]. From the shape
of the (S~/Id) 2 the noise in polysilicon TFTs can be ascribed
to carrier number fluctuations [55]. In order to confirm this
point we have fitted the experimental data with the theoretical
expression for the (S~/I~) 2 in the case of carrier number
fluctuations [57]:
S I / I 2 = ( 1 + a~effld/gm)a(gm/Id)ZSvfb (2)
where a is a constant, tzoffis the effective carrier mobility in
the channel, Cox is the gate oxide capacitance per unit area,
gm is the device transconductance (evaluated from the exper-
imental data) and Svrb is the fiat-band voltage spectral den-
sity. The continuous lines shown in Fig. 13 represent the best
fit of the data to Eq. (2) and, as can be easily recognized, a
very good agreement is observed. The mean value of the
fitting parameter oewas found 1.2 × 104 V s C - 1, close to that
reported for c-Si MOSFETs ( 104 V s C - 1 [57] ), while the
value of the fitting parameter Svfb was around 1.2 X 10 - s V a
Hz - 1 for L = 20 tam. The noise in polysilicon TFTs appears
much higher than in c-Si MOSFETs [58] and such a higher
noise level could be related to fluctuations of the barrier
heights present at the polysilicon grain boundaries or to a
higher density of traps in the oxide close to the interface.
Further investigations are needed to clarify the microscopic
mechanisms causing the excess noise observed in polysilicon
TFTs.
4. Conclusions
The technological evolution of the formation process of
polysilicon active layer for TFTs application has been pre-
sented. The technique that currently produces the best quality
polysilicon is ELC of a-Si, enabling the fabrication of TFTs
with electron field-effect mobility in excess to 100 cm 2 V
s - i. The achievement of such performances opens the doors
to the fabrication of driver-monolithic AMLCD devices.
 G. Fortunate / Thin Solid Films 296 (1997) 82-90
A l t h o u g h a n u m b e r o f p r o b l e m s still r e m a i n to b e s o l v e d in
ELC, including uniformity, surface roughness, pulse-to-pulse
r e p r o d u c i b i l i t y a n d m a i n t e n a n c e , t h e r e is n o d o u b t that in the
n e a r f u t u r e this t e c h n o l o g y will b e s u i t a b l y c o n t r o l l e d to pro-
duce integrated AMLCDs.
In the c a s e o f c i r c u i t a p p l i c a t i o n o f p o l y s i l i c o n T F T s , sev-
eral i s s u e s c o n c e r n i n g e l e c t r i c a l stability a n d n o i s e p e r f o r m -
a n c e s h a v e to b e c o n s i d e r e d . In the s e c o n d part o f this w o r k
s o m e a s p e c t s o f the electrical c h a r a c t e r i s t i c s o f S P C - p o l y s i l -
i c o n T F T h a v e b e e n p r e s e n t e d i n c l u d i n g the electrical insta-
bilities i n d u c e d b y h o t - c a r r i e r effects, t h e a n o m a l o u s d r a i n
c u r r e n t i n c r e a s e o c c u r r i n g at h i g h s o u r c e - d r a i n v o l t a g e s
(called "kink" e f f e c t ) a n d the l o w - f r e q u e n c y n o i s e
performances.
Acknowledgements
T h e a u t h o r w o u l d like to t h a n k his c o - w o r k e r s at l E S S : R.
C a r l u c c i o , S. Cin~, A. C o r r a d e t t i , L. M a r i u c c i , A. Pecora, I.
P o l i c i c c h i o a n d G. T a l l a r i d a w h o m a d e p o s s i b l e this work.
F u r t h e r m o r e t h e a u t h o r is also i n d e b t e d to P. L e g a g n e u x , F.
Plais, C. R e i t a a n d D. P r i b a t for m a n y useful d i s c u s s i o n s a n d
for p r o v i d i n g the d e v i c e s u s e d in t h e e x p e r i m e n t s , a n d to J.
Stoemenos for TEM analyses.
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