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AD5934
AD5934
Network Analyzer
Data Sheet AD5934
FEATURES GENERAL DESCRIPTION
Programmable output peak-to-peak excitation voltage to a The AD5934 is a high precision impedance converter system
maximum frequency of 100 kHz solution that combines an on-board frequency generator with a
Programmable frequency sweep capability with serial I2C 12-bit, 250 kSPS, analog-to-digital converter (ADC). The
interface frequency generator allows an external complex impedance to
Frequency resolution of 27 bits (<0.1 Hz) be excited with a known frequency. The response signal from
Impedance measurement range from 1 kΩ to 10 MΩ the impedance is sampled by the on-board ADC and a discrete
Capable of measuring 100 Ω to 1 kΩ with additional circuitry Fourier transform (DFT) is processed by an on-board DSP
Phase measurement capability engine. The DFT algorithm returns a real (R) and imaginary (I)
System accuracy of 0.5% data-word at each output frequency.
2.7 V to 5.5 V power supply operation
Once calibrated, the magnitude of the impedance and relative
Temperature range: −40°C to +125°C
phase of the impedance at each frequency point along the sweep
16-lead SSOP package
is easily calculated using the following two equations:
APPLICATIONS
Magnitude = R2 + I 2
Electrochemical analysis
Bioelectrical impedance analysis Phase = tan−1(I/R)
Impedance spectroscopy
A similar device, available from Analog Devices, Inc., is the
Complex impedance measurement
AD5933, which is a 2.7 V to 5.5 V, 1 MSPS, 12-bit impedance
Corrosion monitoring and protection equipment
converter, with an internal temperature sensor, available in a
Biomedical and automotive sensors
16-lead SSOP.
Proximity sensing
Nondestructive testing
Material property analysis
Fuel/battery cell condition monitoring
DDS
CORE DAC
(27 BITS)
ROUT VOUT
SCL VBIAS
I2C
SDA INTERFACE
Z(ω)
AD5934
REAL IMAGINARY
REGISTER REGISTER
RFB
1024-POINT DFT
VIN
ADC GAIN
(12 BITS)
LPF
VDD/2
05325-001
AGND DGND
Figure 1.
TABLE OF CONTENTS
Features .............................................................................................. 1 Performing a Frequency Sweep .................................................... 19
Applications ....................................................................................... 1 Register Map ................................................................................... 20
General Description ......................................................................... 1 Control Register (Register Address 0x80, Register Address
Functional Block Diagram .............................................................. 1 0x81)............................................................................................. 20
Revision History ............................................................................... 3 Start Frequency Register (Register Address 0x82, Register
Address 0x83, Register Address 0x84) .................................... 21
Specifications..................................................................................... 4
Frequency Increment Register (Register Address 0x85,
I2C Serial Interface Timing Characteristics .............................. 6 Register Address 0x86, Register Address 0x87) ..................... 21
Absolute Maximum Ratings ............................................................ 7 Number of Increments Register (Register Address 0x88,
ESD Caution .................................................................................. 7 Register Address 0x89) .............................................................. 22
Pin Configuration and Function Descriptions ............................. 8 Number of Settling Time Cycles Register (Register Address
Typical Performance Characteristics ............................................. 9 0x8A, Register Address 0x8B) .................................................. 22
System Description ......................................................................... 12 Real and Imaginary Data Registers (16 Bits—Register Address
0x94, Register Address 0x95, Register Address 0x96, Register
Transmit Stage ............................................................................. 13 Address 0x97) .............................................................................. 23
Frequency Sweep Command Sequence ................................... 14 Serial Bus Interface ......................................................................... 24
Receive Stage ............................................................................... 14 General I2C Timing .................................................................... 24
DFT Operation ........................................................................... 14 Writing/Reading to the AD5934 .............................................. 25
Impedance Calculation .................................................................. 15 Block Write .................................................................................. 25
Magnitude Calculation .............................................................. 15 Read Operations ......................................................................... 26
Gain Factor Calculation ............................................................ 15 Typical Applications ....................................................................... 27
Impedance Calculation Using Gain Factor ............................. 15 Measuring Small Impedances ................................................... 27
Gain Factor Variation with Frequency .................................... 15 Biomedical: Noninvasive Blood impedance Measurement .. 28
2-Point Calibration ..................................................................... 16 Sensor/Complex Impedance Measurement............................ 29
2-Point Gain Factor Calculation .............................................. 16 Electro-Impedance Spectroscopy............................................. 29
Gain Factor Setup Configuration ............................................. 16 Layout and Configuration ............................................................. 30
Gain Factor Recalculation ......................................................... 16 Power Supply Bypassing and Grounding ................................ 30
Gain Factor Temperature Variation ......................................... 17 Outline Dimensions ....................................................................... 31
Impedance Error......................................................................... 17 Ordering Guide .......................................................................... 31
Measuring the Phase Across an Impedance ........................... 17
Rev. E | Page 2 of 31
Data Sheet AD5934
REVISION HISTORY
9/2017—Rev. D to Rev. E Changes to Frequency Sweep Command Sequence Section and
Changes to Control Register Section ............................................20 Receive Stage Section ...................................................................... 14
Changes to Gain Factor Calculation Section and Impedance
5/2017—Rev. C to Rev. D Calculation Using Gain Factor Section ........................................ 15
Changes to Bit D3 Description, Table 9 .......................................20 Changes to Figure 20 ...................................................................... 16
Changes to Impedance Error Section........................................... 17
7/2012—Rev. B to Rev. C Added Measuring the Phase Across an Impedance Section ..... 19
Changes to Pin 10, Description Column, Table 4 and Pin 11, Added Figure 28 and Figure 29; Renumbered Sequentially ...... 20
Description Column, Table 4 ........................................................... 8 Added Table 6; Renumbered Sequentially ................................... 20
Changes to Table 6 ..........................................................................18 Deleted Table 8 ................................................................................ 19
Deleted Choosing a Reference for the AD5934 and Table 17; Deleted Table 10 and Table 11 ....................................................... 20
Renumbered Sequentially ..............................................................30 Changes to Table 9 .......................................................................... 22
Deleted Table 14, Table 16, and Table 17 ..................................... 22
2/2012—Rev. A to Rev. B Changes to Status Register (Register Address 0x8F) Section .... 24
Deleted Evaluation Board ................................................. Universal Added Measuring Small Impedances Section, Figure 37, and
Changes to Impedance Error Section ...........................................17 Table 16 ............................................................................................. 29
Changes to Table 17 ........................................................................ 32
5/2008—Rev. 0 to Rev. A Added Evaluation Board Section .................................................. 34
Changes to Layout .............................................................. Universal Added Figure 40 .............................................................................. 35
Changes to Features Section, General Description Section, and Added Figure 41 .............................................................................. 36
Figure 1 ............................................................................................... 1 Added Figure 42 .............................................................................. 37
Deleted Table 1; Renumbered Sequentially ................................... 1 Added Figure 43 .............................................................................. 38
Changes to Table 1 ............................................................................ 4 Added Table 18 ................................................................................ 39
Changes to Table 2 ............................................................................ 6 Changes to Ordering Guide ........................................................... 40
Changes to Figure 3 and Table 4 ..................................................... 8
Changes to System Description Section and Figure 14..............12 6/2005—Revision 0: Initial Version
Changes to Figure 16 ......................................................................13
Rev. E | Page 3 of 31
AD5934 Data Sheet
SPECIFICATIONS
VDD = 3.3 V, MCLK = 16.776 MHz, 2 V p-p output excitation voltage @ 30 kHz, 200 kΩ connected between Pin 5 and Pin 6; feedback
resistor = 200 kΩ connected between Pin 4 and Pin 5; PGA gain = ×1, unless otherwise noted.
Table 1.
Y Version 1
Parameter Min Typ Max Unit Test Conditions/Comments
SYSTEM
Impedance Range 1k 10 M Ω 100 Ω to 1 kΩ requires extra buffer circuitry,
see Measuring Small Impedances section
Total System Accuracy 0.5 % 2 V p-p output excitation voltage at 30 kHz,
200 kΩ connected between Pin 5 and Pin 6
System Impedance Error Drift 30 ppm/°C
TRANSMIT STAGE
Output Frequency Range 2 1 100 kHz
Output Frequency Resolution 0.1 Hz <0.1 Hz resolution achievable using
direct digital synthesis (DDS) techniques
MCLK Frequency 16.776 MHz Maximum system clock frequency
TRANSMIT OUTPUT VOLTAGE
Range 1
AC Output Excitation Voltage 3 1.98 V p-p Refer to Figure 4 for output voltage distribution
DC Bias 4 1.48 V DC bias of the ac excitation signal; see Figure 5
DC Output Impedance 200 Ω TA = 25°C
Short-Circuit Current to Ground at VOUT ±5.8 mA TA = 25°C
Range 2
AC Output Excitation Voltage3 0.97 V p-p See Figure 6
DC Bias4 0.76 V DC bias of output excitation signal; see Figure 7
DC Output Impedance 2.4 kΩ
Short-Circuit Current to Ground at VOUT ±0.25 mA
Range 3
AC Output Excitation Voltage3 0.383 V p-p See Figure 8
DC Bias4 0.31 V DC bias of output excitation signal; see Figure 9
DC Output Impedance 1 kΩ
Short-Circuit Current to Ground at VOUT ±0.20 mA
Range 4
AC Output Excitation Voltage3 0.198 V p-p See Figure 10
DC Bias4 0.173 V DC bias of output excitation signal; see Figure 11
DC Output Impedance 600 Ω
Short-Circuit Current to Ground at VOUT ±0.15 mA
SYSTEM AC CHARACTERISTICS
Signal-to-Noise Ratio 60 dB
Total Harmonic Distortion −52 dB
Spurious-Free Dynamic Range
Wide Band (0 MHz to 1 MHz) −56 dB
Narrow Band (±5 kHz) −85 dB
Rev. E | Page 4 of 31
Data Sheet AD5934
Y Version 1
Parameter Min Typ Max Unit Test Conditions/Comments
RECEIVE STAGE
Input Leakage Current 1 nA To VIN pin
Input Capacitance 5 0.01 pF Pin capacitance between VOUT and GND
Feedback Capacitance, CFB 3 pF Feedback capacitance around current-to-
voltage amplifier; appears in parallel with
feedback resistor
ANALOG-TO-DIGITAL CONVERTER5
Resolution 12 Bits
Sampling Rate 250 kSPS ADC throughput rate
LOGIC INPUTS
Input High Voltage, VIH 0.7 × VDD
Input Low Voltage, VIL 0.3 × VDD
Input Current 6 1 µA TA = 25°
Input Capacitance 7 pF TA = 25°C
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD, Normal Mode 10 15 mA VDD = 3.3 V
17 25 mA VDD = 5.5 V
IDD, Standby Mode 7 mA VDD = 3.3 V; see the Control Register section
9 mA VDD = 5.5 V
IDD, Power-Down Mode 0.7 5 µA VDD = 3.3 V
1 8 µA VDD = 5.5 V
1
Temperature range for Y version = −40°C to +125°C, typical at +25°C.
2
The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5934.
3
The peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage.
Output Excitation Voltage (V p-p) = [2/3.3] × VDD
4
The dc bias value of the output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage.
Output Excitation Voltage (V p-p) = [2/3.3] × VDD
5
Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of current-
to-voltage amplifier.
6
The accumulation of the currents into Pin 8, Pin 15, and Pin 16.
Rev. E | Page 5 of 31
AD5934 Data Sheet
I2C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted (see Figure 2).
Table 2.
Parameter 1 Limit at TMIN, TMAX Unit Description
fSCL 400 kHz max SCL clock frequency
t1 2.5 µs min SCL cycle time
t2 0.6 µs min tHIGH, SCL high time
t3 1.3 µs min tLOW, SCL low time
t4 0.6 µs min tHD, STA, start/repeated start condition hold time
t5 100 ns min tSU, DAT, data setup time
t6 2 0.9 µs max tHD, DAT, data hold time
0 µs min tHD, DAT, data hold time
t7 0.6 µs min tSU, STA, setup time for repeated start
t8 0.6 µs min tSU, STO, stop condition setup time
t9 1.3 µs min tBUF, bus free time between a stop and a start condition
t10 300 ns max tR, rise time of SDA when transmitting
0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11 300 ns max tF, fall time of SCL and SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS compatible)
250 ns max tF, fall time of SDA when receiving
20 + 0.1 Cb 3 ns min tF, fall time of SCL and SDA when transmitting
Cb 400 pF max Capacitive load for each bus line
1
Guaranteed by design and characterization, not production tested.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) to bridge the undefined falling edge of SCL.
3
Cb is the total capacitance of one bus line in pF. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.
SDA
t9 t3 t10 t11 t4
SCL
t4 t6 t2 t5 t7 t8
t1
Rev. E | Page 6 of 31
Data Sheet AD5934
Rev. E | Page 7 of 31
AD5934 Data Sheet
05325-003
MCLK 8 9 DVDD
NC = NO CONNECT
NOTES:
1. IT IS RECOMMENDED TO TIE ALL SUPPLY
CONNECTIONS (PIN 9, PIN 10, AND PIN 11)
AND RUN FROM A SINGLE SUPPLY BETWEEN
2.7V AND 5.5V.
2. IT IS ALSO RECOMMENDED TO
CONNECT ALL GROUND SIGNALS TOGETHER
(PIN 12, PIN 13, AND PIN 14).
Rev. E | Page 8 of 31
Data Sheet AD5934
25
NUMBER OF DEVICES
NUMBER OF DEVICES
20
20
15
15
10
10
5
5
05325-073
05325-064
0 0
1.92 1.94 1.96 1.98 2.00 2.02 2.04 2.06 0.68 0.70 0.72 0.74 0.76 0.78 0.80 0.82 0.84 0.86
VOLTAGE (V) VOLTAGE (V)
Figure 4. Range 1 Output Excitation Voltage Distribution, VDD = 3.3 V Figure 7. Range 2 DC Bias Distribution, VDD = 3.3 V
30 30
MEAN = 1.4807 MEAN = 0.3827
SIGMA = 0.0252 SIGMA = 0.00167
25 25
NUMBER OF DEVICES
NUMBER OF DEVICES
20 20
15 15
10 10
5 5
05325-077
05325-072
0 0
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 0.370 0.375 0.380 0.385 0.390 0.395 0.400
VOLTAGE (V) VOLTAGE (V)
Figure 5. Range 1 DC Bias Distribution, VDD = 3.3 V Figure 8. Range 3 Output Excitation Voltage Distribution, VDD = 3.3 V
30 30
MEAN = 0.9862 MEAN = 0.3092
SIGMA = 0.0041 SIGMA = 0.0014
25 25
NUMBER OF DEVICES
NUMBER OF DEVICES
20 20
15 15
10 10
5 5
05325-074
05325-066
0 0
0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 0.290 0.295 0.300 0.305 0.310 0.315 0.320
VOLTAGE (V) VOLTAGE (V)
Figure 6. Range 2 Output Excitation Voltage Distribution, VDD = 3.3 V Figure 9. Range 3 DC Bias Distribution, VDD = 3.3 V
Rev. E | Page 9 of 31
AD5934 Data Sheet
30 15.8
MEAN = 0.1982 AVDD1, AVDD2, DVDD CONNECTED TOGETHER
SIGMA = 0.0008 15.3 OUTPUT EXCITATION FREQUENCY = 30kHz
RFB, Z CALIBRATION = 100kΩ
25
14.8
NUMBER OF DEVICES
14.3
20
13.8
IDD (mA)
15 13.3
12.8
10
12.3
11.8
5
05325-088
05325-070
11.3
0 10.8
0.192 0.194 0.196 0.198 0.200 0.202 0.204 0.206 0 2 4 6 8 10 12 14 16 18
VOLTAGE (V) MCLK FREQUENCY (MHz)
Figure 10. Range 4 Output Excitation Voltage Distribution, VDD = 3.3 V Figure 12. Typical Supply Current (IDD) vs. MCLK Frequency
30 0.4
MEAN = 0.1792 VDD = 3.3V
SIGMA = 0.0024 TA = 25°C
0.2 f = 32kHz
25
20
–0.2
15
–0.4
10
–0.6
5 –0.8
05325-028
05325-075
0 –1.0
0.160 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 0.205 0 50 100 150 200 250 300 350 400
VOLTAGE (V) PHASE (Degrees)
Figure 11. Range 4 DC Bias Distribution, VDD = 3.3 V Figure 13. Typical Phase Error
Rev. E | Page 10 of 31
Data Sheet AD5934
TERMINOLOGY
Total System Accuracy Signal-to-Noise Ratio (SNR)
The AD5934 can accurately measure a range of impedance SNR is the ratio of the rms value of the measured output signal
values to less than 0.5% of the correct impedance value for to the rms sum of all other spectral components below the
supply voltages between 2.7 V to 5.5 V. Nyquist frequency. The value for SNR is expressed in decibels.
Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD)
Along with the frequency of interest, harmonics of the fundamental THD is the ratio of the rms sum of harmonics to the fundamental,
frequency and images of these frequencies are present at the where V1 is the rms amplitude of the fundamental, and V2, V3,
output of a DDS device. The spurious-free dynamic range refers V4, V5, and V6 are the rms amplitudes of the second through the
to the largest spur or harmonic present in the band of interest. sixth harmonics. THD is defined as
The wideband SFDR gives the magnitude of the largest harmonic
or spur relative to the magnitude of the fundamental frequency V2 2 + V3 2 + V4 2 + V5 2 + V6 2
THD (dB) = 20 log
in the 0 Hz to Nyquist bandwidth. The narrow-band SFDR V1
gives the attenuation of the largest spur or harmonic in a
bandwidth of ±200 kHz, about the fundamental frequency.
Rev. E | Page 11 of 31
AD5934 Data Sheet
SYSTEM DESCRIPTION
MCLK
DDS
CORE DAC
(27 BITS)
ROUT VOUT
COS SIN
VBIAS
SCL
MICROCONTROLLER I2C
INTERFACE
SDA
Z(ω)
AD5934
REAL IMAGINARY
REGISTER REGISTER
RFB
MAC CORE
(1024 DFT)
MCLK PROGRAMMABLE
WINDOWING GAIN AMPLIFIER
OF DATA VIN
ADC ×5
(12 BITS) ×1
LPF
05325-078
VDD/2
The AD5934 is a high precision, impedance converter system The AD5934 permits the user to perform a frequency sweep with
solution that combines an on-board frequency generator with a a user-defined start frequency, frequency resolution, and number
12-bit, 250 kSPS ADC. The frequency generator allows an external of points in the sweep. In addition, the device allows the user to
complex impedance to be excited with a known frequency. The program the peak-to-peak value of the output sinusoidal signal as
response signal from the impedance is sampled by the on-board an excitation to the external unknown impedance connected
ADC and DFT processed by an on-board DSP engine. The DFT between the VOUT and VIN pins.
algorithm returns both a real (R) and imaginary (I) data-word at Table 5 gives the four possible output peak-to-peak voltages and
each frequency point along the sweep. The impedance magnitude the corresponding dc bias levels for each range for 3.3 V. These
and phase is easily calculated using the following equations: values are ratiometric with VDD. So for a 5 V supply:
Magnitude = R2 + I 2 5. 0
Output Excitation Voltage for Range 1 = 1.98 × =3 V p−p
3. 3
Phase = tan−1(I/R)
5. 0
To characterize an impedance profile Z(ω), generally a frequency Output DC Bias Voltage for Range 1 = 1.48 × = 2.24 V p − p
3. 3
sweep is required such as that shown in Figure 15.
Table 5. Voltage Levels Respective Bias Levels for 3.3 V
Range Output Excitation
No. Voltage Amplitude Output DC Bias Level
1 1.98 V p-p 1.48 V
2 0.99 V p-p 0.74 V
IMPEDANCE (Ω)
performs signal processing, and digitizes the result. The clock for
FREQUENCY (Hz) the DDS is generated from an external reference clock that is
Figure 15. Impedance vs. Frequency Profile provided by the user at MCLK.
Rev. E | Page 12 of 31
Data Sheet AD5934
TRANSMIT STAGE Frequency Increment
As shown in Figure 16, the transmit stage of the AD5934 is made This is a 24-bit word that is programmed to the on-board RAM at
up of a 27-bit phase accumulator DDS core that provides the output Register Address 0x85, Register Address 0x86, and Register Address
excitation signal at a particular frequency. The input to the phase 0x87 (see the Register Map section). The required code loaded to
accumulator is taken from the contents of the start frequency register the frequency increment register is the result of the formula shown in
(see Register Address 0x82, Register Address 0x83, and Register Equation 2, based on the master clock frequency and the required
Address 0x84). Although the phase accumulator offers 27 bits of increment frequency output from the DDS.
resolution, the start frequency register has the three most significant Frequency Increment Code =
bits (MSBs) set to 0 internally; therefore, the user has the ability to
program only the lower 24 bits of the start frequency register.
Required Frequency Increment (2)
R(GAIN) × 2 27
MCLK
PHASE 16
ACCUMULATOR DAC
For example, if the user requires the sweep to have a resolution of
05325-034
(27 BITS) VOUT
VBIAS ROUT
10 Hz and has a 16 MHz clock signal connected to MCLK, the code
Figure 16. Transmit Stage that needs to be programmed is given by
The AD5934 offers a frequency resolution programmable by the Frequency Increment Code =
user down to 0.1 Hz. The frequency resolution is programmed via
a 24-bit word loaded serially over the I2C interface to the frequency
10 Hz
increment register.
16 MHz ≡ 0x00053E
The frequency sweep is fully described by the programming of
three parameters: the start frequency, the frequency increment, 16
and the number of increments. The user programs the value 0x00 to Register Address 0x85, the
Start Frequency value 0x05 to Register Address 0x86, and the value 0x3E to
Register Address 0x87.
This is a 24-bit word that is programmed to the on-board RAM
at Register Address 0x82, Register Address 0x83, and Register Number of Increments
Address 0x84 (see the Register Map section). The required code This is a 9-bit word that represents the number of frequency
loaded to the start frequency register is the result of the formula points in the sweep. The number is programmed to the on-board
shown in Equation 1, based on the master clock frequency and the RAM at Register Address 0x88 and Register Address 0x89 (see the
required start frequency output from the DDS. Register Map section). The maximum number of points that can
Start Frequency Code = be programmed is 511.
For example, if the sweep needs 150 points, the user programs
Required Output Start Frequency (1) the value 0x00 to Register Address 0x88 and the value 0x96 to
× 2 27 Register Address 0x89.
MCLK
16 Once the three parameter values are programmed, the sweep is
For example, if the user requires the sweep to begin at 30 kHz and initiated by issuing a start frequency sweep command to the
has a 16 MHz clock signal connected to MCLK, the code that needs control register at Register Address 0x80 and Register Address
to be programmed is given by 0x81 (see the Register Map section). Bit D2 in the status register
(Register Address 0x8F) indicates the completion of the frequency
measurement for each sweep point. Incrementing to the next
30 kHz
Start Frequency Code = × 2 27 = 0x3D70A3 frequency sweep point is under the control of the user. The measured
16 MHz result is stored in the two register groups that follow: 0x94, 0x95
16 (real data) and 0x96, 0x97 (imaginary data) that should be read
before issuing an increment frequency command to the control
The user programs the value of 0x3D to Register Address 0x82, register to move to the next sweep point. There is the facility to
the value 0x70 to Register Address 0x83, and the value 0xA3 to repeat the current frequency point measurement by issuing a
Register Address 0x84.
repeat frequency command to the control register. This has the
benefit of allowing the user to average successive readings. When
the frequency sweep has completed all frequency points, Bit D3 in
the status register is set, indicating the completion of the sweep.
Once this bit is set, further increments are disabled.
Rev. E | Page 13 of 31
AD5934 Data Sheet
FREQUENCY SWEEP COMMAND SEQUENCE RECEIVE STAGE
The following sequence must be followed to implement a The receive stage comprises a current-to-voltage amplifier,
frequency sweep: followed by a programmable gain amplifier (PGA), antialiasing
1. Enter standby mode. Prior to issuing a start frequency sweep filter, and ADC. The receive stage schematic is shown in Figure 17.
command, the device must be placed in standby mode by The unknown impedance is connected between the VOUT and
issuing an enter standby mode command to the control VIN pins. The first stage current-to-voltage amplifier configuration
register (Register Address 0x80 and Register Address 0x81). means that a voltage present at the VIN pin is a virtual ground
In this mode, the VOUT and VIN pins are connected internally with a dc value set at VDD/2. The signal current that is developed
to ground so there is no dc bias across the external impedance or across the unknown impedance flows into the VIN pin and
between the impedance and ground. develops a voltage signal at the output of the current-to-voltage
converter. The gain of the current-to voltage amplifier is determined
2. Enter initialize mode. In general, high Q complex circuits by a user-selectable feedback resistor connected between Pin 4
require a long time to reach steady state. To facilitate the (RFB) and Pin 5 (VIN). It is important for the user to choose a
measurement of such impedances, this mode allows the user feedback resistance value which, in conjunction with the selected
full control of the settling time requirement before entering gain of the PGA stage, maintains the signal within the linear range
start frequency sweep mode where the impedance of the ADC (0 V to VDD).
measurement takes place. RFB
R
An initialize with start frequency command to the control 5×R
C
register enters initialize mode. In this mode, the impedance
R
is excited with the programmed start frequency but no
measurement takes place. The user times out the required VIN R
settling time before issuing a start frequency sweep command to VDD/2 ADC
05325-038
LPF
the control register to enter the start frequency sweep mode.
3. Enter start frequency sweep mode. The user enters this mode Figure 17. Receive Stage
by issuing a start frequency sweep command to the control
The PGA allows the user to gain the output of the current-to-
register. In this mode, the ADC starts measuring after the
voltage amplifier by a factor of 5 or 1 depending upon the status
programmed number of settling time cycles elapses. The user
of Bit D8 in the control register (see the Register Map section
can program an integer number of output frequency cycles
Register Address 0x80). The signal is then low-pass filtered and
(settling time cycles) to Register Address 0x8A and Register
presented to the input of the 12-bit, 250 kSPS ADC.
Address 0x8B before beginning the measurement at each
frequency point (see Figure 24). The digital data from the ADC is passed directly to the DSP core
of the AD5934 that performs a DFT on the sampled data.
The DDS output signal is passed through a programmable
gain stage to generate the four ranges of peak-to-peak output DFT OPERATION
excitation signals listed in Table 5. The peak-to-peak output A DFT is calculated for each frequency point in the sweep. The
excitation voltage is selected by setting Bit D10 and Bit D9 in AD5934 DFT algorithm is represented by
the control register (see the Control Register section) and is
(x(n)(cos(n) − j sin(n)))
1023
made available at the VOUT pin. X( f ) = ∑
n=0
where:
X(f) is the power in the signal at the Frequency Point f.
x(n) is the ADC output.
cos(n) and sin(n) are the sampled test vectors provided by the
DDS core at the Frequency f.
The multiplication is accumulated over 1024 samples for each
frequency point. The result is stored in two 16-bit registers
representing the real and imaginary components of the result. The
data is stored in twos complement format.
Rev. E | Page 14 of 31
Data Sheet AD5934
IMPEDANCE CALCULATION
MAGNITUDE CALCULATION IMPEDANCE CALCULATION USING GAIN FACTOR
The first step in the impedance calculation for each frequency The next example illustrates how the calculated gain factor
point is to calculate the magnitude of the DFT at that point. derived previously is used to measure an unknown impedance.
For this example, assume that the unknown impedance is 510 kΩ.
The DFT magnitude is given by
After measuring the unknown impedance at a frequency of
Magnitude = R2 + I 2 30 kHz, assume that the real data and imaginary data registers
contain the following data:
where:
R is the real number stored at Register Address 0x94 and Real Data Register = 0xFA3F = −1473 decimal
Register Address 0x95. Imaginary Data Register = 0x0DB3 = +3507 decimal
I is the imaginary number stored at Register Address 0x96 and
Register Address 0x97. Magnitude = ((−1473)2 + (3507)2 ) = 3802.863
For example, assume the results in the real data and imaginary The measured impedance at the frequency point is then given by
data registers are as follows at a frequency point: 1
Impedance =
Real Data Register = 0x038B = 907 decimal Gain Factor × Magnitude
Imaginary Data Register = 0x0204 = 516 decimal 1
= Ω = 509.791 kΩ
Magnitude = (9072 + 5162 ) = 1043.506 515.819273 × 10 −12 × 3802.863
To convert this number into impedance, it must be multiplied GAIN FACTOR VARIATION WITH FREQUENCY
by a scaling factor called the gain factor. The gain factor is Because the AD5934 has a finite frequency response, the gain
calculated during the calibration of the system with a known factor also shows a variation with frequency. This variation in
impedance connected between the VOUT and VIN pins. gain factor results in an error in the impedance calculation over
Once the gain factor is calculated, it can be used in the a frequency range. Figure 18 shows an impedance profile based
calculation of any unknown impedance between the VOUT and on a single-point gain factor calculation. To minimize this error,
VIN pins. the frequency sweep should be limited to as small a frequency
range as possible.
GAIN FACTOR CALCULATION 101.5
VDD = 3.3V
An example of a gain factor calculation follows, with these CALIBRATION FREQUENCY = 60kHz
assumptions: 101.0 TA = 25°C
MEASURED CALIBRATION IMPEDANCE = 100kΩ
PGA gain = ×1
100.0
Current-to-voltage amplifier gain resistor = 200 kΩ
Calibration frequency = 30 kHz
99.5
The typical contents of the real data and imaginary data
registers after a frequency point conversion would then be 99.0 05325-085
Gain Factor =
1
Admittance Impedance
=
Code Magnitude
1
200 kΩ
Gain Factor = = 515.819 × 10 −12
9692.106
Rev. E | Page 15 of 31
AD5934 Data Sheet
2-POINT CALIBRATION GAIN FACTOR SETUP CONFIGURATION
Alternatively, it is possible to minimize this error by assuming When calculating the gain factor, it is important that the receive
that the frequency variation is linear and adjusting the gain stage is operating in its linear region. This requires careful selection
factor with a 2-point calibration. Figure 19 shows an impedance of the excitation signal range, current-to-voltage gain resistor
profile based on a 2-point gain factor calculation. and PGA gain. The gain through the system shown in Figure 20
101.5 is given by
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz Output Excitation Voltage Range ×
101.0 TA = 25°C
MEASURED CALIBRATION IMPEDANCE = 100kΩ Gain Setting Resistor
× PGA Gain
100.5
ZUNKNOWN
IMPEDANCE (kΩ)
CURRENT-TO-VOLTAGE
GAIN SETTING RESISTOR
100.0
RFB
99.5 ZUNKNOWN
VOUT
VIN ADC
05325-089
LPF
99.0 PGA
VDD/2 (×1 OR ×5)
05325-086
98.5
Figure 20. System Voltage Gain
54 56 58 60 62 64 66
FREQUENCY (kHz)
For this example, assume the following system settings:
Figure 19. Impedance Profile Using a 2-Point Gain Factor Calculation VDD = 3.3 V
Gain setting resistor = 200 kΩ
2-POINT GAIN FACTOR CALCULATION ZUNKNOWN = 200 kΩ
This is an example of a 2-point gain factor calculation assuming PGA setting = ×1
the following:
The peak-to-peak voltage presented to the ADC input is 2 V p-p.
Output excitation voltage = 2 V p-p However, had the user chosen a PGA gain of ×5, the voltage
Calibration impedance value, ZUNKNOWN = 100.0 kΩ would saturate the ADC.
PGA gain = ×1
Supply voltage = 3.3 V
GAIN FACTOR RECALCULATION
Current-to-voltage amplifier gain resistor = 100 kΩ The gain factor must be recalculated for a change in any of the
Calibration frequencies = 55 kHz and 65 kHz following parameters:
Typical values of the gain factor calculated at the two calibration • Current-to-voltage gain setting resistor
frequencies read • Output excitation voltage
Gain factor calculated at 55 kHz is 1.031224 × 10−9. • PGA gain
Gain factor calculated at 65 kHz is 1.035682 × 10−9.
Difference in gain factor (ΔGF) is
1.035682 × 10−9 − 1.031224 × 10−9 = 4.458000 × 10−12.
Frequency span of sweep (ΔF) is 10 kHz.
Therefore, the gain factor required at 60 kHz is given by
4.458000E - 12 × 5 kHz + 1.031224 × 10 -9
10 kHz
The required gain factor is 1.033453 × 10−9.
The impedance is calculated as previously described in the
Impedance Calculation section.
Rev. E | Page 16 of 31
Data Sheet AD5934
GAIN FACTOR TEMPERATURE VARIATION Where the gain factor is given by
The typical impedance error variation with temperature is in 1
the order of 30 ppm/°C. Figure 21 shows an impedance profile
Admittance Impedance
with a variation in temperature for 100 kΩ impedance using a Gain Factor = =
Code Magnitude
2-point gain factor calibration.
101.5 The user must calibrate the AD5934 system for a known
impedance range to determine the gain factor before any valid
101.0 +125°C measurement can take place. Therefore, the user must know
the impedance limits of the complex impedance (ZUNKNOWN) for
100.5 the sweep frequency range of interest. The gain factor is simply
IMPEDANCE (kΩ)
Rev. E | Page 17 of 31
AD5934 Data Sheet
Note that it is possible to calculate the gain factor and to calibrate quadrant, the arctangent formula returns a negative angle, and
the system phase using the same real and imaginary component it is necessary to add an additional 180° to calculate the correct
values when a resistor is connected between the VOUT and standard angle. Likewise, when the real and imaginary components
VIN pins of the AD5934, for example, measuring the impedance are both negative, that is, when data lies in the third quadrant,
phase (ZØ) of a capacitor. the arctangent formula returns a positive angle, and it is necessary
The excitation signal current leads the excitation signal voltage to add an additional 180° to calculate the correct standard
across a capacitor by −90 degrees. Therefore, an approximate phase. When the real component is positive and the imaginary
−90 degrees phase difference between the system phase responses component is negative, that is, the data lies in the fourth quadrant,
measured with a resistor and the system phase responses measured the arctangent formula returns a negative angle, and it is necessary
with a capacitive impedance exists. to add an additional 360° to calculate the correct standard phase.
–100
As previously outlined, if the user wants to determine the phase
–90
angle of the capacitive impedance (ZØ), the user first must
determine the system phase response ( ∇system ) and subtract –80
this from the phase calculated with the capacitor connected –70
PHASE (Degrees)
between VOUT and VIN (Φunknown). –60
using a 220 kΩ calibration resistor (RFB = 220 kΩ, PGA = ×1) –40
impedance. –20
One important point to note about the phase formula used to –10
plot Figure 22 is that it uses the arctangent function that returns 0
a phase angle in radians and, therefore, it is necessary to convert 0 15k 30k 45k 60k 75k 90k 105k 120k
05325-091
from radians to degrees. FREQUENCY (Hz)
140
120
Table 6. Phase Angle
100 Real Imaginary Quadrant Phase Angle
80 Positive Positive First 180°
tan −1 (I /R) ×
60 10pF CAPACITOR π
Positive Negative Second 180°
180° + tan −1 (I /R) ×
40
20 π
Negative Negative Third 180°
180° + tan −1 (I /R) ×
0
0 15k 30k 45k 60k 75k 90k 105k 120k
05325-090
π
FREQUENCY (Hz)
Negative Positive Fourth 180°
Figure 22. System Phase Response vs. Capacitive Phase 360° + tan −1 (I /R) ×
π
The phase difference (that is, ZØ) between the phase response
of a capacitor and the system phase response using a resistor is
the impedance phase of the capacitor (ZØ) and is shown in Once the magnitude of the impedance (|Z|) and the impedance
Figure 23. phase angle (ZØ, in radians) are correctly calculated, it is possible
to determine the magnitude of the real (resistive) and imaginary
In addition, when using the real and imaginary values to interpret (reactive) components of the impedance (ZUNKNOWN) by the vector
the phase at each measurement point, care should be taken projection of the impedance magnitude onto the real and
when using the arctangent formula. The arctangent function imaginary impedance axis using the following formulas:
only returns the correct standard phase angle when the sign of
the real and imaginary values are positive, that is, when the The real component is given by
coordinates lie in the first quadrant. The standard angle is |ZREAL| = |Z| × cos(ZØ)
taken counterclockwise from the positive real x-axis. If the sign The imaginary component is given by
of the real component is positive and the sign of the imaginary
component is negative, that is, the data lies in the second |ZIMAG| = |Z| × sin(ZØ)
Rev. E | Page 18 of 31
Data Sheet AD5934
N
Y
05325-047
PROGRAM THE AD5934
INTO POWER-DOWN MODE.
Rev. E | Page 19 of 31
AD5934 Data Sheet
REGISTER MAP
Table 7.
Register Name Register Address Bits Function
Control 0x80 D15 to D8 Read/write
0x81 D7 to D0 Read/write
Start Frequency 0x82 D23 to D16 Read/write
0x83 D15 to D8 Read/write
0x84 D7 to D0 Read/write
Frequency Increment 0x85 D23 to D16 Read/write
0x86 D15 to D8 Read/write
0x87 D7 to D0 Read/write
Number of Increments 0x88 D15 to D8 Read/write
0x89 D7 to D0 Read/write
Number of Settling Time Cycles 0x8A D15 to D8 Read/write
0x8B D7 to D0 Read/write
Status 0x8F D7 to D0 Read only
Real Data 0x94 D15 to D8 Read only
0x95 D7 to D0 Read only
Imaginary Data 0x96 D15 to D8 Read only
0x97 D7 to D0 Read only
Rev. E | Page 20 of 31
Data Sheet AD5934
Control Register Decode START FREQUENCY REGISTER (REGISTER
Initialize with Start Frequency ADDRESS 0x82, REGISTER ADDRESS 0x83,
This command enables the DDS to output the programmed
REGISTER ADDRESS 0x84)
start frequency for an indefinite time. Initially, it is used to The start frequency register contains the 24-bit digital
excite the unknown impedance. When the output unknown representation of the frequency from where the subsequent
impedance has settled after a time determined by the user, the frequency sweep is initiated. For example, if the user requires
user must initiate a start frequency sweep command to begin the sweep to start from a frequency of 30 kHz using a 16.0 MHz
the frequency sweep. clock, the user must program the value 0x3D to Register Address
0x82, the value 0x70 to Register Address 0x83, and the value
Start Frequency Sweep
0xA3 to Register Address 0x84. Doing this ensures the output
In this mode, the ADC starts measuring after the programmed frequency starts at 30 kHz.
number of settling time cycles has elapsed. The user has the
The start frequency code is
ability to program an integer number of output frequency cycles
(settling time cycles) to Register Address 0x8A and Register Start Frequency Code =
Address 0x8B before the commencement of the measurement at
each frequency point (see Figure 24).
30 kHz × 2 27 ≡ 0x3D70A3
Increment Frequency 16 MHz
The increment frequency command is used to step to the next 16
frequency point in the sweep. This usually happens after data The default value of the start frequency register upon reset is as
from the previous step is transferred and verified by the DSP. follows: D23 to D0 are not reset at power-up. After the reset
When the AD5934 receives this command, it waits for the command, the contents of this register are not reset.
programmed number of settling time cycles before beginning
the ADC conversion process. FREQUENCY INCREMENT REGISTER (REGISTER
ADDRESS 0x85, REGISTER ADDRESS 0x86,
Repeat Frequency
REGISTER ADDRESS 0x87)
There is the facility to repeat the current frequency point
The frequency increment register contains a 24-bit representation
measurement by issuing a repeat frequency command to the
of the frequency increment between consecutive frequency
control register. This command allows users to average
points along the sweep. For example, if the user requires an
successive readings.
increment step of 30 Hz using a 16.0 MHz clock, the user must
Power-Down Mode program the value 0x00 to Register Address 0x85, the value
The default state at power-up of the AD5934 is power-down 0x0F to Register Address 0x86, and the value 0xBA to Register
mode. The control register contains the code 1010,0000,0000,0000 Address 0x87.
(0xA000). In this mode, both the output and input pins, VOUT The formula for calculating the frequency increment is given by
and VIN, are connected internally to GND.
Frequency Increment Code =
Standby Mode
This mode powers up the part for general operation. In standby 10 Hz 27
mode, the VIN and VOUT pins are internally connected to GND. 16 MHz × 2 ≡ 0x00053E
Reset 16
A reset command allows the user to interrupt a sweep. The start The user programs the value 0x00 to Register Address 0x85,
frequency, number of increments, and frequency increment the value 0x05 to Register Address 0x86, and the value 0x3E to
register contents are not overwritten. An initialize with start Register Address 0x87.
frequency command is required to restart the frequency sweep
The default value of the frequency increment register upon reset
command sequence.
is as follows: D23 to D0 are not reset at power-up. After the reset
Output Voltage Range command, the contents of this register are not reset.
The output voltage range allows the user to program the
excitation voltage range at VOUT.
PGA Gain
The PGA gain allows the user to amplify the response signal
into the ADC by a multiplication factor of ×5 or ×1.
Rev. E | Page 21 of 31
AD5934 Data Sheet
NUMBER OF INCREMENTS REGISTER (REGISTER into the number of settling time cycles register can be increased
ADDRESS 0x88, REGISTER ADDRESS 0x89) by a factor of 2 or 4, depending on the status of Bits D10 to D9.
The five most significant bits, D15 to D11, are don’t care bits.
The default value of the number of increments register upon
The maximum number of output cycles that can be programmed is
reset is as follows: D8 to D0 are not reset at power-up. After a
511 × 4 = 2044 cycles. For example, consider an excitation signal of
reset command, the contents of this register are not reset.
30 kHz, the maximum delay between the programming of this
Table 11. Number of Increments Register frequency and the time that this signal is first sampled by the
Reg Addr Bits Description Function Format ADC is ≈ 511 × 4 × 33.33 µs = 68.126 ms. The ADC takes 1024
0x88 D15 to D9 Don’t care Read or Integer samples, and the result is stored as real data and imaginary data in
write number Register Address 0x94 to Register Address 0x97. The conversion
D8 Number of Read or stored process takes approximately 1 ms using a 16.777 MHz clock.
increments write in binary
format STATUS REGISTER (REGISTER ADDRESS 0x8F)
0x89 D7 to D0 Number of Read or Integer The status register is used to confirm that particular measurement
increments write number tests have been successfully completed. Each of the bits from D7 to
stored
in binary
D0 indicate the status of a specific functionality of the AD5934.
format Bit D0 and Bit D4 to Bit D7 are treated as don’t care bits; these
bits do not indicate the status of any measurement.
This register determines the number of frequency points in the The status of Bit D1 indicates the status of a frequency point
frequency sweep. The number of frequency points is represented impedance measurement. This bit is set when the AD5934
by a 9-bit word, D8 to D0. D15 to D9 are don’t care bits. This completes the current frequency point impedance measurement.
register in conjunction with the start frequency register and the This bit indicates that there is valid real data and imaginary data
frequency increment register determine the frequency sweep in Register Address 0x94 to Register Address 0x97. This bit is
range for the sweep operation. The maximum number of reset on receipt of a start frequency sweep, increment frequency,
increments that can be programmed is 511. repeat frequency, or reset command. This bit is also reset at
NUMBER OF SETTLING TIME CYCLES REGISTER power-up.
(REGISTER ADDRESS 0x8A, REGISTER ADDRESS The status of Bit D2 indicates the status of the programmed
0x8B) frequency sweep. This bit is set when all programmed increments
The default value of the number of settling time cycles register to the number of increments register are complete. This bit is
upon reset is as follows: D10 to D0 are not reset at power-up. reset at power-up and on receipt of a reset command.
After a reset command, the contents of this register are not reset.
Table 12. Status Register 0x8F
This register determines the number of output excitation cycles Control Word Description
allowed to passthrough the unknown impedance after receipt of 0000 0001 Reserved
a start frequency sweep, increment frequency, or repeat frequency 0000 0010 Valid real/imaginary data
command, before the ADC is triggered to perform a conversion 0000 0100 Frequency sweep complete
of the response signal. The number of settling time cycles register 0000 1000 Reserved
value determines the delay between a start frequency sweep/ 0001 0000 Reserved
increment frequency/repeat frequency command and the time 0010 0000 Reserved
an ADC conversion commences. The number of cycles is 0100 0000 Reserved
represented by a 9-bit word, D8 to D0. The value programmed 1000 0000 Reserved
Rev. E | Page 22 of 31
Data Sheet AD5934
Valid Real/Imaginary Data REAL AND IMAGINARY DATA REGISTERS (16 BITS—
This bit is set when data processing for the current frequency REGISTER ADDRESS 0x94, REGISTER
point is finished, indicating real/imaginary data available for ADDRESS 0x95, REGISTER ADDRESS 0x96,
reading. The bit is reset when a start frequency sweep/increment REGISTER ADDRESS 0x97)
frequency/repeat frequency DDS command is issued. In addition, These registers contain a digital representation of the real and
this bit is reset to 0 when a reset command is issued to the imaginary components of the impedance measured for the
control register. current frequency point. The values are stored in 16-bit, twos
Frequency Sweep Complete complement format. To convert this number to an actual
This bit is set when data processing for the last frequency point in impedance value, the magnitude, (Real 2 + Imaginary 2 ) , must
the sweep is complete. This bit is reset when a start frequency be multiplied by an admittance/code number (called a gain
sweep command is issued to the control register. This bit is also factor) to give the admittance and the result inverted to give the
reset when a reset command is issued to the control register. impedance. The gain factor varies for each ac excitation
voltage/gain combination.
The default value upon reset: these registers are not reset at
power-up or on receipt of a reset command. Note that the data
in these registers is only valid if Bit D1 in the status register is
set, indicating that the processing at the current frequency point
is complete.
Rev. E | Page 23 of 31
AD5934 Data Sheet
SCL
SDA 0 0 0 1 1 0 1 R/W D7 D6 D5 D4 D3 D2 D1 D0
05325-048
START CONDITION ACKNOWLEDGED BY ACKNOWLEDGED BY
BY MASTER SLAVE ADDRESS BYTE AD5934 REGISTER ADDRESS MASTER/SLAVE
Rev. E | Page 24 of 31
Data Sheet AD5934
WRITING/READING TO THE AD5934 8. The master asserts a stop condition on SDA to end the
The I2C interface specification defines several different protocols transaction.
05325-049
for different types of read and write operations. This section S SLAVE W A REGISTER A REGISTER A P
ADDRESS ADDRESS DATA
describes the protocols used in the AD5934. The figures in this
Figure 26. Writing Register Data to Register Address
section use the abbreviations shown in Table 14.
In the AD5934, the write byte protocol is also used to set a
Table 14. I2C Abbreviation Table pointer to a register address (see Figure 27). This protocol is
Abbreviation Condition used for a subsequent single-byte read from the same address,
S Start block read, or block write starting at that address.
P Stop
To set a register pointer, the following sequence is applied:
R Read
W Write 1. The master device asserts a start condition on SDA.
A Acknowledge 2. The master sends the 7-bit slave address followed by the
A No acknowledge write byte/command byte write bit (low).
3. The addressed slave device asserts an acknowledge on SDA.
User Command Codes 4. The master sends a pointer command code (see Table 15, an
The command codes in Table 15 are used for reading/writing to address pointer = 1011 0000).
the interface. They are explained in detail in this section but are 5. The slave asserts an acknowledge on SDA.
grouped within Table 15 for easy reference. 6. The master sends a data byte (a register address to where
the pointer is to point).
Table 15. Command Codes
Command Code 7. The slave asserts an acknowledge on SDA.
Code Name Code Description 8. The master asserts a stop condition on SDA to end the
1010 0000 Block This command is used when writing transaction.
Write multiple bytes to the RAM; see the POINTER REGISTER
05325-050
SLAVE
Block Write section. S
ADDRESS
W A COMMAND A ADDRESS A P
1011 0000 TO POINT TO
1010 0001 Block This command is used when reading
Read multiple bytes from RAM/memory; see Figure 27. Setting Address Pointer to Register Address
the Block Read section. BLOCK WRITE
1011 0000 Address This command enables the user to set
Pointer the address pointer to any location in In this operation, the master device writes a block of data to a
the memory; the data contains the slave device (see Figure 28). The start address for a block write
address of the register to which the must previously have been set. In the case of the AD5934, this is
pointer should be pointing. done by setting a pointer to set the register address.
1. The master device asserts a start condition on SDA.
Write Byte/Command Byte
2. The master sends the 7-bit slave address followed by the
In this operation, the master device sends a byte of data to the
write bit (low).
slave device. The write byte can either be a data byte write to a
Register Address or it can be a command operation. To write data 3. The addressed slave device asserts an acknowledge on SDA.
to a register, the command sequence is as follows (see Figure 26): 4. The master sends an 8-bit command code (1010 0000) that
tells the slave device to expect a block write.
1. The master device asserts a start condition on SDA.
5. The slave asserts an acknowledge on SDA.
2. The master sends the 7-bit slave address followed by the
6. The master sends a data byte that tells the slave device the
write bit (low).
number of data bytes to be sent to it.
3. The addressed slave device asserts an acknowledge on SDA. 7. The slave asserts an acknowledge on SDA.
4. The master sends a register address. 8. The master sends the data bytes.
5. The slave asserts an acknowledge on SDA. 9. The slave asserts an acknowledge on SDA after each data byte.
6. The master sends a data byte. 10. The master asserts a stop condition on SDA to end the
transaction.
7. The slave asserts an acknowledge on SDA.
05325-051
Rev. E | Page 25 of 31
AD5934 Data Sheet
READ OPERATIONS Block Read
The AD5934 uses two I2C read protocols: the receive byte and In this operation, the master device reads a block of data from a
the block read. slave device (see Figure 30). The start address for a block read
must previously have been set by setting the address pointer.
Receive Byte
In the AD5934, the receive byte protocol is used to read a single 1. The master device asserts a start condition on SDA.
byte of data from a register address whose address has previously 2. The master sends the 7-bit slave address followed by the
been set by setting the address pointer. write bit (low).
In this operation, the master device receives a single byte from a 3. The addressed slave device asserts an acknowledge on SDA.
slave device as follows (see Figure 29): 4. The master sends a command code (1010 0001) that tells
the slave device to expect a block read.
1. The master device asserts a start condition on SDA.
5. The slave asserts an acknowledge on SDA.
2. The master sends the 7-bit slave address followed by the 6. The master sends a byte-count data byte that tells the slave
read bit (high). how many data bytes to expect.
3. The addressed slave device asserts an acknowledge on SDA. 7. The slave asserts an acknowledge on SDA.
4. The master receives a data byte. 8. The master asserts a repeat start condition on SDA. This is
required to set the read bit high.
5. The master asserts a no acknowledge on SDA (the slave
needs to check that master has received data). 9. The master sends the 7-bit slave address followed by the
read bit (high).
6. The master asserts a stop condition on SDA and the
10. The slave asserts an acknowledge on SDA.
transaction ends.
11. The master receives the data bytes.
05325-052
S SLAVE R A REGISTER A P
ADDRESS DATA 12. The master asserts an acknowledge on SDA after each
Figure 29. Reading Register Data data byte.
13. A no acknowledge is generated after the last byte to signal
the end of the read.
14. The master asserts a stop condition on SDA to end the
transaction.
05325-053
S SLAVE W A BLOCK A NUMBER A S SLAVE R A BYTE 0 A BYTE 1 A BYTE 2 A P
ADDRESS READ BYTES READ ADDRESS
Rev. E | Page 26 of 31
Data Sheet AD5934
TYPICAL APPLICATIONS
MEASURING SMALL IMPEDANCES The value of the output series resistance depends upon the
The AD5934 is capable of measuring impedance values up to selected output excitation range at VOUT and has a tolerance
10 MΩ if the system gain settings are chosen correctly for the from device to device like all discrete resistors manufactured in
impedance subrange of interest. a silicon fabrication process. Typical values of the output series
resistance are outlined in Table 16.
If the user places a small impedance value (≤500 Ω over the
sweep frequency of interest) between the VOUT and VIN pins, Table 16. Output Series Resistance (ROUT) vs. Excitation Range
it results in an increase in signal current flowing through the Parameter Value (Typ) Output Series Resistance Value
impedance for a fixed excitation voltage in accordance with Range 1 2 V p-p 200 Ω typical
Ohm’s law. The output stage of the transmit side amplifier Range 2 1 V p-p 2.4 kΩ typical
available at the VOUT pin may not be able to provide the Range 3 0.4 V p-p 1.0 kΩ typical
required increase in current through the impedance. To have a Range 4 0.2 V p-p 600 Ω typical
unity gain condition about the receive side I-V amplifier, the
Therefore, to accurately calibrate the AD5934 to measure small
user needs to have a similar small value of feedback resistance
impedances, it is necessary to reduce the signal current by
for system calibration as outlined in the Gain Factor Setup
attenuating the excitation voltage sufficiently and also account
Configuration section. The voltage presented at the VIN pin is
hard biased at VDD/2 due to the virtual earth on the receive for the ROUT value and factor it into the gain factor calculation
side I-V amplifier. The increased current sink/source (see the Gain Factor Calculation section).
requirement placed on the output of the receive side I-V Measuring the ROUT value during device characterization is
amplifier may also cause the amplifier to operate outside of the achieved by selecting the appropriate output excitation range at
linear region. This causes significant errors in subsequent VOUT and sinking and sourcing a known current at the pin
impedance measurements. (for example, ±2 mA) and measuring the change in dc voltage.
The output series resistance can be calculated by measuring the
The value of the output series resistance, ROUT, (see Figure 31)
at the VOUT pin must be taken into account when measuring inverse of the slope (that is, 1/slope) of the resultant I-V plot.
small impedances (ZUNKNOWN), specifically when the value of A circuit that helps to minimize the effects of the issues
the output series resistance is comparable to the value of the previously outlined is shown in Figure 31. The aim of this
impedance under test (ZUNKNOWN). If the ROUT value is unac- circuit is to place the AD5934 system gain within its linear
counted for in the system calibration (that is, the gain factor range when measuring small impedances by using an additional
calculation) when measuring small impedances, there is an external amplifier circuit along the signal path. The external
introduced error into any subsequent impedance measurement amplifier attenuates the peak-to-peak excitation voltage at
that takes place. The introduced error depends on the relative VOUT by a suitable choice of resistors (R1 and R2), thereby
magnitude of the impedance being tested compared to the value reducing the signal current flowing through the impedance and
of the output series resistance. minimizing the effect of the output series resistance in the
2V p-p impedance calculations.
TRANSMIT SIDE
OUTPUT AMPLIFIER R1 In the circuit shown in Figure 31, ZUNKNOWN recognizes the
ROUT VOUT R2 output series resistance of the external amplifier which is
DDS
typically much less than 1 Ω with feedback applied depending
VDD
AD8531 upon the op amp device used (for example, AD820, AD8641,
20kΩ
AD820 AD8531) as well as the load current, bandwidth, and gain.
VDD/2 AD8641
RFB
20kΩ 1µF
AD8627 The key point is that the output impedance of the external
RFB
amplifier in Figure 31 (which is also in series with ZUNKNOWN)
has a far less significant effect on gain factor calibration and
PGA I-V VIN ZUNKNOWN subsequent impedance readings in comparison to connecting
05324-148
Rev. E | Page 27 of 31
AD5934 Data Sheet
For example, if the user measures ZUNKNOWN that is known to The gain factor calculated is for a 100 Ω resistor connected
have a small impedance value within the range of 90 Ω to between VOUT and VIN, assuming the output series resistance
110 Ω over the frequency range of 30 kHz to 32 kHz, the of the external amplifier is small enough to be ignored.
user may not be in a position to measure ROUT directly in When biasing the circuit shown in Figure 31, note that the
the factory/lab. Therefore, the user may choose to add on receive side of the AD5934 is hard-biased about VDD/2 by
an extra amplifier circuit like that shown in Figure 31 to the design. Therefore, to prevent the output of the external
signal path of the AD5934. The user must ensure that the amplifier (attenuated AD5934 Range 1 excitation signal) from
chosen external amplifier has a sufficiently low output series saturating the receive side amplifiers of the AD5934, a voltage
resistance over the bandwidth of interest in comparison to the equal to VDD/2 must be applied to the noninverting terminal
impedance range under test (for an op amp selection guide, see of the external amplifier.
http://www.analog.com/opamps). Most amplifiers from Analog
Devices have a curve of closed-loop output impedance vs. BIOMEDICAL: NONINVASIVE BLOOD IMPEDANCE
frequency at different amplifier gains to determine the output MEASUREMENT
series impedance at the frequency of interest. When a known strain of a virus is added to a blood sample that
The system settings are as follows: already contains a virus, a chemical reaction takes place whereby
the impedance of the blood under certain conditions changes.
VDD = 3.3 V
By characterizing this effect across different frequencies, it is
VOUT = 2 V p-p possible to detect a specific strain of virus. For example, a strain
R2 = 20 kΩ of the disease exhibits a certain characteristic impedance at one
frequency but not at another, resulting in the need to sweep
R1 = 4 kΩ
different frequencies to check for different viruses. The AD5934,
Gain setting resistor = 500 Ω with its 27-bit phase accumulator, allows for subhertz frequency
ZUNKNOWN = 100 Ω tuning.
PGA setting = ×1 The AD5934 can be used to inject a stimulus signal through the
blood sample via a probe. The response signal is analyzed and
To attenuate the excitation voltage at VOUT, choose a ratio
the effective impedance of the blood is tabulated. The AD5934
of R1/R2. With the values of R1 = 4 kΩ and R2 = 20 kΩ,
is ideal for this application because it allows the user to tune to
attenuate the signal by 1/5th of 2 V p-p = 400 mV. The
the specific frequency required for each test.
maximum current flowing through the impedance is 400 mV/
90 Ω = 4.4 mA. 1 16
ADuC702x
The system is subsequently calibrated using the usual method 2 15
TOP VIEW
(Not to Scale)
with a midpoint impedance value of 100 Ω, a calibration AD5934
3
TOP VIEW 14
resistor, and a feedback resistor at a midfrequency point in the RFB (Not to Scale)
sweep. The dynamic range of the input signal to the receive side 4 13
I-V gain resistor at the RFB pin. For example, increasing the I-V
6 11
gain setting resistor at the RFB pin increases the peak-to-peak
signal presented to the ADC input from 400 mV (RFB = 100 Ω) PROBE
7 10
7V
ADR43x
2 6
0.1µF 10µF
05325-057
Rev. E | Page 28 of 31
Data Sheet AD5934
SENSOR/COMPLEX IMPEDANCE MEASUREMENT ELECTRO-IMPEDANCE SPECTROSCOPY
The operational principle of a capacitive proximity sensor is The AD5934 has found use in the area of corrosion monitoring.
based on the change of a capacitance in a RLC resonant circuit. Corrosion in a metal, such as aluminum, which is used in air
This leads to changes in the resonant frequency of the RLC craft and ships, requires continuous assessment because the metal
circuit, which can be evaluated as shown Figure 33. is exposed to a wide variety of conditions, such as temperature and
It is first required to tune the RLC circuit to the area of resonance. moisture. The AD5934 offers an accurate and compact solution
At the resonant frequency, the impedance of the RLC circuit is for this type of measurement compared to the large and expensive
at a maximum. Therefore, a programmable frequency sweep existing units on the market.
and tuning capability is required, which is provided by the AD5934. Mathematically the corrosion of a metal is modeled using a RC
RESONANT CHANGE IN network that consists of a resistance, RS, in series with a parallel
FREQUENCY RESONANCE DUE
TO APPROACHING
resistor and capacitor, RP and CP. A system metal would typically
OBJECT have values as follows: RS is 10 Ω to 10 kΩ, RP is 1 kΩ to 1 MΩ,
and CP is 5 µF to 70 µF.
PROXIMITY IMPEDANCE (Ω)
0.1 kHz to 100 kHz every 10 minutes and download the results
FREQUENCY (Hz)
back to a control unit. To achieve system accuracy from the
Figure 33. Detecting a Change in Resonant Frequency 0.1 kHz to 1 kHz region, the system clock needs to be scaled
An example of the use of this type of sensor is for a train proximity down from the 16.776 MHz nominal clock frequency to 500 kHz,
measurement system. The magnetic fields of the train approaching typically. The clock scaling can be achieved digitally using an
on the track change the resonant frequency to an extent that can external direct digital synthesizer, such as the AD9834, as a
be characterized. This information can be sent back to a mainframe programmable divider that supplies a clock signal to MCLK
system to show the train location on the network. and that can be controlled digitally by the nearby microprocessor.
Rev. E | Page 29 of 31
AD5934 Data Sheet
Rev. E | Page 30 of 31
Data Sheet AD5934
OUTLINE DIMENSIONS
6.50
6.20
5.90
16 9
5.60
5.30
5.00 8.20
7.80
1 7.40
8
1.85 0.25
2.00 MAX 1.75 0.09
1.65
8° 0.95
0.05 MIN 0.38
SEATING 4° 0.75
COPLANARITY 0.22 PLANE
0.65 BSC 0° 0.55
0.10
060106-A
COMPLIANT TO JEDEC STANDARDS MO-150-AC
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD5934YRSZ −40°C to +125°C 16-Lead Shrink Small Outline Package (SSOP) RS-16
AD5934YRSZ-REEL7 −40°C to +125°C 16-Lead Shrink Small Outline Package (SSOP) RS-16
1
Z = RoHS Compliant Part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Rev. E | Page 31 of 31