Department of Electronics & Communication Engineering

Name of the Course :VLSI Design Course Code: 18EC72

Sem/Sec: VII ‘A&B’ Faculty Name: Jayalakshmi N

MODULE-4
1. Briefly explain logic ‘1’ transfer in dynamic NMOS logic.[K3] MODULE 4 PPT
SLIDE 24, PG 224
2. Discuss dynamic bootstrapping technique with neat diagram and waveform.[K3]
MODULE 4 PPT SLIDE 27, PG 231
3. Design a three stage enhancement load dynamic shift register with ratioed logic.[K4]
MODULE 4 PPT SLIDE 37,PG 236
4. With necessary circuit diagram explain 3-bit dynamic shift register with depletion
load.[K4] MODULE 4 PPT SLIDE 32,PG 243
5. Explain dynamic CMOS logic gate with an example.[K2] MODULE 4 PPT SLIDE
38,PG 238
6. Explain cascading problem in dynamic CMOS logic with neat figure.[K2]
MODULE 4 PPT SLIDE 40,PG 239
7. Explain the General structure of Ratioless synchronous dynamic logic with relevant
diagram.[K2] MODULE 4 PPT SLIDE 36,PG 237