Department of Electronics & Communication Engineering

Name of the Course :VLSI Design Course Code: 18EC72

Sem/Sec: VII ‘A&B’ Faculty Name: Jayalakshmi N

MODULE-2
1. Derive the expression for threshold voltage reduction in short channel effect.[K4]
TB 102
2. With a neat sketch explain Narrow Channel Effects in MOS transistor.[K2] TB 108
3. Briefly explain effect of full scaling on oxide capacitance, drain current and power
dissipation.[K3] TB 100
4. Derive the expression for equivalent large signal capacitance in junction capacitances.
[K3]

MODULE-3
1. Sketch a 3-input NAND gate with transistor widths chosen to achieve effective rise
and fall resistance equal to that of a unit inverter(R). Annotate the gate with its gate
and diffusion capacitances. [K3] PPT PG 33
2. Explain RC delay model with equivalent circuit of an inverter.[K2] PG 29
3. Define Elmore delay. Compute the Elmore delay for V out in second order RC system.
[K2] PPT PG 45
4. With a neat logic diagram explain delay in multistage logic networks.[K2]PPT PG 66
5. Design a 3-stage decoder and calculate logical effort, path effort, stage effort and
delay.[K4] PPT PG 86
6. Design a circuit to compute F=AB+CD using NANDs and NORs with bubble
pushing.[K4] TB 356
7. Draw the logic symbol and schematic diagram for an expression AOI21 and calculate
its logical effort and parasitic delay.[K3] PG 25 module 3 AZ Documents
8. Discuss asymmetric gates and skewed gates. [K2] PG 29 module 3 AZ Documents
or PPT PG 101
9. With a neat circuit diagram and waveform explain Domino gates.[K2] PPT PG 120
10. Briefly explain Cascode voltage switch logic with neat diagrams.[K2] PG 39 module
3 AZ Documents