Introduction to Microprocessors

Lecture # 12
Interrupts
CH 14
80X86 IBM PC and Compatible Computers
Assembly Language, Design, and Interfacing

CH9
8086 INTERRUPT from Fundamentals of Digital_ Logic_ and_
Microcomputer_ Design

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Outline
What is interrupt? 

Types of interrupt 

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Polling vs. Interrupt
instruction

While studying, I’ll Input Memory

check the bucket every Device
5 minutes to see if it is
already full so that I can
transfer the content of
the bucket to the drum.

P

POLLING
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Polling vs. Interrupt
instruction

I’ll just study. When the Input Memory

speaker starts playing Device
music it means that the
bucket is full. I can
then transfer the
content of the bucket to
the drum.

Interrupt
request
P
INTERRUPT
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What is Interrupt

• The meaning of ‘interrupts’ is to break the sequence

of operation
• An interrupt is an external event which informs the
CPU that a device needs its service.
• Interrupts are useful when interfacing I/O devices at
relatively low data transfer rates, such as keyboard
inputs
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 8088/86 INTERRUPTS
•An interrupt is an external event which informs the CPU
that a device needs its service.

• In the 8086/88 there are a total of 256 interrupts: INT 00, INT 01, ...,
INT FF (sometimes called TYPEs ).
• When an interrupt is executed,

the microprocessor automatically saves:

» the flag register (FR),
» the instruction pointer (IP),
» code segment register (CS) on the stack,

– and goes to a fixed memory location.

– In 80x86 , the memory location to which an interrupt goes is always four times
the value of the interrupt number.
– For example, INT 03 will go to address 0000CH (4x3=12 =0CH).

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 Flag Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R R R R OF DF IF TF SF ZF U AF U PF U CF

R = reserved
U = undefined
OF = overflow flag
DF = direction flag
IF = interrupt flag
TF = trap flag
SF = sign flag
ZF = zero flag
AF = auxiliary carry flag
PF = parity flag
CF = carry flag

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CE 444 Computer Interfacing

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Mohamad Al Azawi
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8 alazawi@yu.edu.jo
 Interrupt vector table

INT number Physical Address Logical Address

lNT00 00000 0000:0000

INT01 00004 0000:0004
INT02 00008 0000:0008

. . .
. . .
. . .
. . .
INTFF 003FC 0000:03FC

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CE 444 Computer Interfacing

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Mohamad Al Azawi
Habeeb
10 alazawi@yu.edu.jo
 Interrupt service routine (ISR)
• For every interrupt there must be a program associated with it.
• When an interrupt is invoked it is asked to run a program to perform a
certain service.
• This program is commonly referred to as an interrupt service routine
(ISR), or interrupt handler
• where is the address of the interrupt service routine?
• As can be seen from the above Table , for every interrupt there are
allocated four bytes of memory in the interrupt vector table
– Two bytes are for the IP
– and two are for the CS of the ISR.

• These four memory locations provide addresses of the interrupt

service routine for which the interrupt was invoked.
• Thus the lowest 1024 bytes (256 x 4 =1024) of memory space are set
aside for the interrupt vector table and must not be used for any other
function.
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Example
• Find the physical and logical addresses in the interrupt vector table
associated with:
• (1) INT12H (2)INT8
• Solution:
1. The physical addresses for INT12H are 00048H through 0004BH
since (4 x 12H = 48H).
• That means the physical memory locations 48H, 49H, 4AH, and
4BH are set aside for the CS and IP of the ISR belonging to
INT12H. The logical address is 0000:0048H - 0000:004BH.
2. For INT8, we have 8 x 4 =32 =20H; therefore, memory addresses
00020H, 00021H, 00022H,and 00023H in the interrupt vector table
hold the CS:IP of the INT8 ISR.
• The logical address is 0000:0020H – 0000:0023H.

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Intel's List of Designated Interrupts for the 8086/88
CS
0003FC IP } INT FF

CS
00018 IP } INT 06

CS
00014 IP } INT 05

CS
00010 IP } INT 04 signed number overflow

CS
0000C IP } INT 03 breakpoint

CS
00008 IP } INT 02 NMI

CS
00004 IP } INT 01 single-step

CS
00000 IP } INT 00 divide error

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Difference between INT and CALL instructions
CALL
• can jump to any location within •
the 1 megabyte address range of
the 8088/86 CPU,
• used by the programmer in the
sequence of instructions in the
program
• cannot be masked (disabled),
• automatically saves only CS:IP
of the next instruction on the
stack
• At the end of subroutine that
has been called by the "CALL"
instruction, the RET is the last
instruction
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INT
goes to a fixed memory location in the
interrupt vector table to get the
address of the interrupt service
routine.
• externally activated hardware interrupt
can come in at any time, requesting
the attention of the CPU
• belonging to externally activated
hardware interrupts can be masked
• saves FR (flag register) in addition to
CS:IP of the next instruction.
• the last instruction in the interrupt
service routine (ISR) for "INT nn" is
the instruction IRET (interrupt return).
The difference is that RETF pops CS,
IP off the stack but the IRET pops off
the FR (flag register) in addition to CS
and IP.
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 Flag Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R R R R OF DF IF TF SF ZF U AF U PF U CF

R = reserved
U = undefined
OF = overflow flag
DF = direction flag
IF = interrupt flag
TF = trap flag
SF = sign flag
ZF = zero flag
AF = auxiliary carry flag
PF = parity flag
CF = carry flag

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• IF: The interrupt flag is used to mask (ignore) any hardware
interrupt that may come in from the INTR pin.
• If IF = 0, all hardware interrupt requests through INTR are
ignored.
• This has no effect on interrupts coming from the NMI pin or
"INT nn" instructions.
• The instruction CLI (clear interrupt flag) will make IF = 0.
• To allow interrupt requests through the INTR pin, this flag
must be set to one (IF = 1).
• The STI (set interrupt flag) instruction can be used to set IF
to 1.
• The trap flag (TF) is explained below when "INT 01", the
single-step interrupt, is discussed.
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 Processing interrupts
• When the 8088/86 processes any interrupt (software or hardware), it
goes through the following steps:
1. The flag register (FR) is pushed onto the stack and SP is
decremented by two, since FR is a 2-byte register.
2. IF (interrupt enable flag) and TF (trap flag) are both cleared (IF = 0 and
TF = 0). This masks (causes the system to ignore) interrupt requests
from the INTR pin and disables. Depending on the nature of the
interrupt procedure, a programmer can unmask the INTR pin by the
STI instruction.
3. The current CS is pushed onto the stack and SP is decremented by 2.
4. The current IP is pushed onto the stack and SP is decremented by 2.
5. The INT number (type) is multiplied by 4 to get the physical address
of the location within the vector table to fetch the CS and IP of the
interrupt service routine.
6. From the new CS:IP, the CPU starts to fetch and execute instructions
belonging to the ISR program.
7. The last instruction of the interrupt service routine must be IRET, to
get IP, CS, and FR back from the stack and make the CPU run the
code where it left off.

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 Functions associated with
1NT 00 to INT 04
Predefined interrupt

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 INT 00 (divide error)
• This interrupt belongs to the category of interrupts referred to as
conditional or exception interrupts.
• Internally, they are invoked by the microprocessor whenever there are
conditions (exceptions) that the CPU is unable to handle.
• One such situation is an attempt to divide a number by zero. Since the
result of dividing a number by zero is undefined, and the CPU has no
way of handling such a result, it automatically invokes the divide error
exception interrupt.
• INT 00 is invoked by the microprocessor whenever there is an attempt
to divide a number by zero.
• In the IBM PC and compatibles, the service subroutine for this interrupt
is responsible for displaying the message "DIVIDE ERROR" on the
screen if a program such as the following is executed

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 MOV AL,92 ;AL=92
SUB CL,CL ;CL=0
DIV CL ;92/0=undefined result
• INT 0 is also invoked if the quotient is too large to fit into the
assigned register when executing a DIV instruction. Look at the
following case:

MOV AX,0FFFFH ;AX=FFFFH

MOV BL,2 ;BL=2
DIV BL
• 65535/2 =32767 larger than 255 .maximum capacity of AL
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 INT 01 (single step)
• In executing a sequence of instructions, there is often a need to examine the
contents of the CPU's registers and system memory.
• This is often done by executing the program one instruction at a time and then
inspecting registers and memory.
• This is commonly referred to as single-stepping, or performing a trace.
• Intel has designated INT 01 specifically for implementation of single-stepping.
• To single-step, the trap flag (TF), D8 of the flag register, must be set to 1.
• Then after execution of each instruction, the 8086/88 automatically jumps to
physical location 00004 to fetch the 4 bytes for CS:IP of the interrupt service
routine, whose job is, among other things, to dump the registers onto the
screen.
• Now the question is, how is the trap flag set or reset?
• Although Intel has not provided any specific instruction for this purpose (unlike
IF, which uses STI and CLI instructions to set or reset), one can write a simple
program to do that.

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 Setting and Resetting TF
• The following shows two methods of making TF= 0. The first is:
1. the first method is:
PUSHF
POP AX
AND AX,1111111011111111B
PUSH AX
POPF
2. the second method is:
PUSHF
MOV BP,SP
AND [BP]+0,1111111011111111B
POPF

• Recall that TF is D8 of the flag register. The analysis of the above two
programs is left to the you as a practice.
• To make TF =1, one simply uses the OR instruction in place of the
AND instruction above.
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INT 02 (nonmaskable interrupt)

• All Intel 80x86 microprocessors have a pin designated

NMI.
• It is an active-high input. Intel has set aside INT 02 for
the NMI interrupt.
• Whenever the NMI pin of the 80x86 is activated by a high
(5 V) signal, the CPU jumps to physical memory location
00008 to fetch the CS:IP of the interrupt service routine
associated with NMI.

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 INT 03 (breakpoint)
• To allow implementation of breakpoints in software engineering,
Intel has set aside INT 03 solely for that purpose.
• Whereas in single-step mode, one can inspect the CPU and system
memory after the execution of each instruction, a breakpoint is used
to examine the CPU and memory after the execution of a group of
instructions.
• In recent years, some very powerful software debuggers have been
written using INT 01 and INT 03.
• Even in writing simple programs on the IBM PC, the use of single-
step (trace) and breakpoints (INT 03) is indispensable.
• One interesting point about INT 03 is the fact that it is a 1-byte
instruction. This is in contrast to all other interrupt instructions of the
form "INT nn", which are 2-byte instructions.

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INT 04 (signed number overflow)

• This interrupt is invoked by a signed number overflow

condition.
• There is an instruction associated with this, INT0 (interrupt
on overflow).
• If the instruction INT0 is placed after a signed number
arithmetic or logic operation such as IMUL or ADD, the
CPU will activate INT 04 if OF = 1.
• In cases where OF = 0, the INT0 instruction is not
executed but is bypassed and acts as a NOP (no
operation) instruction.

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 Example
MOV AL,DATA1
MOV BL,DATA2
ADD AL,BL ;add BL to AL
INT 0h

Suppose that
» DATA1 =+64 =0100 0000
» DATA2 =+64 =0100 0000.

• The INT0 instruction will be executed and the 8086/88 will jump to
physical location 00010H, the memory location associated with INT
04.
• The carry from D6 to D7 causes the overflow flag to become 1.
• +64 01000000
• +64 01000000
• +128 1000 0000 OF=1 and the result is not +128
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 • The above incorrect result causes OF to be set to 1.
• INT0 causes the CPU to perform "INT 04" and jump to
physical location 00010H of the vector table to get the
CS:IP of the service routine.
• Suppose that the data in the above program was DATA1
=+64 and DATA2 =+17.
• In that case, OF would become 0;
• the INT0 is not executed and acts simply as a NOP (no
operation) instruction.

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Hardware interrupts
three pins in the 80x86 are associated with hardware interrupts

INTR, (interrupt request),

NMI (nonmaskable interrupt),
INTA (interrupt acknowledge) OUTPUT.

 INTR is an input signal into the CPU which can be masked

(ignored) and unmasked through the use of instructions
CLI and STI.
 NMI, which is also an input signal into the CPU, cannot be
masked and unmasked using instructions CLI and STI, and
for this reason it is called nonmaskable interrupt.
 INTR and NMI are activated externally by putting 5 V on
the pins of NMI and INTR of the 80x86 microprocessor.

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  When either of these interrupts is activated, the
80x86 will:
 finishes the instruction which it is executing,
 pushes FR and the CS:IP of the next instruction onto the
stack,
 then jumps to a fixed location in the interrupt vector table
and fetches the CS:IP for the interrupt service routine (ISR)
associated with that interrupt.
 At the end of the ISR, the IRET instruction causes the CPU
to:
 get (pop) back its original FR and CS:IP from the stack,
 thereby forcing the CPU to continue at the instruction where it left
off when the interrupt came in.

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 •Intel has embedded "INT 02" into the 80x86
microprocessor to be used only for NMI.

 Whenever the NMI pin is activated, the CPU will go to memory location 00008 to get the
address (CS:IP) of the interrupt service routine (ISR) associated with NMI.
 Memory locations 00008,00009, 0000A, and 0000B contain the 4 bytes of CS:IP of the ISR
belonging to NMI.
 In contrast, this is not the case for the other hardware pin, INTR. There is no specific
location in the vector table assigned to INTR.
 The reason is that INTR is used to expand the number of hardware interrupts and should
be allowed to use any "INT nn" which has not been previously assigned.
 The 8259 programmable interrupt controller (PIC) chip can be connected to
INTR to expand the number of hardware interrupts up to 64.
 In the case of the IBM PC, one Intel 8259 PIC chip is used to add a total of 8 hardware
interrupts to the microprocessor.
 IBM PC/AT, PS/2 80286, 80386, 80486, and Intel Pentium computers use two 8259 chips
to allow up to 16 hardware interrupts.

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Interrupt Structure of 8086/8088 Microprocessor
An 8086 interrupt can come from any one the three sources:

1-External Signal ( Hard ware interrupt) :

NMI ( nonmaskable interrupt or
INTR ( Interrupt request)

2-Special Instruction ( Software interrupt):

INT n instructions to execute special program n= 0-255

•Predefined interrupts ( Dedicated Interrupt) : Interrupt like

•Type0 : Divide by Zero
•Type1: Single Step Interrupt this interrupt enabled by setting
TF, there is no instruction to set or reset TF. The
following programs set andRaafat
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TF
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•Program to set TF
PUSH F ; PUSH FLAGS INTO STACK
MOV BP,SP ; COPY SP INTO BP
OR WORD PTR[BP],0100H ; SET TF BIT
POP F ; RESTORE FLAG
REGISTER
•Program to reset TF
PUSH F ; PUSH FLAGS REGISTER
MOV BP,SP ; COPY SP INTO BP
AND WORD PTR[BP],0FEFFH ; RESET TF BIT
POP F ; RESTORE FLAG REGISTER

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•Type 2: Non-Maskable Interrupt, this interrupt cannot be disabled by
any software instruction. This interrupt is activated by low-high
transition on 8086 NMI input.
•Type3: Breakpoint, this interrupt is produced by execution INT3
instruction
•Type4: Overflow interrupt, this occurs when overflow flag OF is set as
result of an arithmetic operation on two signed numbers.

INTERRUPT PRIORITY
Divide Error ( Type0) 0 HIGHEST
NMI 1
INTR 2
Single –Step (Type 1) 3 LOWEST

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Example
Write an assembly program to Shift LED 1 bit left when a push button on INTR input is pressed.
. MODEL TINY
CODE SEGMENT
ASSUME CS:CODE, DS:CODE
START: CLI ; DISABLE INTERRUPT
MOV SP,4000H ; SETUP OF STACK POINTER
MOV AX,CS
MOV DS,AX ; DEFINE DS SEGMENT
MAIN: MOV AX,0 ; INTILIZE ES SEGMENT
MOV ES,AX
MOV BX,40H*4 ; SETUP VECTOR ADDRESS OF
MOV ES:WORD PTR[BX],OFFSET ISR_1
;IR0(TYPE 40)
MOV ES:2[BX],CS ; IP OF ISR -1and CS of ISR-1
STI ; ENABLE FOR IR0 INTERRUPT
RPT: NOP ; EXECUTE MAIN PROGRAM
NOP
JMP RPT
ISR_1: ROL AL,1 ; LED rotate left
MOV DX,0FFFEH ; DEFINE OUTPUT PORT
OUT DX,AL
MOV CX,0FFFH ; SETUP DELAY COUNTER
LOOP $
IRET ;RETURN FROM INTERRUPT
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Self Study
From Book: The 80x86 IBM PC and Compatible
Computer Volume II
Chapter 14
Exercise
Problem from Ch 14.1

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