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IGBT gate driver IC with full-bridge output stage using a modified standard
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Article  in  Microelectronics Journal · August 2004

DOI: 10.1016/j.mejo.2004.04.008 · Source: DBLP

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 Microelectronics Journal 35 (2004) 659–666
www.elsevier.com/locate/mejo

IGBT gate driver IC with full-bridge output stage

using a modified standard CMOS process
A. Pérez-Tomás*, X. Jordà, P. Godignon, J.L. Gálvez, M. Vellvehı́, J. Millán
Centre Nacional de Microelectrònica (IMB-CNM-CSIC), Campus UAB, 08193 Barcelona, Spain
Received 4 March 2004; revised 22 April 2004; accepted 26 April 2004
Available online 8 June 2004

Abstract
This paper discusses the benefits of a full-bridge output stage on integrated IGBT gate drive circuits. This full-bridge topology allows
obtaining positive and negative gate voltages using a single floating power supply. Short circuit protections have also been integrated,
implementing an original soft shutdown process after an IGBT short circuit fault. The monolithic integration is based on an innovative high-
voltage CMOS technology for power integrated circuits, using a standard low cost CMOS technology, requiring only one extra processing
step. Lateral power N- and P-MOS transistors have been optimized using 2D simulators attending both specific on-resistance and breakdown
voltage in order to optimize the full-bridge output stage. The IGBT driver has been experimentally tested, producing ^ 15 V gate-to-emitter
voltage, and supplying the current peaks required by the 600 V IGBT switching processes. The driver characteristic response times are
adapted to work at high switching frequency (. 25 kHz) with high value of capacitive loads (3.7 nF).
q 2004 Elsevier Ltd. All rights reserved.
Keywords: IGBT driver; Power integrated circuit; CMOS; LDMOS

1. Introduction protection circuitry [1 – 4]. In most of these designs, the

Correct switching of MOS controlled vertical power
devices (VDMOS and IGBT structures) can be controlled
through the charge and discharge process of the parasitic
input capacitance of the MOS structure. The circuits
performing this task are called gate drive circuits or drivers.
They act as a buffer stage between the logic control signal
and the gate-to-emitter voltage of the power device. In
addition, due to their proximity with the power device, they
are often in charge of additional protection tasks against
short-circuit, over-temperature, etc. The critical part of the
gate drive circuits is the output stage, responsible for
supplying the positive and negative current peaks associated
with the charge and discharge of the MOS structure
capacitance. These current peaks can easily reach 0.5 A
for standard IGBTs or VDMOS transistors with input
capacitances of several nano-farads, under supply voltages
as high as 15 V. In this sense, various processes have been
proposed to implement monolithic IGBT gate drivers with
* Corresponding author. Tel.: þ34-93-594-77-00; fax: þ 34-93-580-
14-96.
E-mail address: amador.perez@cnm.es (A. Pérez-Tomás).
0026-2692/$ - see front matter q 2004 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2004.04.008
implementation has been carried out using different
technology steps from the low-voltage controller circuits.
Nevertheless, an existing low-voltage technology should
desirably be used for the fabrication of Power Integrated
Circuits (PICs) in order to reduce development efforts and
time. One of the main advantages of this approach is that all
the existing standard cells and libraries can be used in
designing the low voltage parts of the circuit [5]. Significant
efforts have been carried out in the past years to develop
CMOS compatible high-voltage devices and integrate them
into existing low-voltage VLSI processes [6 –9]. Depending
on the specific device structure to be implemented, extra
masks and processing steps have to be added to the
conventional CMOS process. These extra processes are
generally additional ion implantation steps or the implemen-
tation of buried layers in the epitaxy. This paper discusses a
method to monolithically integrate an IGBT gate driver with
an original full-bridge output stage and short circuit
protections using a standard CMOS technology, with only
one modified fabrication step. The IGBT gate drive circuit
schematic will be explained in Section 2, including
validations of the more innovative aspects with discrete
devices. The high-voltage CMOS devices proposed for
660 A. Pérez-Tomás et al. / Microelectronics Journal 35 (2004) 659–666
the integration of the output stage are presented in Section 3.
Finally, Section 4 discusses the implementation details of
the whole driver and the experimental results obtained with
the fabricated prototypes, including true operation con-
ditions of IGBT transistors.
2. The IGBT gate driver structure
The present work is based on a gate drive circuit
developed for water-cooled IGBT power modules showing
half-bridge configuration [10]. In the considered power
modules, one thermistor was placed close to each IGBT
switch. This temperature information was used to provide
an over-temperature protection of the module during high-
current operation processes, water-cooling system failure,
etc. Under power supply voltage protection and shoot-
through protection were also implemented giving a very
high level of system reliability. Fig. 1 shows the core of
the proposed circuit schematic. The input signal IN is
validated by the mentioned protection signals with an AND
enable gate. The VCE collector-to-emitter voltage is
continuously monitored through diode D1 with a very
simple circuit in order to detect a short circuit condition
(simultaneous high values of collector current and voltage)
using the desaturation method. Nevertheless, the most
innovative aspect of the proposed driver is the full-bridge
output stage. Traditional IGBT drivers show a push– pull
output stage in order to provide the positive and negative
gate current peaks, charging and discharging the input
capacitance of the IGBT during the switching processes.
However, this topology needs two power supplies if positive
and negative gate-to-emitter voltages have to be applied.
Fig. 1. The IGBT driver schematic.
This is an important point, because off-state negative gate
bias significantly increases the switching speed and the
converter reliability [11]. With a full-bridge topology at the
driver output stage, positive gate-to-emitter voltage during
the on-state and negative voltage during the off-state can be
obtained with a single power supply depending on the state
of each switch of the bridge. In addition, the full-bridge
configuration gives an additional benefit to the short circuit
protection subcircuit. When the VCE monitoring circuit
detects a short circuit condition, automatically turns off the
IGBT reducing the gate voltage from the positive gate
voltage value to zero and finally from zero to the negative
gate voltage, instead of switching it from its positive value
to the negative one. This ‘soft’ turn-off feature can be easily
implemented using the full-bridge output stage topology.
Fig. 2 compares a standard short-circuit recovery process
and the soft turn-off one for a commercial 600 V-20 A
IGBT, showing a 30% reduction of the collector-to-emitter
voltage peak when a 260 A short-circuit current is reduced
to zero.
The core of the proposed gate drive circuit (Fig. 1
schematic) has been integrated using a standard CMOS
process with minor modifications. This circuit consists,
from the technological point of view, of a high-voltage
(36 V) output full-bridge, digital logic control circuits and
RC analog delay cells. The aim of the proposed driver
prototype was to evaluate for the first time the behavior of
an integrated full-bridge output stage.
2.1. The output stage
With a full-bridge topology at the driver output stage,
positive gate-to-emitter voltage during the on-state, þVDD ;
 A. Pérez-Tomás et al. / Microelectronics Journal 35 (2004) 659–666
Fig. 2. Effect of the soft shutdown on the VCE peak voltage during a short circuit recovery.
and negative voltage during the off-state, 2VDD ; can be
obtained with a single power supply depending on the state
of each switch of the bridge [12]. The high voltage level
þVDD at the IGBT gate is achieved with the transistor
combination (Fig. 1) M1/M4-on and M2/M3-off. Analo-
gously, the voltage 2VDD is obtained with the M2/M3-on
and M1/M4-off combination, furthermore with M1/M3-on
and M2/M4-on, a 0 V IGBT gate bias can be obtained. This
characteristic will have an interesting application as will be
explained further on. The proposed output stage circuit
consists of four high-voltage transistors designed with the
modified standard CMOS process and four inverters
connected to each gate of these transistor. External turn-
on and turn-off gate resistors are needed in order to match
with the IGBT switching speed and EMI requirements.
A power supply external decoupling capacitance is also
essential in order to supply the turn-on and turn-off
gate current peaks, avoiding excessive gate-to-emitter
voltage reduction immediately after turn-on or turn-off
processes [10].
2.2. The short circuit protections
The IGBT shows a natural current limitation in its active
zone. This behavior is usually taken in advantage to
implement protection circuits in order to turn-off the
IGBT when short circuit conditions appear (simultaneous
high collector current and high collector-to-emitter voltage
levels). These protection circuits have to be fast enough to
avoid thermal destruction of the IGBT (typical response
times are below 10 ms). The short circuit protection cell is
formed by the components R4 ; D1 ; DZ and R1 2 C1 (Fig. 1).
Analyzing the static transfer function between VCE and VSC
(a short circuit alarm voltage) and the different polarizations
of the diodes D1 and DZ ; three different operation modes are
obtained (A, B, C) considering for simplicity R4 ¼ R1 : Fig. 3
shows the static transfer function between VCE and VSC : VZ
(the voltage fixed by DZ ) can be used as a design parameter
for the purpose of modulating the short circuit response,
because it is related with the S-C (Short-Circuit logic signal)
activation through the ISC inverter threshold voltage. When
661
the IGBT gate voltage is high (around VDD ) and the device
goes from the saturation operating zone (A)
(VCE ¼ VCEsat , 2 – 3 V) to the active one (C)
(VCE q VCEsat ), the Zener diode DZ turns on and generates
a short circuit logic signal S-C at the ISC inverter input. The
transient evolution of this voltage ðVSC Þ can be calculated in
the short circuit condition using expression (1):
 
1
VSC ðtÞ ¼ ðVDD 2 VZ Þ 1 2 e2ð2=R1 C1 Þt ð1Þ
2
During the normal switching process of the IGBT an
undesired transient activation of the monitoring circuit can
occur due to simultaneous high IC and VCE values across the
IGBT, and the filter constituted by R1 and C1 has to be
added. Accurate tuning of this filter allows to delay a few
micro-seconds (short circuit activation time tSC ) the short
circuit protection process. Two additional switch configur-
ations of the full-bridge output stage can apply zero volts
between gate and emitter of the IGBT. They correspond to
M1/M3-on and M2/M4-off or M1/M3-off and M2/M4-on.
This allows introducing a slow or soft turn-off sequence
when a short circuit condition is detected, by reducing the
gate voltage from þ VDD to zero and then from zero to 2VDD ;
Fig. 3. VSC static transfer function for different values of Zener voltage
ðVZ Þ:
662 A. Pérez-Tomás et al. / Microelectronics Journal 35 (2004) 659–666
Fig. 4. IGBT driver Spice simulation during short circuit condition.
instead of reducing it sharply from þ VDD to 2VDD : The
gradual reduction of Vout (IGBT gate-to-emitter voltage)
decreases the collector current speed ðdIC =dtÞ; as well as the
collector voltage peak associated with dIC =dt and the wiring
stray inductance. In short circuit conditions, this peak can
easily reach the IGBT breakdown voltage producing
irreversible damages. When the short circuit logic signal
S-C goes high, the flip –flop is reset. Immediately, the input
signal of inverters I1 and I2 is disabled through the
corresponding NAND gates, since I3 and I4 inverters are
disabled later due to the R2 2 C2 2 D2 delay cell via a
Schmitt trigger inverter. During this short period of time
(soft shutdown time tSS ) associated with a delay between VE
and VG voltages in Fig. 1, the gate-to-emitter IGBT voltage
is zero. When I1, I2, I3 and I4 are disabled, the IGBT gate
voltage is fixed to 2 VDD until the next input pulse arrives.
Spice simulations studying the whole driver functionality
have been used in order to optimize the values of R1 ; C1 ; R2 ;
C2 ; VZ and R4 : R1 ; D1 and DZ values are related with the
short circuit activation time ðtSC Þ by means of the time
dependence aimed in Eq. (1). It can be considered that the
short circuit activation takes place when the VSC ðtÞ voltage
exceeds the threshold voltage ðVTSC Þ of the inverter ISC :
Thus, the following relation can be derived:
 
R C 0:5·½VDD 2 VZ 
tSC < 1 1 ln ð2Þ
2 0:5·½VDD 2 VZ  2 VTSC
Analogously, R2 and C2 constitute the soft turn-off delay
cell yielding tSS < R2 C2 : The values chosen for the
integration are, R1 ¼ R4 ¼ 30 kV, C1 ¼ C2 ¼ 300 pF,
VZ ¼ 8 V and R2 ¼ 10 kV. With such values the expected
values for the short circuit activation time and soft shutdown
time are tSC ¼ 1:5 ms and tSS ¼ 3 ms, respectively. In Fig. 4,
a transient simulated short circuit detection induced by VCE
over voltage signal is shown. The soft shutdown process
(Vout going from 15 to 0 V and from 0 to 2 15 V) can be
observed immediately after the short circuit activation filter
is enabled.
3. High-voltage devices for the driver output stage
Due to the low output current capability and premature
voltage breakdown of the low voltage logic devices, high-
voltage and high-current output devices are required in the
output stage for the correct turn-off/turn-on operation. These
power devices must supply the current peaks required to
charge and discharge the IGBT input capacitance during the
turn-on and turn-off processes, respectively. Furthermore,
IGBT driver ICs operate typically from 15 V DC supplies
and conventional CMOS devices are not indicated for this
purpose. This voltage is used to ensure the operation of the
IGBT in its saturation zone, with minimum forward voltage
drop.
An accurate optimization is essential for the design of
power integrated circuits and power discrete devices. This
optimization has been done using electrical simulation
tools (TMA-MEDICI simulator) attending to two magni-
tudes: BV (breakdown voltage) and Ron (specific on-
resistance). The goal in the design of power integrated
devices is to minimize Ron achieving adequate breakdown
voltage, thus maintaining large safe operating area. The
main achievements in the high-voltage MOSFET devices
performance have been produced with the structural
modification of their drain, with the aim to enhance the
blocking voltage and the reduction of parasitic effects or
hot carriers injection [13]. Using simulation results, two
main structures have been chosen for their integration in a
test power integrated circuit, due to their superior
electrical characteristics [14]. For the N-MOSFET
(Fig. 5), an asymmetric LDD (Lightly Doped Drain)
 A. Pérez-Tomás et al. / Microelectronics Journal 35 (2004) 659–666
Fig. 5. N-MOSFET structure with asymmetric lightly doped drain (LDD-
nMOSFET).
nMOSFET structure maximizes the breakdown voltage,
maintaining Ron at a reasonably low level. Simulations
indicate that the major geometrical variables that define
the voltage handling capability (breakdown voltage and
punch-through voltage) and the specific on-resistance are
the channel length Lch ; and the drift length LD : In
addition, the polysilicon layer over the LOCOS oxide
ðLkg Þ acts as a field plate and modifies the electric field
within the n-drift region. For the P-MOSFET (Fig. 6) an
asymmetric ED (Extended Drain) pMOSFET is chosen
due to its electrical isolation from the epitaxy and low Ron
value when compared with LDD solutions. The extended
drain structure for the ED-pMOSFET has been achieved
introducing a low doped P-type implantation between the
drain of the transistor and the end of the channel region.
This produces an increase of the voltage blocking
Fig. 6. P-MOSFET structure with asymmetric extended drain (ED-
pMOSFET).
663
Table 1
LDD-nMOSFET experimental characteristics
BV (V) Ron (mV cm2) Vth (V)
(Vg ¼ 5 V)
LD ¼ 6 mm=Lkg ¼ 2:5 mm 126 11.8 1.1
LD ¼ 10 mm=Lkg ¼ 2:5 mm 129 12.3 1.2
LD ¼ 20 mm=Lkg ¼ 2:5 mm 161 13.5 1.2
capability due to the formation of a less abrupt junction
between the drain diffusion and the N-well of the device.
A standard 2.5 mm double-well technology, with two
polysilicon layers and two metal layers optimized for
CMOS low-voltage (5 V) digital applications has been
used for this work. The power IC has been fabricated on
bulk n-type substrate where a 18 mm-thick p-type
epitaxial layer has been grown. LDD-nMOSFET devices
are completely integrated within the standard CMOS
process. Only one additional mask compared to the
standard CMOS process has been required to implant
the ED-pMOSFET extended drain (NA ¼ 5 £ 1016 cm23)
in order to manufacture the high-voltage transistors.
However, as this process step is done without thermal
treatments, the other impurity profiles near the silicon
surface are not affected. Therefore, the low voltage
CMOS transistor parameters are preserved and thus, the
high-voltage devices can be integrated with the already
optimized low-voltage analog-digital library cells.
The LDD-nMOSFET has been designed with the CMOS
technology whose main parameters are the drift length LD ;
the channel length Lch and the gate-field-plate length Lkg :
Experimental results are shown in Table 1. For the ED-
pMOSFETs, a breakdown voltage of BV ¼ 36 V has been
achieved, basically independent of the channel length or the
extended drift length (LED) for a fixed doping level of the
extended drain (NA ¼ 5 £ 1016 cm23) as shown in Table 2.
The extended drain doping level has been chosen attending
to a trade-off between the breakdown voltage and the
specific on-resistance values supplied by the simulation
results. In both devices (LDD-nMOSFET and ED-pMOS-
FET) a threshold voltage of 1 V (2 1 V) has been obtained.
It corresponds to the expected (simulated) values and is
similar to the low signal CMOS threshold voltage. Optimal
structures from Tables 1 and 2 have been selected to
integrate the output stage of the driver.
Table 2
ED-pMOSFET experimental characteristics
BV (V) Ron (mV cm2) Vth (V)
(Vg ¼ 25 V)
L ¼ 4 mm=LED ¼ 5 mm 36 2.0 21.0
L ¼ 5 mm=LED ¼ 5 mm 36 3.5 21.0
L ¼ 9 mm=LED ¼ 5 mm 36 13.5 21.1
664 A. Pérez-Tomás et al. / Microelectronics Journal 35 (2004) 659–666
Fig. 7. A photograph of the IGBT gate driver.
4. Driver implementation and test
The IGBT gate driver low-voltage components have
been integrated using a standard CMOS cell library. The
high-voltage components have been implemented specifi-
cally for this issue as explained in previous sections. The
high current capability and the low resistance of the output
LDMOS have been achieved using multifinger structures
increasing the effective channel width of the device. The
inverters connected to the gate of the output full-bridge
transistors have to supply relatively high current peaks to
the gate of the high-voltage MOSFETs. These inverters,
have been implemented with series combination of a
common source transistor with resistive load, with a
standard inverter implemented in complementary high-
voltage CMOS process, forming a 5– 15 V buffer. To
enhance current capability, five additional high-voltage
inverters have been connected in parallel. Fig. 7 shows the
proposed gate driver IC layout. As it can be inferred from
the figure, the output stage implemented with the high-
voltage CMOS process, consists of a number of high-current
cells for high-current capability and occupies the most part
of the total chip area.
The IGBT gate driver output stage has been implemented
using the optimal high-voltage structures experimentally
inferred. For the high-current/high-voltage n-channel tran-
sistors, a multifinger LDD-nMOSFET configuration has
been chosen, with Lch ¼ 4:5mm, LD ¼ 6 mm and
Lkg ¼ 2:5 mm (BV ¼ 126 V Ron ¼ 11:8 mV cm 2 ). The
effective channel width is W ¼ 16:2 mm. Analogously, for
the p-channel transistors, a multifinger ED-pMOSFET
(W ¼ 34:2 mm) structure has been selected, with
L ¼ 4 mm, LED ¼ 5 mm, NA ¼ 5 £ 1016 cm 23
2
(BV ¼ 36 V Ron ¼ 2 mV cm . The full-bridge output
stage transistors experimental measurements, show a
conduction resistance of 5.7 and 1.8 V at 15 V gate bias
for the LDD-nMOSFETs and ED-pMOSFETs, respectively.
These resistance values must be added to the driver external
gate resistors (Rgon and Rgoff ), in order to evaluate the total
effective gate resistance. Threshold voltage of 1.1 and
2 0.9 V have been obtained for the n-channel and p-channel
transistors, respectively, in accordance with the designed
values.
The IGBT driving capability of the implemented circuit
is presented in Fig. 8. The IGBT driver IC output stage
operates from a 15 V DC supply. The output signals have
been obtained with Rgon ¼ Rgoff ¼ 10 V and with a load
capacitor of Cin ¼ 1 nF emulating the IGBT gate to be
driven. The logic input signal (IN) is a 0 –5 V square wave,
at 25 kHz and 60% duty cycle. In such conditions, that
roughly emulates real IGBT operation, the full-bridge peak
output current reaches 300 mA. To measure the IGBT driver
output stage dynamic response, the same test configuration
Fig. 8. The driver switching response with 1 nF capacitive load.
 A. Pérez-Tomás et al. / Microelectronics Journal 35 (2004) 659–666
Table 3
IGBT driver dynamic response characteristics
tr (ns) tf (ns) tdH (ns)
Cin ¼ 1 nF 472.1 449.9 84.1
Fig. 9. Buck converter schematic for operational conditions test.
has been used, where Rgon ¼ Rgoff ¼ 10 V and Cin ¼ 1 nF.
A statistical average of the characteristic switching times
are presented in Table 3. The output voltage is measured
again between the load capacitor terminals. The character-
istic times experimentally obtained, are comparable with
those reported for other integrated IGBT drivers, such as [2],
allowing IGBT operation at high switching frequencies
(. 25 kHz). True operational conditions have also been
demonstrated. An IXSH40N60 IGBT (Cin ¼ 3:7 nF) is
controlled by the proposed driver in a buck converter
configuration (Fig. 9) supplied by VA ¼ 300 V. The exper-
imental waveforms are presented in Fig. 10 with an
inductive load of LL ¼ 2 mH, a stray inductance of
Ls ¼ 70 nH, RURG 8060 freewheel diode (FWD) and
Rgon ¼ Rgoff ¼ 33 V.
The detection of the short circuit and the soft shutdown
features allowed by the full-bridge configuration, have been
also successfully tested. The short circuit activation time
(tSC ¼ 1:4 ms, VZ ¼ 8 V) and the soft shutdown time ðtSS ¼
3:5 msÞ have been determined experimentally in good
agreement with the integrated values of R1 =R4 =C1 =VZ and
R2 =C2 : As it is shown in Fig. 11, the experimental output
signals VG and VE (see Fig. 1), have been delayed
Fig. 10. Output driver stage response in a buck converter configuration
supplied by 300 V.
665
tdL (ns)
104.2
Fig. 11. Characteristics signals, showing the correct short circuit operation
response.
the expected values of tSC and ðtSC þ tSS Þ; respectively,
due to a short circuit signal (VCE rise). The next IGBT gate
turn-on after the short circuit activation takes place when
VCE signal decreases with the IGBT in saturation zone and
IN signal rises to high value, minimizing the recovery and
dysfunction elapsed time.
5. Conclusions
A monolithic IGBT driver has been integrated with short
circuit protections, low voltage control logic and an
innovative full-bridge output stage operating at 15 V,
allowing IGBT operation at high switching frequency
(. 20 kHz). A low-cost CMOS based technology suitable
for power integrated circuits (36 V – 160 V/1A) has been
slightly modified to implement the driver integrated circuit.
This full-bridge topology allows obtaining positive and
negative IGBT gate voltages using a single floating power
supply and the implementation of a soft shutdown process
following a short circuit fault can be easily implemented.
High-voltage n-channel (LDD-nMOSFET) and p-channel
(ED-pMOSFET) transistors have been designed, optimized
and integrated for the full-bridge output stage. Only one
process step and one mask level has to be added to the
standard CMOS process to implement ED-pMOSFET
devices. The LDD-nMOSFET devices are completely
integrated within the standard CMOS process. The IGBT
driver has been experimentally tested producing ^ 15 V
gate-to-emitter voltage and supplying the current peaks
required by the IGBT switching processes. The driver
characteristic response times are adapted to work at high
switching frequency (. 25 kHz) with high capacitive loads
(3.7 nF). The short circuit protection function has also been
successfully tested as well as the capability of the driver to
operate in true operation conditions.
Acknowledgements
This work was supported by the Comisión Interminister-
ial de Ciencia y Tecnologı́a (CICYT) under projects no.
TIC2000-1403-C03-01 and TIC2002-04458-C02-02.
666 A. Pérez-Tomás et al. / Microelectronics Journal 35 (2004) 659–666
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