Lecture 9 and Lecture 10

Examples
Example 1: How the microprocessor 8086 accessing an aligned word-
data in 8086-based memory system. (Explain and draw)

Solution:
• For even-addressed (aligned) words, only one bus-cycle is needed to access
the word, as both low and high banks are activated at the same time using
A0=’0’ and ̅̅̅̅̅̅
BHE=’0’
• Note that during this bus-cycle, all 16-bit data is transferred via D0 to D15 of
the data bus.
 Lecture 9 and Lecture 10
Examples

Example 2: How the microprocessor 8086 accessing a word-data in

memory location DS: FFFA in 8086-based memory system. (Explain
and draw)

Solution:
• For even-addressed (aligned) words, only one bus-cycle is needed to access
the word, as both low and high banks are activated at the same time using
̅̅̅̅̅̅=’0’
A0=’0’ and BHE
• Note that during this bus-cycle, all 16-bit data is transferred via D0 to D15 of
the data bus.
 Lecture 9 and Lecture 10
Examples
Example 3: How the microprocessor 8086 accessing a word-data in
memory location FFFD in 8086-based memory system. (Explain and
draw)

Solution:

• For odd-addressed (unaligned) words (with odd P.A of the LSB), two
bus-cycles are required to access the Word-data.
• During the 1st bus-cycle, odd addressed LSB of the word is accessed
from the High-memory -bank via D8 to D15 of data bus.
• During 2nd bus-cycle, P.A. is auto-incremented to access the even
address MSB of the word from the Low bank via D0 to D7.
• Note that A0 and BHE
̅̅̅̅̅̅ signals are reset accordingly to enable the
required memory bank.
 Lecture 9 and Lecture 10
Examples
Example 4: Draw the timing diagram of 8086 maximum mode
memory-write operation. The required signals: IO/M, MN/MX, S2-S0,
DT/R, Physical Address, ALE, WR, DEN.

Solution:
• To complete the maximum-mode memory-write bus-cycle, the required control
signals with appropriate active logic levels are :
• IO/M
̅ = ‘logic 0’, to select memory interface

• MN/MX
̅̅̅̅ = ‘logic 0’, to select maximum-mode of operation

• DT/R
̅ = ‘logic 1’, to activate the data-transmit mode of ‘Data-bus buffer’

• Valid Physical-address (A0 to A19).

• ALE-pulse, to latch the valid Physical-address.
• Proper status code ̅̅̅
S0 to ̅̅̅ ̅̅̅̅̅̅̅̅)
S2 is generated by CPU to initiate data writing (MRTC
from the desired memory bank
• DEN
̅̅̅̅̅̅ = ‘1’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass

• Reset ̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅ signals to END the read-bus-cycle

MRTC and DEN
 Lecture 9 and Lecture 10
Examples

Example 5: Design an interfacing circuit to interface a memory chip type

2K x 8 EPROM to microprocessor 8086 in memory map decoding using
NAND gate. Determine the address range.

Solution:

2KB= 21 X 210
= 211

• The Address Range

First Location:
Last Location:
 Lecture 9 and Lecture 10
Examples

Example 6: Design an interfacing circuit to interface a memory chip

type 8K x 8 EPROM to microprocessor 8086 in memory map
decoding using 3 x 8 decoder, Determine the address range.

Solution:

3 10
8KB= 2 X 2

13
=2

• The Address Range