12

M I P S Reference Data r
ARITHMETIC CORE INSTRUCTION SET OPCODE / FMT /FT

NAME, MNEMONIC FOR MAT OPERATION

e

ht

/ FUNCT (Hex)
e

Branch On FP True bc1t FI if(FPcond)PC=PC+4+BranchAddr (4) 11/8/1/--

g

CORE INSTRUCTION SET OPCODE o

Branch On FP False bc1f FI if(!FPcond)PC=PC+4+BranchAddr(4) 11/8/0/--

NAME, MNEMONIC MAT OPERATION (in Verilog) Hi=R[rs]%R[rt] 0/--/--/1a Divide
FOR / FUNCT (Hex) Unsigned divu R Lo=R[rs]/R[rt];
Divide div R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] (6) 0/--/--/1b
)
d

4
a

Add add R R[rd] = R[rs] + R[rt] (1) 0 / 20hex

Load Word lw I R[rt] = M[R[rs]+SignExtImm] (2) 23hex
n

a
p

Add Immediate addi I R[rt] = R[rs] + SignExtImm (1,2) 8hex e

Nor nor R R[rd] = ~ (R[rs] | R[rt]) 0 / 27hex

3

Add Imm. Unsigned addiu I R[rt] = R[rs] + SignExtImm (2) 9hex Or or R R[rd] = R[rs] | R[rt] 0 / 25hex
s

m
Add Unsigned addu R R[rd] = R[rs] + R[rt] 0 / 21hex n

o
Or Immediate ori I R[rt] = R[rs] | ZeroExtImm (3) dhex
And and R R[rd] = R[rs] & R[rt] 0 / 24hex
i

Set Less Than slt R R[rd] = (R[rs] < R[rt]) ? 1 : 0 0 / 2ahex

o

c
a

And Immediate andi I R[rt] = R[rs] & ZeroExtImm (3) chex r

( o

f
Set Less Than Imm. slti I R[rt] = (R[rs] < SignExtImm)? 1 : 0 (2) ahex
r

Branch On Equal beq I if(R[rs]==R[rt]) Set Less Than Imm.

PC=PC+4+BranchAddr (4) 4hex FP Add Single add.s FR F[fd ]= F[fs] + F[ft] 11/10/--/0 FP Add
FR
d

Double add.d
s

{F[fd],F[fd+1]} = {F[fs],F[fs+1]} +

{F[ft],F[ft+1]} 11/11/--/0
Branch On Not Equal bne I if(R[rs]!=R[rt]) FP Compare Single c.x.s* FR FPcond = (F[fs] op F[ft]) ? 1 : 0 11/10/--/y FP
Compare
m

PC=PC+4+BranchAddr (4) 5hex

o
FR
Double c.x.d* FPcond = ({F[fs],F[fs+1]} op
t

Jump j J PC=JumpAddr (5) 2hex

o

{F[ft],F[ft+1]}) ? 1 : 0 11/11/--/y
* (x is eq, lt, or le) (op is ==, <, or <=) ( y is 32, 3c, or 3e)
b

FP Divide Single div.s FR F[fd] = F[fs] / F[ft] 11/10/--/3 FP Divide

Jump And Link jal J R[31]=PC+8;PC=JumpAddr (5) 3hex FR
d

l
Double div.d {F[fd],F[fd+1]} = {F[fs],F[fs+1]} /

o
Jump Register jr R PC=R[rs] 0 / 08hex {F[ft],F[ft+1]} 11/11/--/3
F FP Multiply Single mul.s FR F[fd] = F[fs] * F[ft] 11/10/--/2 FP Multiply
FR
. Double mul.d {F[fd],F[fd+1]} = {F[fs],F[fs+1]} *
Load Byte Unsigned lbu I R[rt]={24’b0,M[R[rs]
{F[ft],F[ft+1]} 11/11/--/2
+SignExtImm](7:0)} (2) 24hex FP Subtract Single sub.s FR F[fd]=F[fs] - F[ft] 11/10/--/1 FP Subtract
FR
2

Double sub.d {F[fd],F[fd+1]} = {F[fs],F[fs+1]} -

Load Halfword
I {F[ft],F[ft+1]} 11/11/--/1
Unsigned lhu R[rt]={16’b0,M[R[rs] Load FP Single lwc1 I F[rt]=M[R[rs]+SignExtImm] (2) 31/--/--/-- Load FP
I
d

r
+SignExtImm](15:0)} (2) 25hex Double ldc1 F[rt]=M[R[rs]+SignExtImm]; (2)
a

F[rt+1]=M[R[rs]+SignExtImm+4] 35/--/--/--
c

Move From Hi mfhi R R[rd] = Hi 0 /--/--/10 Move From Lo mflo R R[rd] = Lo

0 /--/--/12 Move From Control mfc0 R R[rd] = CR[rs] 10 /0/--/0 Multiply mult
Load Linked ll I R[rt] = M[R[rs]+SignExtImm] (2,7) 30hex
e
R {Hi,Lo} = R[rs] * R[rt] 0/--/--/18 Multiply Unsigned multu R {Hi,Lo} = R[rs]
* R[rt] (6) 0/--/--/19 Shift Right Arith. sra R R[rd] = R[rt] >>> shamt 0/--/--/3
t

a
Load Upper Imm. lui I R[rt] = {imm, 16’b0} fhex Store FP Single swc1 I M[R[rs]+SignExtImm] = F[rt] (2) 39/--/--/-- Store FP
r
 I d
(2) SignExtImm = { 16{immediate[15]}, immediate }
Double sdc1 M[R[rs]+SignExtImm] = F[rt]; (2) r

a
(3) ZeroExtImm = { 16{1b’0}, immediate }
M[R[rs]+SignExtImm+4] = F[rt+1] 3d/--/--/--
(4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0 }
FLOATING-POINT INSTRUCTION FORMATS
C

I
Unsigned sltiu R[rt] = (R[rs] < SignExtImm) (5) JumpAddr = { PC+4[31:28], address, 2’b0 }
a

FR
t

(6) Operands considered unsigned numbers (vs. 2 s comp.) ’

p

? 1 : 0 (2,6) bhex
a

D
(7) Atomic test&set pair; R[rt] = 1 if pair atomic, 0 if not atomic
g

Set Less Than Unsig. sltu R R[rd] = (R[rs] < R[rt]) ? 1 : 0 (6) 0 / 2bhex
o

c
BASIC INSTRUCTION FORMATS
n

opcode rs rt rd shamt funct

FI
l

Shift Left Logical sll R R[rd] = R[rt] << shamt 0 / 00hex

R
l

Shift Right Logical srl R R[rd] = R[rt] >> shamt 0 / 02hex u

e

31 26 25 21 20 16 15 11 10 6 5 0 f

PSEUDOINSTRUCTION SET
opcode fmt ft fs fd funct
NAME MNEMONIC OPERATION
Branch Less Than blt if(R[rs]<R[rt]) PC = Label Branch Greater Than
bgt if(R[rs]>R[rt]) PC = Label Branch Less Than or Equal ble
if(R[rs]<=R[rt]) PC = Label Branch Greater Than or Equal bge
if(R[rs]>=R[rt]) PC = Label Load Immediate li R[rd] = immediate
31 26 25 21 20 16 15 11 10 6 5 0 Move move R[rd] = R[rs]
opcode fmt ft immediate REGISTER NAME, NUMBER, USE, CALL CONVENTION

NAME NUMBER USE PRESERVED ACROSS A CALL?

31 26 25 21 20 16 15 0 $zero 0 The Constant Value 0 N.A.

P

$at 1 Assembler Temporary No

Store Byte sb I M[R[rs]+SignExtImm](7:0) =

.
$v0-$v1 2-3 Values for Function Results

1
R[rt](7:0) (2) 28hex and Expression Evaluation No

$a0-$a3 4-7 Arguments No

)
Store Conditional sc I M[R[rs]+SignExtImm] = R[rt];

R[rt] = (atomic) ? 1 : 0 (2,7) 38hex $t0-$t7 8-15 Temporaries No

”

$s0-$s7 16-23 Saved Temporaries Yes

Store Halfword sh I M[R[rs]+SignExtImm](15:0) =
$t8-$t9 24-25 Temporaries No
a
R[rt](15:0) (2) 29hex

$k0-$k1 26-27 Reserved for OS Kernel No

C

Store Word sw I M[R[rs]+SignExtImm] = R[rt] (2) 2bhex $gp 28 Global Pointer Yes
n

$sp 29 Stack Pointer Yes

e
Subtract sub R R[rd] = R[rs] - R[rt] (1) 0 / 22hex
r

$fp 30 Frame Pointer Yes

G
Subtract Unsigned subu R R[rd] = R[rs] - R[rt] 0 / 23hex
“

$ra 31 Return Address No

(
(1) May cause overflow exception

R S
PI

opcode rs rt immediate opcode address

I J
31 26 25 21 20 16 15 0 31 26 25 0
Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design,
4th ed. M

3
OPCODES, BASE CONVERSION,
ASCII SYMBOLS
IEEE 754 FLOATING-POINT
STANDARD
4
IEEE 754 Symbols
re

(2) MIPS Deci

(1) MIPS Binary
MIPS malASCII
funct
funct
opcode
(5:0)
(5:0)
(31:26)

(1) sll add.f sub.f 00 0000 0 0 NUL00

j srl mul.f jal 0001 1 1 SOH00 0010
sra div.f 2 2 STX00 0011 3 3
ETX

beq sllv sqrt.f bne 00 0100 4 4 EOT00

abs.f blez srlv 0101 5 5 ENQ00 0110
mov.f bgtz srav 6 6 ACK00 0111 7 7
neg.f BEL

addi jr 00 1000 8 8 BS00

addiu jalr 1001 9 9 HT00 1010
slti movz 10 a LF00 1011 11 b
sltiu movn VT

andi syscall 00 1100 12 c FF00

round.w.f ori break 1101 13 d CR00 1110
trunc.w.f xori ceil.w.f 14 e SO00 1111 15 f
lui sync floor.w.f SI

mfhi 01 0000 16 10 DLE01

(2) mthi 0001 17 11 DC101
mflo movz.f 0010 18 12 DC201
mtlo movn.f 0011 19 13 DC3

01 0100 20 14 DC401
0101 21 15 NAK01
0110 22 16 SYN01
0111 23 17 ETB

mult 01 1000 24 18 CAN01

multu 1001 25 19 EM01 1010
div 26 1a SUB01 1011 27
divu 1b ESC

01 1100 28 1c FS01
1101 29 1d GS01 1110
30 1e RS01 1111 31 1f
US
 lb add cvt.s.f lh 10 0000 32 20 Space10 sc c.sf.f swc1 11 1000 56 38 811 1 to MAX - any
addu cvt.d.f lwl sub 0001 33 21 !10 0010 34.f swc2 c.seq.f
c.ngle 1001 57 39 911 1010 1 in
lw subu 22 "10 0011 35 23 # c.ngl.f 58 3a :11 1011 59
3b ;
MAX 0
10 0100 36 24 $10 c.lt.f 11 1100 60 3c <11
lbu and cvt.w.f lhu 1101 61 3d =11 1110
or sdc1 c.nge.f sdc2
0101 37 25 %10 0110
38 26 &10 0111 39 27 c.le.f c.ngt.f 62 3e >11 1111 63 3f
lwr xor MAX
’ ? ≠0
nor

sb 10 1000 40 28 (10
sh 1001 41 29 )10 1010
swl slt 42 2a *10 1011 43 2b
sw sltu + (Exponent - Bias)
(-1)S ⋅ (1 + Fraction) ⋅ 2 S.P. MAX = 255, D.P. MAX = 2047
ht

swr 10 1100 44where

2c Single
,10 Precision Bias = 127, Double g

cache 1101 45 2dPrecision

-10 1110Bias = 1023.
o

46 2e .10 1111 47
2f / IEEE Single Precision and
)

Double Precision Formats: 4

ll tge c.f.f lwc1 11 0000 48 30 011

tgeu c.un.f lwc2 tlt 0001 49 31 111 0010
c.eq.f pref tltu 50 32 211 0011 51 33 d

c.ueq.f 3 n

teq c.olt.f 11 0100 52 34 411

ldc1 c.ult.f ldc2 0101 53 35 511 0110 3

tne c.ole.f c.ule.f 54 36 611 0111 55 37

7

S Exponent Fraction

31 30 23 22 0 m

Exponent Fraction
S lo

63 62 52 51 0 c

MEMORY ALLOCATION $sp 7fff fffchex Stack Memory

e

STACK FRAME
Higher ...
di

dr

$gp 1000 8000hex 1000 pc 0040 0000hex 0hex Reserved Saved Registers Local Lower a

Memory Addresses
c

0000hex DATA ALIGNMENT

$fp $sp
m

Variables o

t
e

t
a

o r

a
b

Addresses
dl
p

Dynamic Data Static Data

o

Argument 6
Text Argument 5 Stack .

Grows 2
(1) opcode(31:26) == 0 EXCEPTION CODES
)

(2) opcode(31:26) == 17ten (11hex); if fmt(25:21)==16ten (10hex) f = s (single); if ”

fmt(25:21)==17ten (11hex) f = d (double) Number Name Cause of Exception Number Name Cause of Exception
Double Word
0 Int Interrupt (hardware) 9 Bp Breakpoint Exception
Word Word
4 AdEL Address Error Exception 10 RI Reserved Instruction
Halfword Halfword Halfword Halfword (load or instruction Exception
fetch)
Byte Byt Byt Byt Byt Byte Byte Byte
e e e e 5 AdES Address Error Exception 11 CpU Coprocessor
(store) Unimpleme
nted

6 IBE Bus Error on 12 Ov Arithmetic Overflow

Instruction Exception
o
Fetch
t

13 Tr Trap
n
7 DBE Bus Error on Load
o or Store
i

01234567 8 Sys Syscall Exception 15 FPE Floating Point Exception

r

Value of three least significant bits of byte address (Big Endian)

o

EXCEPTION CONTROL REGISTERS: CAUSE AND STATUS

e
d

B Interrupt Exception
Mask Code n

D
e

r
l

31 15 8 6 2
a
a

Pending U E I
Interrupt SIZE PREFIXES (10x for Disk, Communication; 2x for Memory)
M L E
t

PRE PRE PRE PRE

SIZE SIZE SIZE SIZE
FIX FIX FIX FIX
l

3 10 15 50 -3 -15
10 , 2 Kilo- 10 , 2 Peta- 10 milli- 10 femto
u

15 8 4 1 0 106, 220 Mega- 1018, 260 Exa- 10-6 micro- 10-18 atto
.

BD = Branch Delay, UM = User Mode, EL = Exception Level, IE =Interrupt Enable 9 30 21 70 -9 -21

10 , 2 Giga- 10 , 2 Zetta- 10 nano- 10 zepto
1

1012, 240 Tera- 1024, 280 Yotta- 10-12 pico- 10-24 yocto

D
e

r
The symbol for each prefix is just its first letter, except μ is used for micro.
e
S

Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed. M