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  • CH - 2 Page2

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    razu
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    The document appears to be an engineering diagram showing the layout of transistors on an integrated circuit. It depicts multiple transistors of varying sizes connected by polysilicon and metal layers, with dimensions labeled in micrometers. Key components include wells, active areas, gates, sources, drains, and contacts connecting the transistors.

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    CH -2 page2

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    The document appears to be an engineering diagram showing the layout of transistors on an integrated circuit. It depicts multiple transistors of varying sizes connected by polysilicon and metal layers, with dimensions labeled in micrometers. Key components include wells, active areas, gates, sources, drains, and contacts connecting the transistors.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    10 views1 page

    CH - 2 Page2

    Uploaded by

    razu
    The document appears to be an engineering diagram showing the layout of transistors on an integrated circuit. It depicts multiple transistors of varying sizes connected by polysilicon and metal layers, with dimensions labeled in micrometers. Key components include wells, active areas, gates, sources, drains, and contacts connecting the transistors.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    1.

    2µ

    well (n)
    0.6µ m1 0.32µ m2 0.4µ

    1.2µ

    0.4µ
    0.32µ
    active (n) 0.4µ

    0.3µ

    0.4µ m4 0.4µ
    polysilicon m3
    0.36µ

    0.24µ
    0.4µ 0.4µ

    0.44µ

    m5 0.46µ
    0.44µ n+

    0.1µ 0.44µ
    select 0.44µ
    p+
    contact via
    0.44µ
    0.3µ 0.35µ

    0.44µ 0.3µ 0.36µ

    p+
    poly
    0.14µ

    0.36µ

    transistor 0.44µ

    0.6µ
    well boundary

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