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Layer Description Representation

metal

m1 m2 m3 m4 m5

well

nw

polysilicon

poly

contacts & vias

ct v12,v23,v34,v45 nwc pwc

active area
and FETs
ndif pdif nfet pfet

select

nplus pplus prb

Colorplate 1. CMOS layers and representations


(for vanilla 0.25 µm CMOS process)

0.3µ (contact to contact)

m1 0.36µ
m2

via contact
0.14µ (poly to contact)
poly

0.09µ (metal to contact)

poly-m1
poly-m1-m2 overlap overlap
0.14µ (ndif to contact)

m1

0.28µ (transistor to contact) 0.35µ


poly
metal-to-poly
n+ contact

Colorplate 4. Design rules regarding contacts and vias.


Overlapping layers are marked by merged colors.

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