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    This document discusses design rules for well contacts and select layers in semiconductor manufacturing. It shows the layout of an inverter transistor circuit fabricated in a 0.25 micrometer CMOS technology, including an n-well, p-type and n-type transistors, contacts to metal layers, and a polysilicon gate. The inverter has an input and output terminal.

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    CH -2 page3

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    This document discusses design rules for well contacts and select layers in semiconductor manufacturing. It shows the layout of an inverter transistor circuit fabricated in a 0.25 micrometer CMOS technology, including an n-well, p-type and n-type transistors, contacts to metal layers, and a polysilicon gate. The inverter has an input and output terminal.

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    © All Rights Reserved
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    9 views1 page

    CH - 2 Page3

    Uploaded by

    razu
    This document discusses design rules for well contacts and select layers in semiconductor manufacturing. It shows the layout of an inverter transistor circuit fabricated in a 0.25 micrometer CMOS technology, including an n-well, p-type and n-type transistors, contacts to metal layers, and a polysilicon gate. The inverter has an input and output terminal.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    p+ n+

    n-well

    0.1µ

    Colorplate 5. Design rules regarding well contacts and


    select layers (needs work!).

    n-well

    PMOS transistor
    contact to metal

    In Out

    polysilicon gate
    NMOS transistor

    Colorplate 6. Layout of inverter in 0.25 µm CMOS technology.

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