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Step-by-step design of an LCL filter for three-phase grid interactive converter

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Step-by-step Design of an LCL Filter for
Three-phase Grid Interactive Converter
Shahil Shah, Member, IEEE PELS
Abstract—This paper proposes a step-by-step procedure for
designing an LCL filter for grid-interactive converter while
addressing the limiting constraints like maximum allowable
ripple component in grid-side current, converter side ripple
current, range of allowable resonant frequency, size of filter
capacitor, harmonics in voltage profile during stand-alone mode
and limit on total inductance in filter. Primary goal of restricting
the harmonic components in current fed to the grid (grid-
tied mode) or output voltage (stand-alone mode) within limits
specified by stringent standards such as IEEE 519-1992, IEEE
P1547-2003 and IEEE 446-1995 is achieved while adhering to
the aforementioned constraints. The filter design is optimized
by considering the worst case harmonics which could occur in
three phase inverter. This design approach yields compact filter
compared to traditional design procedures, which do not account
for the cancelations of carrier band harmonics in three phase
inverters. The trade-off between selection of resonant frequency
and harmonic attenuation has also been explained quantitatively.
The proposed method also takes into account that the harmonic
pollution in capacitor voltage has to be restricted below 5% THD
in the event of islanded operation of converter. The proposed
design algorithm is verified with simulation studies of a 5kVA,
220V 3-φ grid-interactive inverter.
Index Terms—Grid-interactive Converter, LCL filter, harmonic
analysis, per unit
I. I NTRODUCTION
LTERNATIVE forms of energy sources like Fuel Cells
A (FC), Photovoltaics (PV), and Wind Turbine (WT) sys-
tems are gaining popularity because of the environmental prob-
lems associated with the prevalent use of fossil fuels. Voltage
Controlled Voltage Source Inverters (VCVSI) are preferred
as an interface between non-conventional energy sources and
grid because of their ability of bi-directional power flow, DC
link control and harmonic compensation [1]. These converters
from different sources are connected to form a stand-alone
micro-grid which operates either in isolated mode or grid-
tied mode. Front-end converters are operated in either of the
voltage, PQ or current control mode for transfer of power
to the grid. The double mode operation viz. grid-tied mode
and islanded mode, for front-end converters is preferable as it
provides reliable power supply to sensitive loads in the event
of grid outage as shown in Fig.1. In islanded mode, converters
operate in voltage-control mode and require LC or LCL filters
for output voltage filtering to maintain harmonic pollution in
voltage profile below levels specified by IEEE Std. 446-1995
[2]. Whereas, in grid-tied mode, converters operate in current
control mode or PQ control mode, which again basically
controls the real and reactive part of the current supplied to the
S. Shah is with the Decentralized Renewable Energy Technology, Corpo-
rate Research & Technologies, SIEMENS, Bangalore 560100, India (email:
shahil.shah@siemens.com).
1
Vdc
Li Ri Lg Rg DS
grid
a
b
c
Vdc Cf
Rc
Primergy
Sensitive loads
Fig. 1: Grid-interactive Inverter Supplying to Sensitive Loads
grid. Hence, for grid-tied mode, converters require L or LCL
filters for output current filtering and reducing the amount of
harmonics injected to the grid below limits stipulated by the
IEEE Std. 512-1992 and IEEE Std. P1547-2003 [3] [4]. Hence,
a grid-interactive converter which could operate in both modes
requires an LCL filter for interfacing with the grid. Moreover,
an LCL filter provides higher harmonic attenuation compared
to simple L filter with same per unit circuit inductance and
hence they are more suitable for converters operating at low
switching frequencies where inductance size tends to become
very large in case simple L filter is used [5]. The decrease
in the total inductance also results in decrease in voltage
drop across filter and consequently reduction in required DC
link voltage. The smaller DC voltage also means decrease in
ratings of semiconductor switches and further reduction of cost
of whole system. Nonetheless, the design of current control
scheme becomes more complex with LCL filter owing to its
resonance [6].
Usually, in methods presented in literature for the design of
LCL filter [7]- [12], the inverter-side inductance (Li ) is first
chosen to limit the inverter side ripple current to 10-30% of
fundamental current. There is a tradeoff between the size of Li
and maximum allowable ripple current through semiconductor
switches. After selection of Li , the grid-side inductance (Lg )
and filter capacitor (Cf ) are chosen based on the harmonic
attenuation requirements specified by IEEE Std. 519-1992 and
IEEE Std. P1547-2003. The combination of Cf and Lg acts
as a second order low pass current filter and attenuates the
current harmonics coming from inverter side inductor, Li ,
before feeding it to the grid. During selection of Cf and Lg ,
generally it is ensured that the reactive power consumption
by Cf is always less than 5-15% of KVA rating of converter.
Although these methods ensure the attenuation of switching
harmonics below stipulated levels, they do no consider the
effect of resonant frequency on the design of system control
scheme. Also, as the filter is designed using absolute values
and not per unit values, it is not possible to compare filter
sizes for different ratings and applications. Moreover, the
 2

ig (s) 1 + Rc Cf s
=    
vi (s) Li Lg Cf s3 + (Ri + Rc )Lg + (Rg + Rc )Li Cf s2 + (Li + Lg ) + (Ri Rg + Rg Rc + Rc Ri )Cf s + Ri + Rg
ig (s) Li Cf s2 + (Ri + Rc )Cf s + 1
=   (1)
vg (s) (Rg + sLg ) Li Cf s2 + (Ri + Rc )Cf s + 1 + (1 + Rc Cf s)(Ri + sLi )

TABLE I: PU BASE VALUES The inverter output voltage and grid voltage are inputs to
the filter and the currents in the circuit are dependent on these
Parameter Expression Value
inputs and filter parameters. However, the relations between
Power SB - 5.0 kVA grid-side current, ig , and the voltage inputs to the filter are
of paramount importance as the design of current controller,
Voltage (l-l) VB - 220 Volts
attenuation of harmonic currents fed to the grid by inverter and
Frequency fB - 50 Hz sinking of harmonic currents by converter due to distortion
P
in grid voltage depend on them. Eq.(1) gives the transfer
Current IB √ B 13.12 A
3VB function from inverter and grid voltages to grid-side current.
Radian freq. ωB 2πfB 314.16 rad/s The parasitic resistances of inductors are very small and as
VB 2
the entire power flows through them, they are minimized
Impedance ZB 9.68 Ω
PB to decrease losses and can be neglected for analysis. The
Inductance LB ZB
ωB
30.81 mH simplified transfer function from vi to ig is given by (2) and
1
corresponding resonant frequency by (3).
Capacitance CB ωB Z B
328.8 µF
ig (s) 1 + Rc Cf s
=  
vi (s) s Li Lg Cf s2 + (Li + Lg )Rc Cf s + (Li + Lg )
analysis presented is particular to LCL filter and does not allow s (2)
to consider filters with different topologies when the main 1 Lg + Li
objective is common, attenuating current harmonics below fres = (3)
2π Lg Li Cf
permitted level.
In order to generalize the filter design approach and con-
solidate the available information on filter design, this pa- III. D ESIGN C ONSTRAINTS
per presents an unified step-by-step design methodology of Apart from the main objective of limiting the grid-current
filters for grid-interactive converters. Though the method is harmonics within limits, the design of an LCL filter for grid-
demonstrated for an LCL filter, it can be applied invariably to interactive converter is also governed by several technical
other topologies as well. To optimize the design and reduce constraints like the limit on total inductance, allowable range
the size of filter, the paper also considers the cancelation of of resonant frequency, limit on the size of filter capacitor,
carrier band harmonics in three-phase inverters [13]. With allowable ripple current from converter and requirement of
the presented approach, it is possible to design filter hav- passive damping. Following sections describe all this con-
ing resonant frequency within specified zone. Also, as grid- straints and their implications.
interactive converters operate in voltage control mode during
islanded operation to supply power to the sensitive loads, the
design procedure takes into account the maximum permitted A. Grid Current and Output Voltage Harmonic Limits
harmonic pollution in output voltage specified by standards For any distributed source supplying power to the utility
such as IEEE 446-1995. The performance of designed LCL grid through grid-interactive converter, the amount of harmon-
filter is verified by simulation studies on a three-phase 5kVA, ics in current injected to the grid should not exceed limits
220V (line-line), LCL filter based grid-interactive converter imposed by utility standards like IEEE 519-1992 and IEEE
operating at 10kHz switching frequency. P1547-2003. Table II shows the current distortion limits for
generating units feeding power at distribution levels (120V
II. LCL F ILTER M ODEL through 69kV).
Apart from grid-tied mode, in the event of grid failure,
Fig.1 shows the typical schematic of grid-interactive inverter grid-interactive converter shown in Fig.1 operates in islanded
coupled with grid through an LCL filter. For the demonstra- mode and acts as a voltage source to supply uninterrupted
tion of design a 5kVA, 220V line-to-line, 50Hz three phase power to the sensitive loads. Hence, such converters basically
two level grid-connected inverter operating with asymmetrical behave as an UPS system and the harmonic content in their
regular sampled (ARS) sine-triangle PWM is selected. The voltage profile should be restricted below levels specified by
design is presented in a per-unit (P.U.) basis and base values appropriate standards, e.g. IEEE 519-1992 and IEEE 446-
are provided in Table I for reference. 1995.

TABLE II: IEEE 1547-2003 Limits for Current Distortion in percent of Rated Current (IB )
Harmonic Order (h) h < 11
Percent (%) 4.0
∞ ∞
4Vdc X X 1  π 
Vab (t) =
π m=0 ↔ n=1
m>0 ↔ n=−∞
1
X=1
Y=1
0.8
Vh (Normalized)
0.6
0.4
X = 198
Y = 0.316
0.2
0 proportional to harmonic voltage spectrum of converter and
0 100 200 300 400
h (harmonic number)
Fig. 2: Worst-case harmonic output voltage spectrum for
frequency modulation ratio, mf = 200 & 0.8 ≤ M ≤ 1
in ARS sine-triangle PWM based three-phase inverter.
B. Worst-case Harmonics from Converter
The filter has to be designed such that the output voltage
and current harmonics stay within the limits even for the
worst condition. Hence it is important to evaluate the harmonic
spectrum of converter analytically and derive the highest
magnitudes of voltages the converter can possibly generate
for different harmonic orders. The converter voltage harmonic
spectrum depends upon converter topology, DC link voltage
and modulation technique used. A two level converter is used
here with asymmetrical regular sampled sine-triangle PWM
technique. The line voltage between phase ‘a’ and ‘b’ for such
converter is given by (4), where M is the modulation index,
Vdc is the DC-link voltage, ωo and ωc are the fundamental
and carrier frequencies respectively and specific ‘m’ and ‘n’
indices define the particular nth sideband harmonic around
mth carrier band [13]. Note the different lower summation
limit for n when m = 0 as only positive baseband harmonics
are defined.
For optimum utilization of DC link, the modulation in-
dex value is generally restricted between 0.8 and 1.0. The
worst-case harmonic magnitudes are extracted by sweeping
modulation index from 0.8 to 1 using (4) and are plotted
in Fig.2. It should be noted that the cancelation of certain
harmonics in three phase inverter is accounted here and hence
the first carrier band harmonic of order 200 (= fc /fo ),
the most dominant harmonic in phase-leg voltage harmonic
3
11 ≤ h < 17 17 ≤ h < 23 23 ≤ h < 35 35 ≤ h Total Demand Distortion (TDD)
2.0 1.5 0.6 0.3 5.0
 π π  h πi π
Jn q M sin [m + n] sinn cos mωc t + n ωo t − + (4)
q 2 2 3 3 2
where, q = m + n(ωo /ωc )
spectrum, is absent in the harmonic spectrum of converter.
Such consideration substantially reduces the size of filter
compared to reported conservative designs [14]. The most
dominant harmonic frequency is denoted by ωµ , where µ is
198 (= fc /fo − 2).
X = 399 C. Inverter-side Inductor Ripple Current & Total Inductance
Y = 0.317
The inverter-side inductance ripple current has to be limited
below certain level, same as existence of grid-side harmonic
limits. The ripple current flowing through the converter is
500 600
filter admittance. Hence, higher filter impedance is required
to limit current through semiconductor switches of converter.
However, the voltage drop across filter increases with higher
filter impedance and inverter will be required to produce
this fundamental voltage drop also apart from rated voltage.
Hence, for given choice of switch rating, the maximum ripple
current is limited by the current rating of switch and minimum
ripple current is limited by its voltage rating. Moreover, the
selection of core material, size and cooling requirement owing
to copper and core losses are governed by the ripple content in
inverter-side inductor. Typically the ripple current is limited to
15% ∼ 20% of rated current and the total inductance is limited
to 0.15 p.u. to limit the voltage drop across filter [5].
D. Resonant Frequency
1) Upper Limit: If resonant frequency of filter lies near the
harmonics generated by inverter, instead of attenuating those
harmonics filter will amplify them and destabilize the system.
To avoid such scenario, the resonant frequency of filter, given
by (3), should be kept sufficiently away from the harmonic
spectrum of PWM inverter. It is recommended to keep it below
half of switching frequency of converter due to absence of any
PWM generated harmonics in that region [5].
2) Lower Limit: To increase the relative stability of system,
the resonant peak of filter has to be attenuated below certain
level. This can be done either by passive damping, which
involves the insertion of damping resistors in filter or by active
damping where virtual resistors are emulated in filter through
software to avoid losses associated with passive damping [15].
In contrast to what most literature suggests of placing the
resonant frequency outside of control bandwidth if passive
damping has to be used and within the bandwidth if active
damping has to be implemented for resonant peak attenuation
 4

[10] [14], it is not necessary to keep resonant frequency within hence fundamental currents in both the inductors of filter are
the bandwidth for the implementation of active damping. The approximately equal as shown in (5).
active damping is generally implemented by having an inner
current loop based on either inductor current or capacitor P = 3Vg × ILg ,1 ≈ 3Vg × ILi ,1 =⇒ ILg 1 = ILi 1 (5)
current [15] and the maximum resonant frequency it can
In generalized manner, the per phase rms value of most
damp depends upon maximum possible bandwidth of this
dominant harmonic voltage generated by inverter for any
inner current loop, which is limited by hardware bandwidth
modulation technique can be represented by,
of system and not the control bandwidth of outer loops. The
√
hardware bandwidth is limited by two delays in inner loop Vi,µ = x × 0.5Vdc / 2 = 0.353 · x · Vdc . (6)
owing to delay in switching of inverter after the modulation
signal has changed (worst case delay is Tsw /2) and delay In present case, the value of ‘x’ is 0.316 as shown in
because of sampling of current. To avoid multiple instances Fig.2. The rms value of grid-side inductor current at the most
of switching in single carrier cycle, the sampling frequency is dominant harmonic frequency can be obtained by,
generally limited to twice the switching frequency and hence
VLg ,µ VCf ,µ
the worst sampling delay is also limited to Tsw /2. Hence, ILg ,µ = = (7)
the worst-case total delay which might occur in inner loop is ωµ L g ωµ L g
Tsw and its effect can be easily compensated around resonant where VLg ,µ = VCf ,µ − Vg,µ = VCf ,µ , if grid voltage is
frequency by proper design of lead compensators in inner assumed to be pure sinusoidal. From (5)-(7), the grid-side
current loop for active damping [15]. Hence, to simplify the inductor is given by
design of outer control loops, it is recommended to keep the
resonant frequency higher than the control bandwidth, even 3x · a · Vdc · Vg
when active damping is used for resonant peak attenuation. Lg = √ . (8)
2 2 · ωµ · rg · P
E. Filter Capacitor It is shown in Appendix.A, that the attenuation of harmonic
In an LCL filter, for feeding power to the grid at unity power components in capacitor voltage, VCf , during islanded mode
factor, there are four combinations of locations to put voltage is approximately same as that during grid-tied mode, given
and current sensors [8]. The measured voltage and current are by ‘a’. Hence to meet the voltage distortion limits during
kept in phase and if voltage and current sensors are located islanded mode, ‘a’ is kept very low and it can be assumed
such that they measure vg and ig then the power fed to the that Vi,µ ≫ VCf ,µ .
grid will be at unity power factor. Though voltage sensors Hence the rms value of inverter-side inductor current at the
are generally positioned to measure vg to extract grid angle, most dominant frequency is given by,
current sensors are usually positioned to measure inverter-side VLi ,µ Vi,µ
inductor current, ii to avoid extra sensors for over-current ILi ,µ = = (9)
ωµ L i ωµ L i
protection of inverter. This decreases the grid-side power factor
by the reactive power consumed by filter capacitor. Hence to Then, from (5), (6) and (9) the inverter-side inductor is
keep the decrease in power factor within limit, the capacitor determined by
size has to be limited to 0.05 p.u.
3x · Vdc · Vg
Li = √ . (10)
IV. D ESIGN P ROCEDURE 2 2 · ωµ · ri · P
The objective of LCL filter design is to evaluate the val-
Also, by neglecting the parasitic resistances in filter circuit,
ues of inverter-side inductance (Li ), filter capacitance (Cf )
the capacitor voltage at most dominant frequency ωµ is given
and grid-side inductance (Lg ) such that the filter meets all
by
the aforementioned design constraints. The values of these Lg
three filter parameters are basically governed by following VCf ,µ = 2
Vi,µ . (11)
ωµ Lg Cf Li + (Lg + Li )
variables defined as 1. grid-side ripple current component
(rg = ILg ,µ /ILg ,1 ), 2. inverter-side ripple current component From (11), the capacitor size is determined by
(ri = ILi ,µ /ILi ,1 ) and 3. capacitor voltage ripple attenuation √ !
(a = VCf ,µ /Vi,µ ). The grid-side ripple current component, 1 1 − a 2 2 · ωµ · rg · P
Cf = − . (12)
rg , is fixed to 0.3% as shown in Table.II. Hence, the filter ωµ 2 a Li 3x · Vdc · Vg
parameters are function of two variable, viz. ri and a and all
the design constraints can be plotted on surface plots showing
limits on these variable. This exercise yields the permitted B. Sizing of DC Bus
range of these two variable in which filter will satisfy all The required DC link voltage Vdc in grid-interactive inverter
mentioned constraints. depends upon minimum modulation index (M̌) and grid-
voltage Vg . The relation between them is
A. Formulation
As the filter capacitor size is limited to 0.05p.u., the Vdc
Vg = M̌ √ ⇒ Vdc ≈ 450V (f or, M̌ = 0.8). (13)
fundamental component of capacitor current is negligible and 2 2
 5

Range of "a" and "r "

i TABLE III: Designed Filter Parameters
0.16

0.14 Parameter Abs. Value P.U. Value

Capacitor Voltage Attenuation V (µ)/V (1)

Inductor limit (0.1 p.u.)

Cf

0.12 Li 411 µH 0.0133

Cf

0.1
Lg 616 µH 0.0200
Maximum Resonant Frequency (3500 Hz)
0.08
LT 1027 µH 0.0333
0.06
Cf 20 µF 0.0606
0.04 Maximum Capacitance (0.15 p.u.)
fres 2271 Hz 45.42
0.02
Minimum Resonant Frequency (2000 Hz)

0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Inverter−side Current Ripple I (µ)/I (1)
Li Li (LTpu ) to be less than 10%, filter capacitor size (Cfpu ) less
than 15% and resonant frequency (fres ) lying between 2000
Fig. 4: Permissible range of ‘a’ and ‘ri ’. and 3500Hz. It should be noted that for this region, inverter-
side ripple content is less than 30%. A point is selected from
this region with a equal to 0.03 and ri equal to 0.15, giving
C. Per Unit Expressions capacitor voltage attenuation of about 30dB and inverter-side
It is possible to formulate the expressions between filter ripple current content to be 15%. This selection gives filter
parameters and design constraints in terms of per unit values parameters as shown in Table.III.
as not only the design constraints are given in percentage but
they are dependent also on p.u. values of filter parameters and V. S IMULATION R ESULTS
not on their absolute values. The filter designed in per unit A two level three phase inverter operating on ARS sine-
system can be directly compared with filters designed with triangle PWM with an LCL filter with parameter values as
different topology and/or for different rating. designed in earlier section is simulated to verify the perfor-
Using base values of Table.I and eq. (8), (10), (12) and (13), mance of the designed filter. Fig.5 shows the waveforms for
the expressions for filter parameters and resonant frequency in output phase voltage (vi ), inverter-side inductor current (ILi ),
p.u are given by grid-side inductor current (ILg ) and filter capacitor voltage
(x/M̌ ) · ωB (x/M̌ ) · a · ωB (VCf ) along with corresponding harmonic spectrums. The
+ LTpu = Lipu + Lgpu = absence of first carrier band harmonic in Fig.5a must be noted,
ωµ ri ωµ rg
whose consideration has resulted in optimized design. Also,
(14)
  the inverter-side ripple current content is 8.37%, which is
ωB (1 − a) · ri − rg lower than selected ri of 15% because the modulation index
Cfpu = (15)
ωµ · a (x/M̌ ) used in the simulation is 0.8. The ripple content in current
s
ωµ a · ri + rg going to the grid is 0.17% as shown in Fig.5c, which is less
ωrespu = (16) than the stipulated bound of 0.3%. Moreover, during islanded
ωB (1 − a) · ri − rg
s operation also, the capacitor voltage has THD of 1.35%, which
ωµ a · ri + rg is well within the limits specified by IEEE 519-1992 and IEEE
and hence, fres = (17) 446-1995 of 5.0%.
2π (1 − a) · ri − rg
To reemphasize, it should be noted from above equations VI. C ONCLUSIONS
that p.u values of filter parameters are dependent only on a, ri ,
The paper has proposed the unified step-by-step design ap-
rg and (x/M̌ ), where the last variable depends on modulation
proach for an LCL filter design for grid-interactive converter.
scheme used, inverter topoloty and minimum modulation index
Though the design approach is demonstrated for an LCL
allowed in the system.
filter based two level inverter operating with asymmetrical
regular sampled sine-triangle PWM, it is applicable to other
D. Permissible Region for a and ri filter topologies and also to multi-level inverters operating
Fig.3 shows the total inductance, filter capacitance and res- with different modulation schemes. The cancelation of har-
onant frequency as functions of capacitor voltage attenuation monics due to three-phase topology, specifically the carrier
(a) and inverter-side current ripple content (ri ). It also includes band harmonics, are considered in the paper, resulting in the
the limits on them imposed by design constraints discussed in optimized design. The paper also discusses exhaustively the
earlier section. It is possible to get the range of a and ri design constraints one has to consider while designing filter
in which total inductance and filter capacitor size are within for grid-interactive converters. The effect of choice of active or
stipulated limits and resonant frequency is in specified range. passive damping on selection of resonant frequency has also
been discussed and it is shown that the selection of resonant
Fig.4 shows the range of a and ri where any point lying frequency is independent of the choice of damping method.
in the shaded region ensures total per unit inductance of filter Moreover, the presented design approach in p.u. system allows
 6

(a) Total Inductance (LTpu ) (b) Filter Capacitance (Cfpu ) (c) Resonant Frequency (fres )

Fig. 3: Total inductance, capacitance and resonant frequency as functions of ‘a’ and ‘ri ’ with design constraints.

(a) Output phase voltage of inverter (vi ). (b) Inverter-side inductor current (ILi ).

(c) Grid-side inductor current (ILg ). (d) Filter Capacitor Voltage (VCf ).

Fig. 5: Performance of the designed filter with ARS PWM based three-phase two level inverter.

the comparison of filters designed for converters of different A PPENDIX A

ratings and topologies. The complete analysis and performance O UTPUT VOLTAGE ATTENUATION IN I SLANDED M ODE
of the designed filter are validated by simulation studies on The relation between inverter output voltage (vi ) and filter
5kVA, 220V, three-phase LCL filter based grid-interactive capacitor voltage (vCf ) in islanded mode is given by
converter.
vCf (s) 1 + Rc Cf s 1
= ≈ (18)
vi (s) Li Cf s2 + Rc Cf s + 1 Li Cf s2 + 1
It is necessary that the dominant harmonics in output voltage
are sufficiently attenuated, specifically in islanded operation
to meet the maximum THD limit of 5.0% specified by IEEE
519-1992 and IEEE 446-1995. As the LCL filter design for
 7

grid-tied mode depends on a, ri and rg , it is convenient

to formulate this design constraint of THD limit on output
voltage in terms of this variable. From (18), the attenuation
of most dominant harmonic component of order µ in output
voltage during islanded operation, denote by ã, is given by
1 ωB 2 1
ã = ≈ ·
Li Cf ωµ 2 + 1 ωµ 2 Lipu Cfpu
ari
=
(1 − a)ri − rg
Now, (1 − a) ≈ 1 and ri ≫ rg and hence,
ã ≈ a (19)
Eq.(19) shows that the attenuation in output voltage dur-
ing islanded mode is approximately same as filter capacitor
voltage attenuation during grid-tied mode.

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