HALF AND FULL

SUBTRACTOR
EXPERIMENT NO(HW/SW): 4

REGISTER NO: 21BAI1154

NAME: Yamini S

DATE: 5th September, 2022

AIM: To construct combinational logic circuits, half subtractor and full subtractor, using
FPGA and digital IC trainer kit.
TRAINER KIT/EDA TOOL: Digital IC trainer/ModelSim
IC PIN DIAGRAM:

DESIGN (TRUTH TABLE/SCHEMATIC/SIMPLIFICATION):

VERILOG CODE:
HALF SUBTRACTOR:
i) GATE LEVEL MODELING:
ii) DATA FLOW MODELING

iii) BEHAVIORAL MODELING

FULL SUBTRACTOR:
i) GATE LEVEL MODELING:

ii) DATA FLOW MODELING

iii) BEHAVIORAL MODELING

SIMULATION OUTPUT:

HALF SUBTRACTOR:
FULL SUBTRACTOR:

RESULT/INFERENCE:

The combinational circuits designed have proven to perform the simple subtraction
operation, using FPGA and IC trainer kit.