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  • STA Interview Questions

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    nagendra babu
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    This document contains questions related to static timing analysis (STA) concepts and techniques. Some of the key topics covered include: - The difference between StarRC SPEF and ICC2 SPEF files - How to resolve linking issues and PARA-006 errors - The difference between false paths and disabled timing paths - How to define and check timing constraints and clock definitions - What timing loops are and how to resolve them - How to address unclocked sequential cells - The purpose of set_max_delay constraints - How to check the quality of timing reports, parasitic files, and constraints - What arrival time and required time refer to - The meaning of setup and hold time windows

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    STA interview questions

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    This document contains questions related to static timing analysis (STA) concepts and techniques. Some of the key topics covered include: - The difference between StarRC SPEF and ICC2 SPEF files - How to resolve linking issues and PARA-006 errors - The difference between false paths and disabled timing paths - How to define and check timing constraints and clock definitions - What timing loops are and how to resolve them - How to address unclocked sequential cells - The purpose of set_max_delay constraints - How to check the quality of timing reports, parasitic files, and constraints - What arrival time and required time refer to - The meaning of setup and hold time windows

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    175 views2 pages

    STA Interview Questions

    Uploaded by

    nagendra babu
    This document contains questions related to static timing analysis (STA) concepts and techniques. Some of the key topics covered include: - The difference between StarRC SPEF and ICC2 SPEF files - How to resolve linking issues and PARA-006 errors - The difference between false paths and disabled timing paths - How to define and check timing constraints and clock definitions - What timing loops are and how to resolve them - How to address unclocked sequential cells - The purpose of set_max_delay constraints - How to check the quality of timing reports, parasitic files, and constraints - What arrival time and required time refer to - The meaning of setup and hold time windows

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    What is the STA analysis?

    What kind of inputs needed to start Prime Time?


    What is the difference between StarRC SPEF and ICC2 SPEF?
    How do you resolve linking issues?
    What is PARA-006 Issues?
    What is target Library?
    What is link library?
    What is the difference between False Paths Vs Disable timing paths?
    How generated clocks will define?
    How to check constraints quality?
    What are the timing loops?
    What will happen with timing loops?
    How to resolve un-clocked sequential ?
    What is the purpose of set_max_delay constraints?
    What is MPW? How to fix MPW?
    As STA engineer, which will prefer fix before starting the ECO’s of the partition?
    What kind of checks will do before timing fixes?
    What is the linking issues code in Log files?
    How do u check quality of parasitic files?
    What is RC-011 warning in log files?
    Can we create clock definitions on combo cells?
    Can u draw circuit for generated clocks?
    Is cross talk going to impact setup or hold?
    What is CRPR?
    How CRPR is going to impact your design ?
    What is arrival time?
    What is required time?
    how do you fix clock gate violations?
    what is the meaning of set_driving_cell?
    What kind of latency is good for design, Higher latency or lower latency?
    What do you mean by global skew or local skew ?
    What is the setup & Hold time?
    How can we avoid setup & Hold timing issues?
    What the purpose of timing constraints?
    What is the corners / modes?
    What is the difference between SS and FF timing analysis
    How do you read timing models for Hierarchical model designs?
    What is the difference between PnR spef Vs QRC spec?
    What kind of variations will be see between two corners?
    What is the effect of temperature inversion effect?
    Is any constraints will be defined in .lib files?
    What is the difference wire load models Vs SPEF files?
    What is the difference between Pre and Post Layout STA? Is the inputs files are going to
    change between the two models?
    What is the duty cycle distortion? how to improve?
    How to fix the cross talk?
    How will latency impact Setup / Hold timing?
    What is anchor buffer?
    What is the difference between CCS and NLDM models?
    Which model is more accurate between CCS and NLDM models ?
    What kind of information contains in. libs ?

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