 What are Sanity checks will you perform on synthesis and net list

 Pre Pnr checks

 What are the inputs for pnr
 What is the core utilization you have given before floor plan
 How is the utilization on later stage if (yes/no) why?
 Floor plan guide lines
 What are the checks will you do after placing floor plan
 What is congestion
 Reduction techniques of congestion
 If you are seeing congestion at the notch of the core how will reduce the congestion
 What are the reports you check after placement
 Set up slack fixes
 CTS inputs
 If we are unable to meet the latency targets what will u do
 Set up slack fixes and hold slacks fixes?
 What is cross talk how will reduce the cross talk
 Difference between cross talk and noise
 Innovus commands
 Scripting,which language you are using
 Inputs for cts
 What is lef and def
 What is physical design process
 What is cross talk reduction techniques
 Different type of cells used in cts
 Challenges done in your project
 Tools used in your project
 Why we will not you low and high strength cells clock path?
 What are cts exceptions?
 Given some scenarios like same path violating for setup and how you fix them?
 We are seeing setup violation you must not touch data path, how you fix them?
 About yourself