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Physical Design Questions
Physical Design Questions
A. It is not possible to fix both at a time because if we increase the delay in data
path it's good for hold and bad for setup.But there is only one way to fix it.
A. a) Increase the spacing between the aggressor and victim nets.
b) Shielding.
A. It is the undesirable electric interaction between two or more physical adjust
nets due to the capacitance cross coupling.When two nets are in parallel the electric
field of one net is effects the other net which is nearer to it.This called cross-talk
effect.
A. It is the process of re connecting the scan chains in the design to optimize for
routing by reordering the scan chain connection which improves timing and
congestion.
A. The std-cells in the design are placed in rows.All rows have equal height and
spacing.The width of the row can vary.The std-cell in the row get the power and
ground connection from vdd and vss rails.Sometimes technology allows the rows to
be flip.So they can share the power and ground rails in vdd-vss-vdd patron.
A. We can insert buffer near to launch flop which decreases the transition
time.Hence decreasing the wire delay therefore overall delay will decrease.When
arrival time will decrease setup violations will reduce(required time-arrival time).
Q 10.What is partitioning?
A. It is the process of dividing the chip into small blocks this is done mainly to
separate different functional blocks and also make placement.routing easier.
A. To reduce the yield loss due to via failures,double via's are inserted traditionally
double via's where inserted in post route and then modify the routing to fix any
DRC's.
A. At the time of etching they use some type of chemicals due to that chemical
metal loss will be more for that reaction we are inserting the metal fills.
Q 14.What is metal slotting?
A. It is the Technic for avoiding the problems like metal lift off and metal erosion.
A. It is defined as the difference between the height of the oxide in the spaces and
that of the metal in the trenches.It is caused by CMP.It may reduced by some
dummy fill Technics effectively.
A. It is the process of smoothing surface with the combination of chemical and
mechanical forces.It is used in IC fabrication to get a high level of polarization.
A. a) Shorts.
b) Opens.
A.It is the delay between the clock source and clock pin.It is two types.Clock source
latency and clock network latency.The time taken from clock source to
definition pin is the clock source latency and from the clock definition pin to clock
pin of the flip flop 2 is the clock network latency.
Hold:-
A.
.v
.lib and .lef
.sdc
tlu+ file
Physical partitioning information of design.
Floor plan parameters like height,width,aspect
ratio,utilization.
Pin/pad position.
A.
Die/block area.
I/O pad placed.
Macro placed.
Power grid design.
Power pre routing.
Std-cell placement area.
A. It is the region around the boundary of fixed macros in design in which no other
macros or standard cells not allows.It allows only buffers and inverters in it's area.
c) Multiple clocks with domine crossing synthesis each clock separately and
balance the skew.
Q 27.What is IR drop?
A. Each metal layer has a resistance value.When the current flows through the
metal the resistance consumes some current.This is the IR drop.If the resistance is
more the drop also more.
A.If we have positive slack use HVT cells in the path and use LVT cells in the path
when we have negative slack.HVT cells have large delay and less leakage power.
LVT cells have less delay and more leakage power.To meet the timing use LVT
cells and to reduce the leakage power use HVT cells.
Q 29.What is wire load model (WLM)?
A. It is an estimation of delay based on area and fan-out.The delay depend on..
Resistance.
Capacitance.
A. It is the ability of an electric signal to carry information reliably and to resist the
effects (cross-talk, EM) of high frequency electromagnetic interface from near by
signals.
A.Yes it is because cross-talk adds or subtracts energy to the signal which cause
setup or hold violations.
A. Positive edge triggered flip flop will favour to setup (setup violations will
reduce).Negative edge triggered flip flop will favour to hold (hold violations will
reduce).
A. i/p's:-
Data base with valid floor plan.
Power rings and power straps width.
Spacing between vdd and vss straps.
o/p:-
A. I/P's:-
Netlist.
Mapped and floor planed design.
Logical and physical lib.
Design constraints.
O/P 's:-
A. To improve the timing for the design or to improve the congestion for a complex
floor plan we can use magnetic placement to specify fixed objects as magnets and
icc moves their connected standard cells close to them.For the best results perform
the magnetic placement before standard cells are placed.
A.The table is drawn by using input transition and output load values.It is used to
calculate the cell delay.
Clock gating.
Multi voltage design.
Power gating.
Multiple vt libraries.
c) Nets.
d) Noise.
A.a) Overlapping of macros.
A. At floor plan stage it acts like guidelines for placement of standard cells.In CTS
stage in order to balance the skew more no.of buffers and inverters are added and
blockages are used to reserve space for buffer and inverter.
A. The horizontal and vertical power straps in the design are called mesh.
A. The i/o cells are the one which interact in between the blocks outside of the chip
to internal blocks of the chip.In floor plan stage i/o cells are placed in between core
and die.These are responsible for providing voltage to the cell in the core.
A.These are the cells which are made of group of std-cells based on functionality
requirement.This cells height is grater than the std-cells and lesser than the macros.
Q 49.What is etching?