2260 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO.
10, OCTOBER 2019
A 24-GHz DCO With High-Amplitude Stabilization
and Enhanced Startup Time for Automotive Radar
Iman Taha , Student Member, IEEE, and Mitra Mirhassani , Senior Member, IEEE
Abstract— In this paper, the optimized design strategies for the
implementation of a CMOS digitally controlled oscillator (DCO)
are investigated. Moreover, the boosting mechanism for a DCO
with and without negative resistance is considered. The pro-
posed design methodology is based on an in-depth mathematical
analysis of the startup condition and amplitude of oscillation.
This approach results in an optimized topology for a Colpitts
Clapp-DCO (CC-DCO). The improved performance is achieved
through the negative resistance boosting mechanism. The nega-
tive resistance enhances the startup time and increases ampli-
tude stabilization across a wide tuning range (TR). Moreover,
it improves the phase noise (PN) performance while suppresses
the amplitude-to-phase conversion. The proposed 24-GHz CMOS
enhanced CC-DCO (ECC-DCO) is implemented in 65-nm TSMC
CMOS process. It can effectively reduce the startup time by 41%.
Also, it boosts and stabilizes the amplitude across a TR of 29%.
The amplitude varies by 1.5% across the 22–29-GHz TR. The
ECC-DCO consumes 12.8 mW. It shows a PN of −106 dBc/Hz
at 1-MHz offset frequency and achieves −185-dBc/Hz figure of
merit (FoM) and −194-dBc/Hz FoM for tuning.
Index Terms— Digitally controlled oscillator (DCO),
millimeter-wave frequency, stable amplitude of oscillation,
wide tuning range.
I. I NTRODUCTION
A UTOMOTIVE short range radar (SRR) contributes to
road safety via precrash sensing, blind-spot detection,
and collision avoidance [1]. Based on the Federal Communi-
cation’s Commission (FCC) regulations, an automotive SRR is
allowed to operate in the frequency range of 22–29 GHz [2].
Range resolution (R) is a key requirement of the
frequency-modulated continuous wave (FMCW) for SRRs,
and it depends on the transmitter bandwidth and tuning
range (TR) of the local oscillator. The bandwidth (B) and R
are related by R = c/B, where c is the speed of light.
Ultrawideband SRR (5 GHz) requires the hard range
resolution. For such a wide frequency range, the amplitude-
to-phase conversion needs to be avoided [3]. The amplitude
of oscillation and, consequently, the transmitted output power
for the SRR is restricted by the effective isotropic radiated
power (EIRP) of −41.3-dBm/MHz.
Manuscript received January 15, 2019; revised April 23, 2019 and May 21,
2019; accepted June 8, 2019. Date of publication July 11, 2019; date of
current version September 25, 2019. This work was supported in part by the
Canadian Micro-Systems Corporation and in part by the National Science and
Engineering Research Council of Canada (NSERC). (Corresponding author:
Mitra Mirhassani.)
The authors are with the Department of Electrical and Computer Engi-
neering, University of Windsor, Windsor, ON N9B 3P4, Canada (e-mail:
taha@uwindsor.ca; mitramir@uwindsor.ca).
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2019.2924018
1063-8210 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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The quality factor (Q) of the switched tuning capacitors
is sharply degraded in higher frequencies, and therefore,
the overall Q tank is reduced. In order to compensate for
the losses, large transistors are required to provide sufficient
transconductance. However, the parasitic capacitors of the
large transistors impose loading effect and, hence, affect the
TR of the voltage-controlled oscillator (VCO) [4]. Therefore,
achieving low phase noise (PN) and wide TR simultaneously
is challenging.
Unlike ring and relaxation oscillators used at low frequen-
cies for few gigahertzs [5], [6], the high-frequency oscillators
are employed based on highly selective resonator to prevent the
noise from outside the bandwidth from degrading the PN [9].
A 24-GHz Colpitts VCO with 30% TR was reported
in [7]. The work in [8] showed the design of a 30-GHz
common-drain Colpitts oscillator. Negative resistance was
improved by employing a parasitic cancellation technique.
Although the startup condition was satisfied over a TR of
15.9%, it was based on 0.2 GaAs pHEMt technology that
required access to specialized and more costly fabrication
process.
However, the steady-state oscillation condition for the
Colpitts VCO varies across the TR. This condition is kept
constant across the TR by employing a Clapp VCO at the
expense of limited TR [9]. In order to increase the TR,
the Colpitts–Clapp topology was proposed in [10].
VCOs and digitally controlled oscillators (DCOs) for SRR
mandate low PN and wide TR [10]. The startup condition
and the amplitude of oscillation in Colpitts Clapp VCOs
are the functions of the tuning element that can impose
difficulties for a design with wide TR requirements [11].
Moreover, the increased reliability factor of the transistor
reduced sizes is 2 to 3 times the minimum initially esti-
mated size [9]. The process and temperature variations neces-
sitate extra frequency tuning margins. Furthermore, increas-
ing the device size increases the parasitic capacitors by
the same factor, limiting the minimum size of the tuning
capacitor, and consequently, the maximum possible achieved
frequency [8].
The work in [12] employs a special resonator-based topol-
ogy to realize an mm-wave VCO, which relaxes the startup
requirement and stabilizes the amplitude. However, the startup
condition enhancement and amplitude stabilization tradeoff
with the TR. The reported TR was limited to 1.7%.
In [13], a Colpitts oscillator was designed to work as a
frequency reference. A high sheet poly resistor with negative
temperature coefficient was used in a constant gm biasing
TAHA AND MIRHASSANI: 24-GHz DCO WITH HIGH-AMPLITUDE STABILIZATION AND ENHANCED STARTUP TIME 2261

Fig. 2. Simulated startup waveforms for the ECC-DCO.

Fig. 1. Differential ECC-DCO schematic.

increase the TR. This has been achieved by employing double

circuitry. The amplitude was stabilized against temperature
tuning capacitors that are comprised of C3 and part of C2 .
variations. However, the TR of this work was limited to
The remaining part of C2 provides the intermediate and the
0.625%.
fine-tuning. The differential Colpitts-based topology can be
The swing and the startup were enhanced in [14] for
analyzed using half-circuit representation [14].
Colpitts VCO by replacing the tail current source with an
When the circuit is biased, the broadband noise that appears
inductor. However, amplitude stability throughout the TR was
at the input initiates the oscillation. Since noise that appears
not discussed, and the TR for the VCO was limited to 2.5%.
at the onset of oscillation is very small, the small-signal
In [15], a Colpitts Clapp-DCO (CC-DCO) was proposed for
model can be developed to describe the startup of oscilla-
SRR, which did not require any special fabrication process and
tion. However, when noise is amplified by the oscillation
was implemented using the conventional CMOS technology.
process, the small-signal approximation is not valid anymore.
In this paper, a more thorough detailed analysis of this mod-
The amplitude of oscillation (Vosc ) increases by the selective
ified topology is derived. The CC-DCO suitable for automotive
positive feedback. Once the oscillation is steady, a large-signal
SRR is designed using the TSMC 65-nm CMOS process.
model is a better choice to describe the behavior.
A negatively boosted structure is employed, which increases
the amplitude without the need to increase the tail current,
and stabilizes the amplitude across the wide TR. Moreover, A. ECC-DCO Startup Negative Resistance Model
it relaxes the restriction on the value of the transconductance
Referring to Fig. 1, the behavior of M3,4 at the startup
that is required to startup the CC-DCO. To the best of
differs from that at the steady oscillation state. Vosc at the
our knowledge, a DCO with boosted amplitude and relaxed
onset of oscillation is practically zero and Vtail biasing =
startup transconductance has not been employed in CMOS
Vgs3,4 = Vds4,3 .
for automotive radar prior to this paper. The proposed design
Fig. 2 shows the gate and drain signals of M3,4 throughout
methodology takes into consideration these effects at an early
the startup till the oscillation grows up to be steady. With
stage of the design, in order to reduce the startup time
just the biasing is being applied to the circuit, Vg3 ≈ Vd3
and to stabilize the amplitude across the TR. The proposed
and Vg4 ≈ Vd4 at the startup. Thus, M3,4 behave like
methodology is geared toward the design of a CC-DCO for
diode-connected devices and can be modeled as resistors
the use in automotive radars.
with a value of 1/gm3,4 , where gm3,4 is the small-signal
The rest of this paper is organized as follows. Section II
transconductance of M3,4 .
presents the small-signal and the large-signal derivations of
Fig. 3(a) shows the half-circuit representation of the
the negative resistance-based models that are used to describe
ECC-DCO. The input impedance (Z in ), looking into the gate
the behavior of the oscillator at the onset and the steady state of
of M1 at the onset of oscillation is derived using the model
oscillation. The TR is discussed in Section III. The amplitude
in Fig. 3(b). The integrated capacitors C1,2 are implemented
stability analysis is provided in Section IV. Section V presents
in 65-nm CMOS technology with the high-quality factor.
the design aspects and the design methodology. The design
Thus, the lossy serial resistances associated with C1,2 are
parameters and prelayout simulation results are shown in
ignored [16]. Moreover, the intrinsic output resistance and
Section VI. The postlayout simulation results are shown in
the second-order effect are neglected for getting an intuitive
Section VII followed by the conclusion in Section VIII.
analysis.
Applying KVL and KCL, Vx in Fig. 3(b) can be written as
II. C OLPITTS –C LAPP AND CMOS E NHANCED M ODELS ⎡ ⎤
The structure of the proposed enhanced CC-DCO (ECC- Vx − SCIx
DCO) is shown in Fig. 1. It is a differential common-drain Ix 1 ⎢ ⎢ gm1 Ix  ⎥
1 ⎥
Vx =  +  ⎣ Ix +  − ⎦ (1)
Colpitts oscillator with a negative resistance boosting mech- SC1 SC2,E SC1 1
anism and extra capacitors in parallel with the inductors to gm3

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2262 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 10, OCTOBER 2019

Instability is enforced at the startup when | Rneg1 |>

R L [17], such that
gm1 + gm3
2 C C
≥ RL . (8)
ωosc 1 2,E
At the frequency of oscillation, L resonates with Ceqv and
ωosc = 2π fosc is given by
1 1
ωosc = 
=  . (9)
C 1 C 2,E
 LCeqv

L C3 + C  +C 
1 2,E

The resistance RL,P is the equivalent parallel resistance of

the R L , such that RL,P = R L (1 + Q 2L ) ∼
= R L Q 2L , where Q L
is the quality factor of L.
Since Q L = (ωosc L/R L ) and Q L  1, R L ,P can be
expressed as
R L ,P ∼
= R L Q 2L = ωosc L Q L . (10)
By substituting the R L by ωosc L/Q L , multiplying both sides
Fig. 3. Reduced circuits used to derive the ECC-DCO negative resistance by R L ,P , replacing R L ,P at the right side of the inequality
small-signal model for analyzing the startup condition. (a) Half-circuit rep- by (10), replacing ωosc by (9), and substituting Ceqv by (7),
resentation of the differential ECC-DCO. (b) Small-signal impedance model
looking into the gate of M1 . (c) Derived small-signal impedance in parallel
a modified startup condition is obtained as follows:
with L and C3 . (d) Negative resistance-based model for the ECC-DCO at the C1 C2,E

startup. gm,E R L ,P ≥  2 (11)
C C
C3 + C  1+C2,E

Vx ∼ 1 1 gm1 + gm3 1 2,E
Z in = = + − 2   . (2) where gm,E = gm1 + gm3 is the effective initial transconduc-
Ix j ωC1 
j ωC2,E ω C1 C2,E
tance for the ECC-DCO.
The negative resistance is denoted by Equation (11) relates the required gm,E to the tuning and
gm1 + gm3 the parasitic capacitors.
Rneg1 = − 2   (3)
ω C1 C2,E The largest value of C2,E cannot exceed C1 as con-
strained by PN requirements [9]. On the other hand, C3 ≈
where gm1 is the small-signal transconductance of M1 and
C2 following the simultaneous tuning mechanism design
C1 = C1 + Cgs1 (4) constraints [15]. Therefore, if C1 = C2 = C3 , the startup
 condition requirement can be expressed as a multiplication of
C2,E = C2 + Csb1 + Cdb3 + Cdb5 + Cgs4 (5)
the effective initial transconductance and the R L ,P , as follows
where Cgs , Csb , and Cgd are the parasitic capacitors associated
4
with the transistors. Equation (2) shows that Z in is equivalent gm,E R L ,P ≥
. (12)
to series combination of C1 , C2,E , and R
neg1 . This input
9
impedance, Z in , in parallel with the lossy inductor and C3 Equation (12) can be used to design M1 and M3 in order to
is shown in Fig. 3(c), where satisfy the startup requirements, taking into consideration the
losses of the tank and the effect of the associated parasitic
C3 = C3 + Cgd1 . (6) capacitors.
The lossy inductor is modeled as an inductor (L) in series with
a parasitic series resistance (R L ). If C1 in series with C2,E
 is B. CC-DCO Startup Negative Resistance Model
 
equal to Cs , then Cs in series with Rneg1 can be converted to
The startup negative resistance model is similar to Fig. 3(d).
a parallel combination of C p and Rneg, p . However, Ceqv,C replaces Ceqv and gm3 = 0. The capacitor
For high Q Cs , C p = Cs Q 2C  /(1 + Q 2C  ) ∼ = Cs , and 
Ceqv,C can be defined using (7) by replacing C2,E  ,
with C2,C
s s
Rneg, p = Rneg1 (1 + Q 2C  ). Let Ceqv = C3 ||C p . The parallel where
s
combination of Ceqv and Rneg, p can be converted back to 
an equivalent series representation. The series resistor and C2,C = C2 + Csb1 + Cdb5 . (13)
capacitor are Rneg,s = Rneg, p /(1 + Q 2Ceqv ) ∼ = Rneg1 and The negative resistance is
Ceqv,s = ((1 + Q 2Ceqv )/Q 2Ceqv )Ceqv ∼
= Ceqv . gm1
Rneg2 = − . (14)
Fig. 3(d) shows the negative resistance-based model for the ωosc C1 C2,C
2 
ECC-DCO at the startup, where Ceqv,E is given by
Instability is enforced at the startup when | Rneg,2 |> R L .
C1 C2,E

Comparing (3) with (14) shows that if, as an example, gm1 =
Ceqv = C3 + . (7)
C1 + C2,E
 gm3 and C2,E  , then the absolute value of the startup
= C2,C

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TAHA AND MIRHASSANI: 24-GHz DCO WITH HIGH-AMPLITUDE STABILIZATION AND ENHANCED STARTUP TIME 2263

negative resistance is doubled in the ECC-DCO and startup

time of the ECC-DCO is lower than that of the CC-DCO.
An alternative startup requirements, similar to (11) and (12)
can be obtained by substituting gm3 = 0, which results in
C1 C2,C

gm1 R L ,P ≥
2 (15)
 C 1 C 2,C

C3 + C  +C 
1 2,C

4
gm,C R L ,P ≥ (16)
9
where gm,C = gm1 is the initial transconductance required for
the CC-DCO.
If L and M1 for the CC-DCO and the ECC-DCO are
identical, then comparing (12) with (16) shows that gm,E
is stronger. The comparison also shows that the CC-DCO
demands higher gm1 than the ECC-DCO that requires
larger M1 . Increasing the size of M1 increases C gd1 that causes
larger C3 . Even C2,E
 has additional parasitic capacitors as

compared to C2,C , the larger parasitic capacitors associated Fig. 4. Steps to derive large-signal models for the CC-DCO and the ECC-
with C1 and C3 for the CC-DCO due to larger M1 can make DCO. (a) Circuit to derive the large-signal CC-DCO model. (b) CC-DCO
large-signal model. (c) Circuit to derive the large-signal ECC-DCO model.
Ceqv and Ceqv,C comparable. (d) ECC-DCO large-signal model.

C. CC-DCO Large-Signal Model The amplitude of oscillation for the CC-DCO in (20) varies
across the TR by the variation of C2 .
Nonlinearity due to large-signal forces Vosc from increasing
while the oscillation continues steadily. By assuming that the
average current of the Colpitts switching transistor is equal to D. ECC-DCO Large-Signal Model
the biasing current, the function model in [18] approximates Referring to Fig. 1, when the swing at the gate of M1 is
I1,2 ≈ 2Ibias , where I1,2 is the peak of Id1,2 that appears as a maximum, the swing at the gate of M2 is minimum, M3 is
train of pulses. turned off, and M4 is turned on. As Vg1 starts to drop-down
The describing function for the large-signal transconduc- from its maximum value and Vg2 shoot-up from its minimum
tance (G m ) can be defined as the ratio of the peak pulse current level, M4 conducts current. M3 conducts peak current in an
to the amplitude of Vgs for the switching transistor and is equal opposite way. Such that the peak of Id3 occurs while Vg2 is
to shooting up and Vg1 is falling down.
I1,peak 2Ibias 2Ibias The average current in M1,2 is equal to the summation of
G m1 ≈ ≈ ≈ (17) Ibias and the average current in M3,4 . Since the switching
VC1 VC1 nVosc
where Ibias is the biasing current for M1,2 . transistors (M1,2 ) and the cross-coupled transistors (M3,4 )
With n = C2 /(C1 + C2 ), VC1 is related to Vosc by the conduct in the opposite directions, then the peak of the
relation train of current pulses flowing in the switching transistors
can still be approximated to be 2Ibias and the large-signal
VC1 = nVosc . (18) transconductance can still be approximated by (17).
Large-signal model for the amplitude approximation is con- The opposite polarities of large signals at the gates of
structed by using the T model to represent M1 and replacing cross-coupled devices generate a negative resistance to be
gm by G m . The large-signal model of the CC-DCO is shown seen between the device gates. We may define G m3,4 to be
in Fig. 4(a). The resistor 1/G m1 and the tapped capacitors C1 the large-signal transconductance for M3,4 . Thus, the cross-

and C2,E can be converted to a resistor of 1/G m1 n 2 in parallel coupled connected devices M3,4 generate a negative resistance
with a series combination of C1 and C2,E [11]. Fig. 4(b) shows of −2/G m3,4 seen between the gates of M3 and M4 . It is
the final model after this transformation. Since C3 appears equivalent to a negative resistance of −1/G m3,4 looking into
in parallel with the series combination of C1 and C2,E  , then the gate of M3,4 .
the total capacitor is Ceqv . The total resistance (Rtotal ) is Fig. 4(c) shows the basic circuitry used to derive the
(1/G m1 n 2 )R L ,P . large-signal model to describe the amplitude. The transistor
At f osc , Vosc for the CC-DCO is given by M1 is replaced by an equivalent T model and G m1 replaces
R L ,P gm1 . The resistors 1/G m1 and −1/G m3 appear in parallel with
Vosc = 2Ibias Rtotal = 2Ibias . (19) C1 and C2 , respectively. By substituting 1/G m1 = R1 and
1 + G m1 n 2 R L ,P −1/G m3 = R2 , the equivalent impedance (Z eqv ) for the series
By substituting (17) in (19) and arranging the terms, the output combination of C1 R1 and C2,E  R can be expressed as
2
amplitude for the CC-DCO is given by   
C1 C1 + C2 R1 R2 + 1s (R1 + R2 )
Vosc = 2Ibias RL,P (1 − n) = 2Ibias RL,P . (20) Z eqv = . (21)
C1 + C2 sC1 C2 R1 R2 + C1 R1 + C2 R2 + 1s

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2264 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 10, OCTOBER 2019

At high frequency, 1/s ∼= 0, and therefore, Z eqv is modified

as follows:
∼ 1
Z eqv = (22)
sCs +  C  +
1
 1 C 
R2 / 1 R1 / 2
C1 +C2 C1 +C2

where Cs is the series combination of C1 and C2 .

The equivalent impedance (Z v ) for a parallel combination
of two typical resistors, R4 and R5 , and a capacitor Cs can be
expressed as
1
Zv = . (23)
sCs + 1/R4 + 1/R5
By comparing (22) with (23), the series combination of R1 C1

and R2 C2,E can be transformed to R4 R5 Cs , where
R2 −1
R4 =   = (24) Fig. 5. Simulated drain current of M3 (Id3 ) and the oscillating output voltages
C1 / C1

+ C2,E G m3 (1 − n) at the gates of M1 (Vg1 ) and M2 (Vg2 ).
R1 1
R5 =    
= . (25) Moreover, increasing C2, f is constrained by the PN require-
C2,E / C1 + C2,E G m1 n
ments; a low PN requires maximizing C1 and the ratio of
Fig. 4(d) shows the final large-signal model after the trans- (C1 /C2 ) [9].
formation. The total output resistance Rtotal is the parallel
combination of 1/nG m1 , −1/G m3 (1 − n), and R L ,P . At f osc , IV. A MPLITUDE S TABILITY A NALYSIS
Vosc = 2Ibias Rtotal , and can be expressed as The oscillation frequency is sensitive to the output ampli-
1 tude and reduced oscillation amplitude degrades the PN
Vosc = 2Ibias . (26) and better PN performance can be achieved by suppressing
1
R L,P + nG m1 − (1 − n)G m3
amplitude-to-phase conversion [12]. Referring to (26), if the
If, as an example, C1 = C2 and G m1 = G m3 , then for following condition holds:
a given Ibias and R L ,P , the ECC-dc amplitude in (26) is
C2 G m1 = C1 G m3 (29)
twice of that of the CC-DCO in (20). Moreover, (26) shows
that increasing G m3 increases Vosc . Since, PN is inversely then the amplitude of oscillation for the ECC-DCO can be
proportional to the square of Vosc , thus larger amplitude is expressed as
mandatory to satisfy low PN requirements [19].
Vosc = 2Ibias R L ,P . (30)
The derived equations (8), (9), (11), (12), (14), (16), (20),
and (26) contribute to the design methodology and explain the This means that the amplitude of oscillations could be inde-
small-signal and large-signal behaviors. pendent of tuning capacitors, yet it depends on Q L as related
in (10).
III. T UNING R ANGE Since G m3 is the large-signal transconductance, a special
function could be derived to describe it due to the non-linearity
The TR is equal to ( f max − fmin )/ f center . Referring to (9),
associated with large-signal behavior.
f max and f min correspond to Ceqv,min and Ceqv,max , respec-
Fig. 5 shows the transient response of Id3 along with
tively. The simultaneous tuning mechanism in [15] equates the
the oscillating voltages at Vg1 and Vg2 , which appear as
parts of C2 with C3 for the coarse tuning while maximizing
(1 − n)Vg2 and (1 − n)Vg1 at the gate and the drain of
the ratio of C1 /C2 such that
M3 , respectively. The transistors, M3,4 , are designed using
C2 = C2, f + C2,intermediate + C2,fine + Ct,coarse (27) low threshold devices. The transistor M3 conducts and carries
C3 = C3, f + Ct,coarse (28) positive drain current when Vg2 is decreasing in the upper half
and Vg1 is increasing in the lower half of the corresponding
where Ct,coarse , C2,intermediate, and C2,fine are the coarse, inter- sinusoidal waveform.
mediate, and fine-tuning effective capacitance, C2, f and C3, f The drain current of transistor M3 , Id3 , overshoots from
are the fixed part of C2 and C3 , respectively, that are compa- 0 mA at X to a maximum current at Z when the sinusoidal
rable to the associated parallel parasitic capacitors in addition waveform of Vg2 starts to drop from its maximum value.
to the layout parasitic capacitors. G m3 is related to the large current change during the conduc-
For C2,min to effectively tune the maximum frequency, tion cycle that is associated with Vgs change. By approximating
it should remain greater than the parasitic capacitors. Increas- the slope of X Z ≈ the slope of XY, G m3 could be approxi-
ing the fixed part of capacitance C2 (C2, f ), to account for mated by the ratio of Id3 to Vg3 of the segment line XY .
the parasitics, lowers the maximum tuned frequency that may The coordinates (Id , Vgs ) of the point X are Id3 = 0 mA and
mandate decrease L to retain the maximum frequency. Vg3 with an amplitude of (1 − n)Vosc. The point Y lies on the

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TAHA AND MIRHASSANI: 24-GHz DCO WITH HIGH-AMPLITUDE STABILIZATION AND ENHANCED STARTUP TIME 2265

TABLE I
CC/ECC-DCO S C ORNER A NALYSIS R ESULTS

same horizontal line where Vg1 and Vg2 cross each other. The 
If ωosc is associated with the incremental increase in Ceqv  =
crossing point corresponds to the dc biasing point. Therefore, Ceqv +Ceqv , then the ratio of ((ωosc + ωosc ) /ωosc ) is equal
2 2
the coordinates (Id , Vgs ) of the point Y correspond to the M3 to (Ceqv /Ceqv + Ceqv ) and can be expressed as
biasing current Ib3 and voltage Vb3 . The biasing voltage Vb3

is a fraction of Vosc . Let Vosc = f (1 − n)Vosc , where f is a ωosc −2 Ceqv

1+ =1+ . (36)
fraction factor that is < 1. ωosc Ceqv
Since VY < V X , then G m 3 is a negative value and related Since (ωosc /ωosc )  1, the left side of (36) can be approx-
to the dynamic of operation. Therefore, G m3 and its absolute imated by the first-order Taylor expansion as follows:
value can be described as
ωosc Ceqv
IY − I X Ib3 1−2 = 1+ . (37)
G m3 = =− (31) ωosc Ceqv
VY − V X (1 − n)Vosc (1 − f )
Ib3 Using this transformation, results in
|G m3 | = . (32)
(1 − n)Vosc (1 − f ) ωosc Ceqv
=− . (38)
Substitution of (32) and G m1 ≈ (2Ibias /nVosc ) from (17) ωosc 2Ceqv
in (29) result in
Since the last term in (35) is  1, it can be ignored. By substi-
Ib3 = 2Ibias (1 − f ). (33) tuting (38) in (35), the ECC-DCO normalized amplitude can
The result in (33) reveals that Ib3 is proportional to Ibias . The be approximated to be
maximum value of Ib3 can be set to be equal to Ibias with 
Vosc (ωosc + ωosc )2 Ceqv
f = 0.5, for the design to be justified, while the optimum = =1− ≈1 (39)
Vosc ωosc
2 Ceqv
value is determined by the required G m3 considering the
for Ceqv  Ceqv . Therefore, once the condition in (29) is
amplitude stability in (29) and verifying the startup condition
in (8). satisfied, the amplitude has poor dependence on the tuning
capacitors. Conditions stated by (32) and (33) serve as design
It should be noted that the slope approximation depends on
criterion to assist the simulation-based design methodology in
the biasing condition, and it varies with the class of operation.
Moreover, the shape of the current depends on closeness of the obtaining a constant amplitude throughout the TR. Stabilizing
the amplitude is important for suppressing the amplitude-to-
frequency of the oscillation to the transistor transit frequency
phase conversion [12].
( f T ). Although the approximations are crude, they are useful
by providing an intuitive link between the biasing current of
the cross-coupled transistor and the tail biasing current. V. D ESIGN C ONSIDERATIONS
If the condition represented in (29) is satisfied, then R L ,P In this section, the results obtained from Sections II–IV are
is the only parameter that can affect the amplitude stability used to form a robust design methodology. Four oscillators are
across the TR since, as shown in (10), it changes with the designed and process corner simulation results are compared
frequency. with the mathematical derivations of the last sections.
In order to investigate the amplitude stability with the TR,
ωosc is modified by ωosc with ωosc  ωosc . Since R L ,P is A. CC-DCO Versus ECC-DCO Design Aspects
related to ωosc in (10), then
In order to verify the concept and prove the mathematical
R ∼
L ,P = R L Q 2 = (ωosc + ωosc )L Q L .
L (34) analysis, two versions of each fully differential ECC-DCO
(ECC1, ECC2) and CC-DCO (CC1, CC2) were developed

Vosc = 2Ibias R L ,P and the normalized amplitude for the
using TSMC 65-nm RFIC models. The process with corner
ECC-DCO can be expressed as
temperature analysis is performed for all of the four designs.

Vosc (ωosc + ωosc )2 ωosc ωosc
2
= = 1 + 2 + . (35) The performance results are listed in Table I. The values of L,
Vosc ωosc
2 ωosc ωosc
2 C1 , Vdd , Vb1 , and Vb2 for all designs are 88 pH, 680 fF, 1.2 V,

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2266 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 10, OCTOBER 2019

0.6 V, and 0.9 V, respectively, where R is the ratio of W3,4

to W5,6 and Iavrg is the average current consumption. Startup
time is measured as the time to reach 90% of Vosc .
The initial condition is applied deferentially in all simula-
tions. In order to compare the startup time of the CC-DCO
versus ECC-DCO, the same value of the initial voltage con-
dition is applied for both designs. The corner simulation
results for the four designs are shown in Fig. 6. The CC2 is
designed to sustain process and temperature variations, and it
passes the typical process corner at the typical temperature
of 25 ◦ C (typ.), fast-best process corner at low temperature
of −25 ◦ C (f.b), and slow-worst process corner at high
temperature of 75 ◦ C (s.w.).
ECC1 is designed with M1,2 and M5,6 being half of
the corresponding devices for CC2. With the same tuning
frequency, the performance of ECC1 is comparable or better
than that of the CC2, in spite of having G m1 and the tail
current is being halved. The s.w. corner for a startup is an
exception as the startup time is worse for the ECC1 than the
CC2. ECC1 improves the amplitude as compared to CC2 but
does not improve the startup time.
If the reduced device sizes in ECC1 are applied to design
CC1, then CC1 fails to oscillate under typ. and s.w corners.
If these devices are increased from being 1/2, the CC2 device
sizes in ECC1 to 3/4 the CC2 device sizes in ECC2, then
even with a 25% reduction in the tail current and a reduction
in Iavrg by 10.2%, 7.4%, and 16.9% for the typ, f.b, and s.w
corners, the amplitude is higher by 40% and 35% for the typ
and f.b corners, while it is increased by more than 100% for
the s.w corner.
The enhanced amplitude result proves the derived mathe-
matical relation in (26). G m3,4 with its minus sign decreases
the denominator and, thus, increases the amplitude.
The ratio between Vosc of the ECC and CC designs (Rvosc ) Fig. 6. Simulated corner analysis showing the waveform, amplitude, and
frequency under typical (typ), fast-best (f.b), and slow-worst (s.w) process
can be obtained by dividing (30) over (20) that results in and temperature corners. (a) ECC1-DCO. (b) ECC2-DCO. (c) CC1-DCO.
Ibias,ECC (C1 + C2 ) (d) CC2-DCO.
Rvosc = . (40)
Ibias,CC C1 Fig. 7(b) indicates the amplitude throughout the TR. Maximum
The ratio between the simulated amplitudes for ECC2 and amplitude points exist, and Vosc is higher for the ECC2 as
CC2 at the typ. corner is 1.4. The calculated value based expected from the analysis.
on (40) is 1.49, which is comparable to the simulation coun- M3,4 and M5,6 are low threshold devices of similar types.
terpart. Repeating the same for ECC1 and CC2 results in Prior to optimization, the size of M3,4 = M5,6 . G m3 is
1 and 1.03 for the simulated versus calculated amplitude ratios. optimized based on simulation by changing the sizes of M3,4
The comparable results between the hand calculations and the through varying R. Fig. 7(c) shows the effect of changing the
simulated results prove the derived mathematical equations. value of R on the amplitude taken at the minimum, middle, and
The startup time for ECC2 is reduced by 47%, 33%, maximum coarse tuning. The three graphs intercept at a point
and 72%, as compared to CC2, for the typ, f.b, and s.w that corresponds to R = 3.15. At this point, the amplitude
corners correspondingly. This result confirms that the negative is independent of the tuning capacitor. Fig. 7(d) shows the
resistance is stronger as derived in (3). Moreover, even with amplitude versus the TR with R = 3.15. The percentage of
gm1 for ECC2 being 0.75% of that of the CC2, the summing amplitude variation is calculated as
effect of gm,3 increases Rneg1 , and the startup time is reduced
Vosc,max − Vosc,min
significantly. %Vosc = . (41)
Vosc,24GHz
B. Amplitude Boosting and Stability Optimizing Based on the simulation results in Fig. 5(b). The amplitude
The effectiveness of the ECC-DCO in increasing and sta- varies across the TR by 22 and 32 mV for ECC1 and ECC2,
bilizing the amplitude across the TR is validated through respectively. However, it varies by just 7 mV for ECC2 with
simulation, and the expected mathematical results are verified. R = 3.15 in Fig. 5(d). Increasing R may stabilize the
Fig. 7(a) shows the coarse frequency tuning for ECC1,2 and amplitude within 7 mV across the TR. However, large R

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TAHA AND MIRHASSANI: 24-GHz DCO WITH HIGH-AMPLITUDE STABILIZATION AND ENHANCED STARTUP TIME 2267

increases the parasitic capacitors that affect the TR. Under the
restrictions of the tuning design requirements in Section III,
R is chosen to be 2 for ECC2 and the ECC-DCO design.

C. ECC-DCO Design Methodology

The developed design methodology is a combination of
hand calculations and simulation-based design. Low PN
requirement is considered. The transistors are biased at the
optimum noise figure current density (JOPT) of 0.15 mA/μm.
Vosc stability is optimized. Minimum Ibias is determined by the
optimized Vosc and startup condition is verified. The strategy
to build up the ECC-DCO structure shown in Fig. 1 is as
follows.
1) Set the tank inductor to the minimum feasible value.
Get Q L and R L ,P at the maximum tuning frequency
and calculate the maximum R L ,P (RP,max ) from (10).
2) Based on L, use (9) to calculate the maximum and
the minimum Ceqv (Ceqv,max and Ceqv,min ) that corre-
sponds to the minimum and maximum tuning frequen-
cies ( f osc,min and f osc,max ), respectively.

3) Let C2,max = mC1 and C2,max  > r C3,max , where m
and r are the variables for design optimization. Low PN

mandates that C2,max ≤ C1 . Therefore, m ≤ 1. Since the
intermediate and the fine-tuning design are a part of C2 ,
r should be > 1. Let m = 1 and r = 4, calculate C1
from (9).

4) Design C3,min 
= C2,min 
. Substitute Ceqv,min from step 2

and C1 from step 3 in (??), calculate C2,3,min  .
5) Set Vosc to the maximum allowed value Vosc,max by
the technology and the system requirements. Get Ibias
from (30) using RP,max from step 1 and Vosc,max .
6) M1,2 are designed with a minimum length defined by the
process. Considering the biasing at a current density of
0.15 mA/μm for low PN noise requirement, determine
the size of M1 from W1 = Ibias /0.15. Get gm1 and the
values of the parasitic capacitors from the simulator by
employing a simple simulating test circuitry.
7) Let Ib3 = Ibias by assuming f = 0.5 in (33). Use low
thresholds device model, size M3 using the simulator
considering Vds3 = Vgs3 = Vs1. Get Vs1 from the
outcome of step 6. Get gm3 and the values of the
parasitic capacitors from the simulator.
8) Verify the startup condition at the maximum tuning
frequency in (8) from the outcome of gm1 , gm3 , C1 ,

and C2,min in steps 6, 7, 3, and 4, respectively.
9) Iterate between steps 6, 7, and 8, to verify the startup
condition in step 8, by changing W1 or W3 or both,
keeping the same current density.
10) Use low thresholds device model, set the bias and the
size M5 using the simulator considering Vds5 = Vs1. Fig. 7. Amplitude stability simulation-based optimization. (a) Coarse
frequency tuning for ECC1 and ECC2 to show the TR. R = 2. (b) Amplitude
Get the values of the parasitic capacitors from the of ECC1 and ECC2 across the TR. R = 2. (c) Parametric analysis for
simulator. ECC2 amplitude versus R at the minimum, middle, and maximum tuning.
11) Using (4), (5), and (6), subtract C1 , C2,max  
, and C3,max (d) ECC2 amplitude across the TR with R = 3.15.
from the values of the parallel associated parasitic capac-
itors to calculate C1 , C2,max , and C3,max , respectively. 13) Optimize Vosc throughout simulation as in Section V-B.

12) Verify that C2,min 
and C3,min are not less than the parallel 14) Iterate between the Steps 3–13 by optimizing m, r , Ibias ,
parasitic capacitors in (5) and (6). W1 , W3 , and W5 .

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2268 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 10, OCTOBER 2019

Fig. 8. Schematic of ECC-DCO. Fig. 9. Simulated process corner analysis. (a) Process corner analysis for the
CC-DCO and the ECC-DCO loop-gain magnitude. (b) Process corner analysis
for the CC-DCO and the ECC-DCO loop-gain phase.
VI. ECC-DCO D ESIGN AND P RELAYOUT S IMULATION
TABLE II
The main structure of the ECC-DCO is constructed as ECC-DCO D ESIGN PARAMETERS
shown in Fig. 8. Based on (3), the ECC-DCO adds more
negative resistance at the startup. Moreover, it enlarges and
stabilizes the amplitude of oscillation.

A. ECC-DCO Design
Based on the design methodology in Section V-C, the single
turn central tap tank inductor (L t ) with 176.6 pH is first
selected and implemented in Metal 9. It achieves Q L of
43 at 24 GHz. Tail biasing current (I5,6 ) and M5,6 size is
determined by the required Vosc based on (30). PN is inversely
proportional to the square of Vosc that calls for maximizing
Vosc . However, larger Vosc is restricted by the allowed safe
voltage that can be applied to the transistor junctions without
causing a breakdown. The output is taken from the drain of
M1,2 that is connected to Vdd through Rd L d . Such that an
output buffer is not needed and the output power is increased
with the drain inductor L d .
Process corner analysis is conducted for the CC-DCO and
the ECC-DCO and the magnitude and the phase of the loop
gain are shown in Fig. 9(a) and (b), respectively. The worst
case for both designs is at the s.w. corner of the minimum
frequency. Based on the worst case, the minimum size of the
Fig. 10. Simulated large-signal transconductance (G m ) of the CC2 and the
transistors is optimized. While M1,2 size for CC2 includes the ECC versus the coarse tuning index.
required reliability factor to ensure startup under temperature
and process variations. W1,2 and W5,6 for the ECC-DCO are The ECC-DCO PN at 1-MHz offset is simulated against
decreased by 25%. W3,4 is triple W5,6 with R = 3. process corners. The resultant PN is tabulated in Table III at
Table II shows the values of the designed parameters for the minimum, middle, and maximum tuning frequencies. The
the ECC-DCO. ECC-DCO PN is always better than −101 dBc/Hz.
Based on the describing function approximation in (17), Considering mismatch and process variations, Monte Carlo
the plot of G m1 across the TR is shown in Fig. 10. The analysis is conducted for 1100 samples. Fig. 11 shows the
maximum required G m1 for the CC-DCO and the ECC-DCO simulated Monte Carlo analysis results for the amplitude and
are 19.6, and 18.6 mS, respectively, such that CC-DCO needs the loop-gain magnitude taken at the minimum, middle, and
an extra 1 mS to keep the oscillation steady. maximum tuning frequencies. The standard deviation for Vosc

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TAHA AND MIRHASSANI: 24-GHz DCO WITH HIGH-AMPLITUDE STABILIZATION AND ENHANCED STARTUP TIME
Fig. 11. Simulated Monte Carlo analysis considering process and mismatch at the minimum, middle, and maximum TR. (a) Monte Carlo analysis for the
ECC amplitude. (b) Monte Carlo analysis for the ECC loop-gain magnitude.
TABLE III
ECC-DCO PN A GAINST P ROCESS C ORNERS
Fig. 12. Unit capacitance cell structure. (a) MoM switched capacitor cell
for the CTB and ITB. (b) Varactor unit cell for the FTB.
at the minimum and middle tuning frequencies is 1.3 mV,
while it is 1.4 mV at the maximum tuning frequency. %Vosc
considering the mean values at the three tuning frequencies is
as low as 1.6%.
The mean value for the loop-gain magnitude is the worst at
the minimum tuning frequency as expected and agrees with
the process corner analysis.
B. ECC-DCO Frequency Tuning
Simultaneous tuning mechanism for wide TR with the
fine resolution is obtained by separate and overlapped tuning
capacitance banks based on (27) and (28). The two coarse
tuning banks (CTBs) and the intermediate tuning bank (ITB)
are implemented using binary-weighted metal-oxide-metal
(MoM) capacitors controlled by a 6-bit coarse word (CW[5:0])
and 3-bit intermediate word (IW[2:0)], respectively. The
fine-tuning bank (FTB) is implemented using binary-weighted
varactors. It is controlled using a 6-bit fine word (FW[5:0]).
The unit capacitance cells are shown in Fig. 12. It is imple-
mented to be similar to [20].
VII. P OSTLAYOUT R ESULTS
To verify the effectiveness of the modified topology, the
layout is accomplished for the designed ECC-DCO and CC2.
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2269
TABLE IV
P OSTLAYOUT P ERFORMANCE C OMPARISON
The postlayout with the parasitic extraction performance
results for the CC-DCO and the ECC-DCO are tabulated
in Table IV. While the CC2 amplitude varies across the TR
by 103 mV, the ECC-DCO amplitude varies by 12 mV.
Fig. 13(a) shows the postlayout frequency tuning for the CC
and the ECC at −25 ◦ C, 25 ◦ C, and 75 ◦ C. The tuning index
for the CC starts at 9 caused by less parasitic capacitors in
parallel with C2 . The temperature has the minimal effect on the
coarse tuning for both designs. The coarse, intermediate, and
fine-tuning steps for the ECC-DCO are 160 MHz, 50 MHz,
and 1.1 MHz, respectively. The intermediate and fine TR are
350 and 66 MHz, respectively, to provide the overlapping
between the banks.
Fig. 13(b) shows the amplitude variation with temperature
across the TR. The amplitude variations across the TR are
as low as 5.3%, 1.5%, and 6.8% at −25 ◦ C, 25 ◦ C, and
75 ◦ C, respectively. The increase/decrease of G m1 and G m3
is of the same polarity that is subtracted at the denominator
of (26) making the ECC-DCO less sensitive to temperature
variations.
Oscillating at 24 GHz, the PN at 1-MHz offset is shown
in Fig. 13(c) and (d) for the CC and the ECC, respectively.
The ECC improves the PN by 2 dB at 25 ◦ C and by 4 dB at
75 ◦ C, as compared to the CC PN. Driven by low amplitude
variations with temperature, the ECC PN deviates by only
1 dBc/Hz with temperature variation between −25 ◦ C and
75 ◦ C, as compared to 3-dBc/Hz deviation for the CC.
Fig. 14 shows the chip for the ECC-DCO. CC-DCO chip
has the same dimension and pads. The total chip area is
1 mm2 , which is pad limited. The core area fits in a rectangular
of 1.3 mm × 0.5 mm. To quantify the overall performance,
the figure of merit (FoM) and FOM for TR (FoMT ) are
2270 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 10, OCTOBER 2019

Fig. 13. Postlayout Simulation Results. (a) Frequency versus coarse tuning. (b) ECC-DCO amplitude across the TR at −25 ◦ C, 25 ◦ C, and 75 ◦ C.
(c) Oscillating at 24 GHz, the CC PN at −25 ◦ C, 25 ◦ C, and 75 ◦ C. (d) Oscillating at 24 GHz, the ECC PN at −25 ◦ C, 25 ◦ C, and 75 ◦ C.
TABLE V
P ERFORMANCE S UMMARY AND C OMPARISON

defined in (42) and (43) as in [4]

fcenter PDC
FoM = PN − 20log + 10log (42)
f 1 mW
f center T R% PDC
FoMT = PN − 20log . + 10log (43)
 f 10% 1 mW

where Pdc is the power dissipation and  f is the offset from

the center frequency ( f center ) of 24 GHz. Table V shows the
resultant comparison with the state-of-the-art mm-wave VCOs
and DCOs. The reported PN in [28] is −146.7 dBc/Hz because
the VCO consumes power in the range of a hundred, while
the maximum reported power among the rest is 24 mW. The
ECC-DCO has the best FoMT and the highest FoM with the
power consumption limited to few tens of milliwatt.
Fig. 14. Chip layout of the proposed 24-GHz ECC-DCO.
VIII. C ONCLUSION
In this paper, the modified topology of ECC-DCO achieves
better performance over a wide TR of 29% for SRR appli-
cations. Oscillation initiation is boosted up by an extra

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TAHA AND MIRHASSANI: 24-GHz DCO WITH HIGH-AMPLITUDE STABILIZATION AND ENHANCED STARTUP TIME
negative resistance without the need to increase the tail
current.
The amplitude and startup enhancement are achieved by
analyzing the proposed circuitry at startup and the large-signal
steady oscillation state. The derived equations serve as design
criterion and assist in the simulation-based design methodol-
ogy to optimize the amplitude stability.
The ECC-DCO is designed in Cadence using 65-nm RF
component models. Pnoise setup with SpectreRF is used to
simulate the PN. Simulation results for the ECC-DCO and
a robust CC-DCO show that, even with 24% reduction in
the power consumption, the amplitude of oscillation for the
ECC-DCO is boosted by 23%. The ECC-DCO amplitude
varies by 1.5% across the TR as compared to 19.6% vari-
ation for the CC-DCO. Startup time is reduced by 41%.
The ECC-DCO PN is 2 dB better than the CC-DCO PN.
The ECC-DCO achieves better FoM and FoMT than the
CC-DCO that confirms the enhanced achievements. In the
future, the ECC-DCO is to be implemented as a part of
ADPLL, which is suitable for FMCW generation or an indus-
trial measurement application.
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Iman Taha (S’18) received the M.Sc. degree in elec-
trical and computer engineering from the University
of Windsor, Windsor, ON, Canada, in 2004, where
she is currently pursuing the Ph.D. degree.
From 2006 to 2009, she was a Senior Analog
IC Design Engineer at Qimonda, Cary, NC, USA,
where she was involved in designing oscillators,
bandgaps, references, and low drop regulators for
the generator system of the DDR2,3 and graphic
SDRAM products.
Mitra Mirhassani (SM’14) received the Ph.D.
degree from the University of Windsor, Windsor,
ON, Canada, in 2007, where she was involved in
the development of a new type of arithmetic more
suitable for implementing neural networks.
In 2007, she joined the Electrical Engineer-
ing Department, University of Windsor, as an
Associate Professor. Her current research interests
include neural networks, mixed-signal arithmetic,
signal processing, and low-power low-noise com-
puter arithmetic.