Computer

Organization
Lab 14
Rundown
▪ Bit Values
▪ Operators
▪ Behavioral modelling
▪ Initial Block
▪ Memory
▪ Always Block
▪ If/Else
▪ Logic Distribution
▪ Clock Mechanism
▪ Tasks
▪ Quiz

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Bit Values in Verilog
Valu Meaning Color (Simulation)
e
0 Zero, Low, False Green
1 One, High, True Green
X Unknown or Garbage Red
Z Unconnected or high-impedance Blue

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 Operations (Selective)
Sr. No Operation Verilog Operator Example Remarks

1 Add + c = a + b; A and B must be of same bit size

2 Subtract - c = a - b; -do-
3 Multiply * c = a * b; Bit size of c must be N+M, where N and
M are bit sizes for a and b
4 Divide / c = a / b; Can only divide by 2 (on hardware)
5 OR | c = a | b; Operands must be of same length
6 AND & c = a & b; -do-
7 XOR ^ c = a ^ b; -do-
8 Not ~ c = ~a;
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Behavioral Modeling
Makes use of high-level constructs (if/else, loops)

Rules:
Left hand side must be declared as “reg”
Use of initial/always blocks

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Behavioral Modelling - Register
Specifically for Implicit storage – unless variable of this type is modified it retains previously assigned value

Regs Does not necessarily imply a hardware register

Register type is denoted by “reg”

–reg [<signed>] [<range>] <reg_name>;

– reg [7:0] y;

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Behavioral Modeling - Blocks
Two coding blocks can be used in
behavioral modelling

Initial block executes once at 𝑡 = 0

Always block executes repeatedly

at 𝑡 = 0 and afterwards

The choice of block depends on the

requirement of problem

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Initial Block – ROMs/RAMs
A block of memory (group of reg [7:0] ROM [0:3];
contiguous registers) can be
initialized as ROM using the
initial
initial block begin
ROM[0] = 5;
reg [<range>] <reg_name>
ROM[1] = 10;
[<depth>]; ROM[2] = 125;
ROM[3] = 100;
end

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Behavioral Modeling – Events
The execution of a procedural statement is triggered by:
▪ A value change on a wire
▪ The occurrence of a named event

A list of named events is called sensitivity list and can be provided as follows:
always @ (*)
always @ (A, B)
always @ (posedge clk)

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Example 1:
Comparator (A == B)
i0 i1 eq
0 0 1
0 1 0
1 0 0
1 1 1

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HDL Code
module comparator(i0, i1, eq);
input i0, i1;
output eq

reg p0, p1, eq;

always@(*)
eq = p0 | p1;

always @(i0, i1)

begin
p0 = ~i0 & ~i1;
p1 = i0 & i1;
end

endmodule
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Task 0: Half Adder
In1 In2 Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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Behavioral Modeling – Control
Structures
High level Codes such as
Conditional Syntax
if/else
Case
Loops
for
while
repeat

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Example 2: 4x1 MUX
Multiplexer is used to select one of the multiple lines at the output

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Behavioral Modeling – Control
Structures
If/Else Case Statement
always@(*) always@(*)
begin begin
if (A == 0) case (A)
out = in1; 0: out = in1;
else if (A == 1)
out = in2;
1: out = in2;
else if (A == 2) 2: out = in3;
out = in3; default: out = in4;
else endcase
out = in4;
end
end

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Task 1 (ALU Design)
An Arithmetic Logic Unit (ALU)
can perform multiple operations. Opcode/Function Operation Output
Write Verilog code for the 0 Addition 𝑜𝑢𝑡 = 𝐴 + 𝐵
following ALU capable of 1 Subtraction 𝑜𝑢𝑡 = 𝐴 − 𝐵
operations given in the table. 2 OR 𝑜𝑢𝑡 = 𝐴|𝐵
3 AND 𝑜𝑢𝑡 = 𝐴&𝐵
4 Left Shift 𝑜𝑢𝑡 = 𝐴 >> 𝐵
At the end, we will have a single 5 Right Shift 𝑜𝑢𝑡 = 𝐴 << 𝐵
output 𝑤 depending on which
operation was chosen.

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 opcode

Task 2: 8 bits
opcode[1:0]

4x1 MUX
Write Verilog Code for the 1
following circuit performing ALU
operations on ROM data. 2 𝟖

3 ALU out
ROM has 4Byte of data (𝟒𝒙𝟖) (4
locations where each location is 8 ROM (Lab
8
bit wide). Code)

4x1 MUX
Initialize the ROM with random
values for testing purpose. 𝟖

Extra Credit to students who can learn

and use module calling (so that 2
previous code is used as it is)
opcode[2:1]
It is the same opcode which is given to ALU

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 𝑷𝑪 𝟑
ROM
Splitter
Task 3: 𝟒 (Instructions) 𝟏𝟗 𝟖

19-bits
Consider that you have instructions
placed in a ROM (𝟖𝒙𝟏𝟗) with depth
𝟖 where each location is 𝟏𝟗 bit wide.
𝐷𝑎𝑡𝑎1
Instruction structure is as follows: ALU 𝟖
Opcode Value of A Value of B (previous
3 bits 8 bits 8 bits Lab Code) 𝒐𝒖𝒕

You are required to 𝐷𝑎𝑡𝑎2

1. Split the respective field
2. Use the previous ALU code to run the
instruction as per given opcode
(instruction)
Extra Credit to students who can learn and use module calling (so that
previous code is used as it is)

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Info: Constants in Verilog
Constants can be written in
Decimal (default)
13, ‘d13
Binary
4’b1101
Octal
4’o15
Hexadecimal
4’ha
You can write/assign any number e.g.
ROM[0] = 19’b001_01110101_1110000; //_ has no effect, it is used for convenience

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