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  • Test Vector

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    asmnabdnm
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    The document contains the expected input and output signal values for different states of a processor over multiple clock cycles. It shows the load, store, and hold states for the processor with the corresponding signal values at each clock cycle.

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    Test vector

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    The document contains the expected input and output signal values for different states of a processor over multiple clock cycles. It shows the load, store, and hold states for the processor with the corresponding signal values at each clock cycle.

    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    6 views4 pages

    Test Vector

    Uploaded by

    asmnabdnm
    The document contains the expected input and output signal values for different states of a processor over multiple clock cycles. It shows the load, store, and hold states for the processor with the corresponding signal values at each clock cycle.

    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    Load

    I/O signal Expected Values . .2 .3 .4 .5 .6


    I #clk 1 2 3 4 5 6 7
    I reset 0 1 0 0 0 0 0
    I step_en 0 0 1 0 0 0 0
    I opcode 0 0 0 0 0 0 0
    I ACK_N 1 1 1 1 1 0 1
    O IN_INIT 1 1 1 0 0 0 0
    O as_n 0 0 0 0 1 1 0
    O wr_n 0 0 0 0 0 0 0
    O MAC_state 0 0 0 0 1 1 2
    O ir_ce 0 0 0 0 0 0 1
    O gpr_we 0 0 0 0 0 0 0
    O select_pc 0 0 0 1 1 1 1
    O load 0 0 0 0 0 0 0
    O decode 0 0 0 0 0 0 0
    O dlx_state 0 0 0 1 1 1 1

    mr 0 0 0 1 1 1 1
    mw 0 0 0 0 0 0 0
    busy 0 0 0 1 1 0 1
    req 0 0 0 1 1 1 1

    store
    I/O signal Expected Values . .2 .3 .4 .5 .6
    I #clk 1 2 3 4 5 6 7
    I reset 0 1 0 0 0 0 0
    I step_en 0 0 1 0 0 0 0
    I opcode 0 0 0 0 0 0 0
    I ACK_N 1 1 1 1 1 0 1
    O IN_INIT 1 1 1 0 0 0 0
    O as_n 0 0 0 0 1 1 0
    O wr_n 0 0 0 0 0 0 0
    O MAC_state 0 0 0 0 1 1 2
    O ir_ce 0 0 0 0 0 0 1
    O gpr_we 0 0 0 0 0 0 0
    O select_pc 0 0 0 1 1 1 1
    O load 0 0 0 0 0 0 0
    O decode 0 0 0 0 0 0 0
    O dlx_state 0 0 0 1 1 1 1

    mr 0 0 0 1 1 1 1
    mw 0 0 0 0 0 0 0
    busy 0 0 0 1 1 0 1
    req 0 0 0 1 1 1 1

    hold
    I/O signal Expected Values . .2 .3 .4 .5 .6
    I #clk 1 2 3 4 5 6 7
    I reset 0 1 0 0 0 0 0
    I step_en 0 0 1 0 0 0 0
    I opcode 0 0 0 0 0 0 0
    I ACK_N 1 1 1 1 1 0 1
    O IN_INIT 1 1 1 0 0 0 0
    O as_n 0 0 0 0 1 1 0
    O wr_n 0 0 0 0 0 0 0
    O MAC_state 0 0 0 0 1 1 2
    O ir_ce 0 0 0 0 0 0 1
    O gpr_we 0 0 0 0 0 0 0
    O select_pc 0 0 0 1 1 1 1
    O load 0 0 0 0 0 0 0
    O decode 0 0 0 0 0 0 0
    O dlx_state 0 0 0 1 1 1 1

    mr 0 0 0 1 1 1 1
    mw 0 0 0 0 0 0 0
    busy 0 0 0 1 1 0 1
    req 0 0 0 1 1 1 1
    .7 .8 .9 .10 .11 .12 .13
    8 9 10 11 12 13 14
    0 0 0 0 0 0 0
    0 0 0 0 0 0 0
    100011 100011 100011 100011 100011 100011 100011
    1 1 1 0 1 1 1
    0 0 0 0 0 0 1
    0 0 1 1 0 0 0
    0 0 0 0 0 0 0
    0 0 1 1 2 0 0
    0 0 0 0 0 0 0
    0 0 0 0 0 1 0
    0 0 0 0 0 0 0
    0 0 0 0 1 0 0
    1 0 0 0 0 0 0
    2 5 5 5 5 6 0

    0 1 1 1 1 0 0
    0 0 0 0 0 0 0
    0 1 1 0 1 0 0
    0 1 1 1 1 0 0

    .7 .8 .9 .10 .11 .12


    8 9 10 11 12 13
    0 0 0 0 0 0
    0 0 0 0 0 0
    101011 101011 101011 101011 101011 101011
    1 1 1 0 1 1
    0 0 0 0 0 1
    0 0 1 1 0 0
    0 0 1 1 0 0
    0 0 1 1 2 0
    0 0 0 0 0 0
    0 0 0 0 0 0
    0 0 0 0 0 0
    0 0 0 0 0 0
    1 0 0 0 0 0
    2 4 4 4 4 0

    0 0 0 0 0 0
    0 1 1 1 1 0
    0 1 1 0 1 0
    0 1 1 1 1 0

    .7 .8 .9 .10
    8 9 10 11
    0 0 0 1
    0 0 0 0
    0 0 0 0
    1 1 1 1
    0 1 1 1
    0 0 0 0
    0 0 0 0
    0 0 0 0
    0 0 0 0
    0 0 0 0
    0 0 0 0
    0 0 0 0
    1 0 0 0
    2 3 3 0

    0 0 0 0
    0 0 0 0
    0 0 0 0
    0 0 0 0

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