Turkish Journal of Electrical Engineering & Computer Sciences Turk J Elec Eng & Comp Sci

(2021) 29: 2962 – 2982

http://journals.tubitak.gov.tr/elektrik/
© TÜBİTAK
Research Article doi:10.3906/elk-2010-101

Advanced single-loop discrete-time control for T-type voltage source inverter

with minimum capacitor voltage ripple modulation

Manh Linh NGUYEN, Phuong VU∗

Department of Industrial Automation, School of Electrical Engineering, Hanoi University of Science and Technology,
Vietnam

Received: 23.10.2020 • Accepted/Published Online: 26.03.2021 • Final Version: 30.11.2021

Abstract: This research focuses on improving the performance of the voltage source inverter (VSI), which has been
widely used in practical applications such as uninterruptible power supply (UPS), photovoltaic (PV) systems in stand-
alone mode. To reduce the total harmonic distortion (THD) of the output voltage without increasing the switching
frequency, the T-type three levels inverter with enhanced modulation strategy, which minimizes the voltage ripple of the
two input capacitors, is employed. In addition, a new single-loop fully digital control strategy in which various advanced
control techniques such as proportional-integral observer, one-step ahead minimum prediction error, and model-based
current command generator is also proposed to fulfill the strict requirements of the output voltage. The proposed control
strategy is capable of achieving excellent output voltage regulation and high robustness against the parameters variation
with low computational cost. Real-time simulations based on hardware in the loop (HIL) platform are conducted to
confirm the validity of the method.

Key words: Voltage source inverters, state and disturbance estimation, one step-ahead minimum prediction error,
T-type inverter

1. Introduction
Single phase voltage source inverters (VSI) have been widely used not only in UPS systems which are capable of
delivering emergent AC power to critical loads but also in photovoltaic (PV) systems in stand-alone mode. The
output voltage of a high performance VSI must be sinusoidal with low total harmonic distortion (THD) that
satisfies EN 62040-3 standard, ie. 5% maximum, if connected to 100% non-linear load, and 3% maximum if
connected to 100% linear load. Furthermore, good voltage regulation and quick transient response with sudden
changes of loads are also needed, i.e. 5% from nominal for 100% step load changes with full recovery within
three cycles maximum.
In order to fulfill the above mentioned requirements, many control strategies have been proposed in
the literature [2–12]. In [2, 3], conventional cascade control schemes based on inner inductor current-loop or
inner capacitor current-loop are investigated. These control schemes are capable of achieving high voltage
performance with low THD and quick response if the parameters of the output filter components are known
precisely. In practice, these parameters are normally inaccurate and time-varying according to the working
condition, following that the performance of the VSI can be degraded considerably. In [4], a proportional-
integral (PI) controller designed in output voltage synchronous reference frame is proposed to achieve zero
∗ Correspondence: phuong.vuhoang@hust.edu.vn

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 NGUYEN and VU/Turk J Elec Eng & Comp Sci

steady-state error. However, the design procedure of this method is complicated, and the computation time
is increased since trigonometric functions are employed in the coordinate transformation. In [5], the iterative
learning control (ILC) has been used to achieve low THD under nonlinear periodic loads. The slow dynamics,
large memory requirement and poor performance under non-periodic disturbances are the major problems of this
technique. The self-tuned feed-forward with harmonic feedback strategy proposed in [6] can also reduce the THD
of the output voltage significantly. In practice, this method is suffered from its complexity in implementation.
To further enhance the robustness of the closed-loop control system, the sliding mode control (SMC) with merits
such as insensitive to matched disturbances, quick dynamic response and easy to be implemented has also been
developed [7–9]. The dynamic of the system even can be made faster by using a time-varying sliding gain in
the sliding function [9]. Since these techniques are designed in continuous-time domain, the VSI is suffered
from the variable switching frequency which may increases the THD and power loss. To alleviate the variable
switching frequency problem, discrete-time sliding mode control (DSMC) has been adopted in [10] with a dual-
loops scheme, including an inductor current predictor and an inductor current controller. Nevertheless, the
chattering is still inevitable. In [11], an extended Lyapunov function based control is developed such that global
stability, fast dynamic response, and zero steady-state error can be obtained simultaneously. However, using
measured load-current, and especially its derivative to generate reference inductor current may face problems in
the case the load is nonlinear and distort due to the fact that the derivative of measured signal is very sensitive
to high frequency noise.
Most of aforementioned control methods are based on dual control loops, which may result in slow
transient response with load disturbance. In this paper, two solutions are offered to improve the performance
of the VSI. First, a T-type three level (3L) inverter [13, 14] is used to further reduce the THD of the output
voltage. An enhanced pulse width modulation (PWM) technique is proposed which not only guarantees the
voltage balance of the two input capacitors but also reduces the capacitor voltage ripple. Second, a new single-
loop fully digital control strategy is proposed to improve the dynamic performance of the control system. Instead
of controlling the output voltage directly as usual, the inner inductor current control loop is preserved. Hence,
current trimming function can easily be implemented. The set-point for the current loop is computed by a
current command generator such that the output voltage quickly tracks the sinusoidal reference one. Since the
calculation of the reference current is strongly dependent on systems parameters and load current, disturbance
observer-based [18–20] technique has been considered. In detail, a proportional-integral observer (PIOb) [15]
is employed to estimate the unknown disturbances caused by the modeling error and the unmeasured load
current. The advantage of this strategy is that the design procedure is simple and straightforward in tuning.
Furthermore, the closed-loop system is robust against the modeling error and load disturbances. Real-time
simulations based on hardware in the loop (HIL) platform are conducted to verify the effectiveness of this
proposed strategy.
To this end, the paper is organized as follows. Section 2 shows the system description. The PIOb is
designed in Section 3. The control design and enhanced PWM is presented in Section 4. Real-time simulations
with various loads and scenarios are implemented in Section 5 to verify the proposed solution’s performance.
Finally, the conclusions are shown in Section 6.

2. System description
The typical configuration of a single-phase T-type VSI is shown in Figure 1. Since the switching frequency
range of an IGBT is normally high in practice, i.e. 3kHz → 10kHz , the inverter can be considered as an

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ideal voltage source. Then, the dynamic of the VSI is mainly governed by the output inductance-capacitance
(LC) filter. The state-space equations describing the operation of the inverter in continuous time domain are
as follows:

Figure 1. Topology of the single phase T-type inverter.

ẋ(t) =Ax(t) + Bu(t) + d(t)

(1)
y(t) =Cx(t)

where,
[ ] [ ]
vo (t) −Rc didt
o (t)
− ioC(t) + d1 (t)
x(t) = y(t) = , d(t) = f
iL (t) d2 (t)
 ( ) [R V ]
Rc Rf [ ] (2)
− Rc
Cf − Lf
1 c d

A =  L1f  B = LVf , C = 1 0
R 0 1
− Lf − Lff
d
Lf

and −1 ≤ u ≤ 1 is the control signal.

In (2), iL (t) and io (t) are the inductor and the load current, Rf , Rc , Lf , Cf are the parameters of the
equivalent LC filter, d1 (t) , d2 (t) represent for the modeling errors due to the fact that all the parameters of
the inverter may be varied during operation.
For control design purpose, a discrete time state-space model derived from (1) is used in this paper:

Xk+1 = ΦXk + Γuk + fk

(3)
Yk = CXk

The corresponding state-space variables and matrices of the discrete-time system (3) are
[ ]
V
Xk = Yk = o,k
[IL,k ]
ϕ ϕ12
Φ=e ATs
= 11
ϕ21 ϕ22
[ ] (4)
∫Ts Aτ −1 Γ
Γ = e dτ B = A (Φ − I2 )B = 11
Γ
0 [ 21 ]
∫Ts Aτ f
fk = e d{(k + 1)Ts − τ }dτ = 1,k
0 f2,k

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where I2 is an unity (2 × 2) matrix, and Ts is the sampling time.

In this design, the output voltage Vo,k and the inductor current IL,k are chosen as the state variables
and measured. The load current Io,k is not measured and treated as a disturbance. This unknown term in
combination with the other uncertainties caused by the parameters variation may significantly degrade the
performance of the control system. To cope with the above problem, a discrete-time proportional-integral
observer (dPIOb) is employed to estimate the disturbances first. Then, the information getting from the
disturbance observer is included in the control design, which is based on the one step-ahead minimum prediction
error technique. By using the proposed control strategy, the closed-loop system not only has a quick transient
response but also robust against the parameters variation.

3. State and disturbance estimation

The observability matrix Oab and controllability matrix Cab of the continuous-time system (1) are derived from
(2) as
 ( ) 
Rc2 Vdc Rc Rf
[ ] Rc Vdc
− + 1
− Vdc
Cab = B AB =  KLf KL2f Cf Lf KLf  (5)
Rf Vdc
Vdc
KLf − RKL 2 −
c Vdc
KL2f
f

[ ]
[ ]
C I
Oab = = 2 (6)
CA A

Since

Vd2
|Cab | = − ̸= 0 (7)
K 2 L2f Cf
1
|A| = ̸= 0 (8)
Lf Cf

It can be concluded that Cab and Oab are not singular, which means the state-space system (1) is completely
observable-controllable. Then, the state and disturbance estimation can be designed with assumptions that:
Assumption 1: The sampling time Ts is sufficient small such that the controllability and the observability
of the discrete-time system (3) are preserved, which results in
[ ]
Φ − I2 I2
rank( )=4 (9)
−C 0

Assumption 2: The disturbance f (t) is smooth and the sampling time Ts is sufficient small such that

fk+1 − fk =O(Ts )

fk+1 − 2fk + fk−1 =O(Ts2 ) (10)

which means there always exists constant A and B such that

|fk+1 − fk | < ATs

|fk+1 − 2fk + fk−1 | < BTs2 (11)

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and if Ts → 0 ,

|fk+1 − fk | = 0

|fk+1 − 2fk + fk−1 = 0 (12)

Hence, the notations O(Ts ), O(Ts2 ) mean same order with Ts and Ts2 , respectively.
Define X̂k and fˆk as the estimation state and the estimation disturbance. The goal of the dPIOb is to
force X̂k → Xk and fˆk → fk as k → ∞ . The state-space equation of the dPIOb is [15]

X̂k+1 = ΦX̂k + Γuk + L1 (Yk − Ŷk ) + fˆk

fˆk+1 = fˆk + L2 (Yk − Ŷk ) (13)
Ŷk = CX̂k

where L1 and L2 are (2 × 2) designed matrices and

[ ]
V̂
X̂k = Ŷk = ˆc,k (14)
IL,k

Define the estimation errors as

X̃k = Xk − X̂k (15)

Ỹk = Yk − Ŷk (16)

f˜k = fk − fˆk (17)

From (3) and (13), the dynamic of the state estimation error is

X̃k+1 = (Φ − L1 C)X̃k + f˜k (18)

The one step-ahead disturbance estimation error can be obtain from (13) and (17) as follows,

f˜k+1 =fk+1 − fˆk+1

=(fk+1 − fk ) + (fk − fˆk ) − L2 CX̃k

=f˜k − L2 CX̃k + (fk+1 − fk ) (19)

From (18) and (19), the state-space equations of the estimation errors can be reformulated as follows:
[ ] [ ][ ] [ ]
X̃k+1 Φ − L1 C I2 X̃k 0
= +
f˜k+1 −L2 C I2 f˜k fk+1 − fk
[ ]
X̃
=(M − LG) ˜k + O(Ts ) (20)
fk
[ ] [ ]
[ ] X̃ X̃
Ỹk = C 0 ˜k = G ˜k (21)
fk fk

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where,
[ ]
Φ I2 [ ]T [ ]
M= , L = LT1 LT2 ,G = C 0 (22)
0 I2

As proved in [15], if Assumption 1 is satisfied, the pair of matrices (M, G) is always observable, which means
the matrix (M-LG) can be stabilized, i.e by using pole-placement technique. Then, it follows that

X̂k → Xk − O(Ts ) as k→∞

(23)
fˆk → fk − O(Ts ) as k→∞

The above analysis shows that the dPIOb can restrict the estimation error in the small region O(Ts ) in steady-
state. And normally, the gain matrix L is chosen such that the eigenvalues of (M-LG) is close to the origin of
the unit circle to reduce the response time of the observer. The estimated disturbances are then employed in
the control design introduced in the next section.

4. Control design and enhanced pulse width modulation (PWM) technique

4.1. Current controller
From (4), the state space model (3) can be rewritten in detail as follows:

Vo,k+1 =ϕ11 Vo,k + ϕ12 IL,k + Γ11 uk + f1,k (24)

IL,k+1 =ϕ21 Vo,k + ϕ22 IL,k + Γ21 uk + f2,k (25)

∗
To force the inductor current IL,k of the inverter tracks a desired current IL,k in the presence of the unknown
term f2,k , the current controller is designed as following.
Define the one step-ahead current tracking error ei,k+1 as

∗
ei,k+1 = IL,k+1 − IL,k+1 (26)

The control signal uk , which forces ei,k+1 to zero, can be founded by solving the following equation

ei,k+1 = 0 (27)

By substituting (25) into (27), a fundamental operation yields

1 ( ∗ )
uk = I − ϕ21 Vo,k − ϕ22 IL,k − f2,k (28)
Γ21 L,k+1

Since f2,k is unknown, its approximation is employed

f2,k ≈ fˆ2,k (29)

Suppose that the pole-placement design for the dPIOb results in

[ ]
ϵ ϵ12
L2 = 11 (30)
ϵ21 ϵ22

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From (13), (20) and (30), it gives

fˆ2,k =fˆ2,k−1 + ϵ21 Ṽo,k−1 + ϵ22 I˜L,k−1 (31)

Based on (28) and (29), the control action for the current loop is

1 ( ∗ )
uk = IL,k+1 − ϕ21 Vo,k − ϕ22 IL,k − fˆ2,k (32)
Γ21

The stability of the current-loop controller can easily be evaluated as following.

First, by substituting (25) into (26), then it gives

∗
ei,k+1 = IL,k+1 − [ϕ21 Vo,k + ϕ22 IL,k + Γ21 uk + f2,k ] (33)

Then, from (32) and (33), it can be deduced that:

ei,k+1 = f2,k − fˆ2,k = O(Ts ) (34)

which means ei,k+1 → O(Ts ) in steady-state since the properly operation of the dPIOb is proven in Section 3.
It can also be realized from (34) that the dynamic of the tracking error is mainly governed by the dynamic of
the observer. So, the poles of the dPIOb should be carefully chosen such that fˆ2,k quickly approaches f2,k .
Consequently, the tracking error approaches O(Ts ) region in one step later.

4.2. Current command generator

∗ ∗
To keep the output voltage Vo,k follows a desired voltage Vo,k , an appropriate reference inductor current IL,k+1
is needed for the current loop.
Define the generalized voltage tracking error Ev,k as

Ev,k = ev,k + λev,k−1 (35)

where 0 < λ < 1 is a design parameter which has strong influence on the dynamic of Ev,k , and ev,k is the
instantaneous voltage tracking error computed by

∗
ev,k = Vo,k − Vo,k (36)

The one step-ahead generalized voltage tracking error is

Ev,k+1 =ev,k+1 − λev,k

∗ ∗
=Vo,k+1 − Vo,k+1 − λ(Vo,k − Vo,k ) (37)

By using (24), (32) and (37), a fundamental operation yields

( )
∗ ∗ Γ11
Ev,k+1 = Vo,k+1 − λVo,k + ϕ21 − ϕ11 + λ Vo,k
Γ21
( )
Γ11 Γ11 ˆ Γ11 ∗
+ ϕ22 − ϕ12 IL,k + f2,k − f1,k − I (38)
Γ21 Γ21 Γ21 L,k+1

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∗
Based on (38), the current command IL,k+1 which forces Ev+1 = 0 is
( )
∗ Γ21 ( ∗ ∗
) Γ21
IL,k+1 = V − λVo,k + ϕ22 − ϕ12 IL,k
Γ11 o,k+1 Γ11
[ ]
Γ21 Γ21
+ ϕ21 − (ϕ11 − λ) Vo,k + fˆ2,k − f1,k (39)
Γ11 Γ11

Due to the fact that f1,k in (39) is unknown, its approximation is used instead

f1,k ≈ fˆ1,k (40)

where fˆ1,k is also computed from (13), (20) and (30) as

fˆ1,k =fˆ1,k−1 + ϵ11 Ṽo,k−1 + ϵ12 I˜L,k−1 (41)

with,

Ṽo,k−1 = Vo,k−1 − V̂o,k−1 (42)

I˜L,k−1 = IL,k−1 − IˆL,k−1 (43)

Finally, from (39)-(41), the output of the current command generator is

( )
∗ Γ21 ( ∗ ∗
) Γ21
IL,k+1 = V − λVo,k + ϕ22 − ϕ12 IL,k
Γ11 o,k+1 Γ11
[ ]
Γ21 Γ21 ˆ
+ ϕ21 − (ϕ11 − λ) Vo,k + fˆ2,k − f1,k (44)
Γ11 Γ11

The analysis of the voltage tracking error dynamic is similar to the aforementioned current control-loop. In
details, substitutes (44) into (38), it results in
Γ11 ( ) ( )
Ev,k+1 = f2,k − fˆ2,k − f1,k − fˆ1,k
Γ21
= O(Ts ) (45)

Then, substitute (45) into (35), it gives

ev,k+1 = λev,k + O(Ts ) (46)

The solution of (46) is

∑
k−1
ev,k = λk e0 + λi O(Ts )
i=0

λk − 1
= λk ev,0 + O(Ts ) (47)
λ−1

in which, ev,0 is the initial tracking error. Since 0 < λ < 1 , it can be concluded that
1
lim ev,k = O(Ts ) = O(Ts ) (48)
k→∞ 1−λ

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Equation (47) and (48) show that the voltage tracking error approaches the small region defined by O(Ts )
asymptotically. And the convergence speed is governed by λ . As λ is close to 0 , the convergence speed is fast,
and vice versa. However, fast convergence speed usually results in large reference current, which may exceed
the limitation of the power converter. Hence, this coefficient should be appropriately tuned. Finally, the block
diagram of the control system can be depicted as in Figure 2.

Lf

V C1
Cf V

V C2

iL
dPOb
eLS-PWM
(eq.13) Vac

iL, Vac, f 1k, f 2k

Uk

Controller Vref
(eq.44 and eq. 32)

Figure 2. The block diagram of the control system.

4.3. Enhanced Level shift PWM for capacitor voltage balance

Theoretically, the output voltage of the multilevel inverters exhibit lower THD in comparison with the con-
ventional ones [17]. However, the THD may be worse in practice due to the ripple of the capacitor voltage.
Hence, studies on PWM technique to maintain the balance of capacitor voltage with low ripple have received
great attention. In this studies, an enhanced level shift PWM (eLS-PWM) is proposed to cope with the above
mentioned problem.
As pointed out in [16], the conventional LS-PWM results in high capacitor voltage ripple following that
the THD of the output voltage is degraded significantly. To reduce the capacitor voltage ripple, a modified
LS-PWM is proposed [16] where the redundant switching states as in Table 1 are employed such that each DC
link capacitor is used for swapped π/4 period during the whole line cycle. The corresponding effective duty
cycle of the conventional LS-PWM and its modified one are shown in Figure 3a and Figure 3b, respectively.
In comparison with the conventional LS-PWM, the modified one can reduce the capacitor voltage ripple about
50% .
Aiming to high performance VSI applied to PV systems, this research proposes an eLS-PWM technique
to minimize the capacitor voltage ripple. In detail, Table 1 shows that the redundant switching states can be
use to charge or discharge the DC link capacitors without changing the output voltages. Hence, by monitoring
the capacitor voltage, an appropriate switching state can be chosen in every consequent PWM cycle such that
the capacitor voltage ripple is minimized. Conventionally, four carrier-waves in different levels are needed to

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Table 1. Switching states of single phase T-type inverter.

Vol. Seq. SA1 SA2 SA3 SA4 SB1 SB2 SB3 SB4 Vdc1 Vdc2
Vdc V1S1 ON OFF OFF OFF OFF OFF OFF ON - -
V2S1 ON OFF OFF OFF OFF ON ON OFF ↓ ↑
Vdc /2
V2S2 OFF ON ON OFF OFF OFF OFF ON ↑ ↓
V3S1 ON OFF OFF OFF ON OFF OFF OFF - -
0 V3S2 OFF OFF OFF ON OFF OFF OFF ON - -
V3S3 OFF ON ON OFF OFF ON ON OFF - -
V4S1 OFF ON ON OFF ON OFF OFF OFF ↓ ↑
−Vdc /2
V4S2 OFF OFF OFF ON OFF ON ON OFF ↑ ↓
Vdc V5S1 OFF OFF OFF ON ON OFF OFF OFF - -

Figure 3. Effective duty cycle of: (a) Conventional LS-PWM; (b) Modified LS-PWM.

implement the algorithm. However, most micro-controllers only support carrier-wave in one level. To solve this
practical issue, the original modulation index m is turned into four channels mA1, mA2, mB1, mB2 instead
of using four carrier-waves. The block diagram of the proposed PWM module is provided Figure 4, and the
value of each modulation index is changed in every consequent sampling instance according to the measured
capacitor voltage as described by Figure 5.
The comparative modulation index and capacitor voltage ripple between the LS-PWM used in [16] and
the proposed eLS-PWM is shown in Figure 6 and Figure 7, respectively. It is obviously seen that the proposed
method gives much smaller capacitor voltage ripple, i.e. Vripple ≈ 4V , in comparison with the method used in
[16], i.e., Vripple ≈ 30V .

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Figure 4. Block diagram of the proposed eLS-PWM module.

Figure 5. The proposed eLS-PWM algorithm.

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(a). Implementation of LS-PWM

4 mA1

modulation index
mA4
2
mB1
0 mB4
-2 Carrier
0 0.005 0.01 0.015 0.02 0.025 0.03
(b). Effective duty cycle of [15]
2
mA1

-2
0 0.005 0.01 0.015 0.02 0.025 0.03
(c). Effective duty cycle of our proposed LS-PWM
1
0
mA1

-1
-2

0 0.005 0.01 0.015 0.02 0.025 0.03

Time(s)

Figure 6. Comparative modulation index.

(a). Conventional LS-PWM

250
Vdc (V)

200

150
0 0.01 0.02 0.03 0.04 0.05 0.06

(b). Modified LS-PWM

210
Vdc (V)

200

190

0 0.01 0.02 0.03 0.04 0.05 0.06

(c). Our proposed LS-PWM

202
Vdc (V)

200

198
0 0.01 0.02 0.03 0.04 0.05 0.06

Time (s)

Figure 7. Comparative capacitor voltage ripple.

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5. Hardware in the loop simulations and discussion

In this section, simulations based on HIL platform are conducted for a 5kVA single phase T-type inverter.
Compare to simulations using Matlab/Simulink, which is implemented by personal computer only, the HIL-
based simulation shows more advantages because both control software and hardware are test in real-time [21].
In addition, the HIL simulation particularly suits with control design of high risky plants since the practical
system is replaced by a high fidelity model [22, 23].
The HIL platform and the block diagram of the implemented VSI are shown in Figure 8 and Figure 9,
respectively. The t-type VSI with output LC filter is simulated in real-time by the Typhoon HIL 402 devices
whilst the proposed control algorithm is implemented by the TMS320F28379D - a 32bit real-time controller.
The parameters of the VSI used in simulation are provided in Table 2.

Figure 8. HIL system for real-time simulation.

Figure 9. T-type inverter implemented by Typhoon HIL.

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Table 2. Simulation parameters.

Lf 0.852 mH
Rf 0.1 Ω
Cf 20 µF
Rc 0.15 Ω
C1 , C2 470µF
Vdc 400 Vdc
Ts 100 µs
fsw 10 kHz
√
Vo∗ 220 2sin(2π50t)

Corresponding to the parameters provided in Table 2, the state matrices of the discrete-time system (3)
are
[ ]
0.7160 4.5092
Φ= (49)
−0.1058 0.7202
[ ]T
Γ = 113.5998 42.34 (50)

By placing the poles of the augmented system (20) close to the origin of the unit circle as following
[ ]
p = 0.05 0.1 0.15 0.023 (51)

the corresponding gain matrices L1 and L2 of the PIOb are

[ ]
1.5430 4.5092
L1 = (52)
−0.1058 1.5702
[ ]
0.8304 0.0000
L2 = (53)
0.0000 0.8550

In order to investigate the proposed control strategy performance, real-time simulations are carried out
in various scenarios where both linear and nonlinear load are employed. First, suppose that the system model
is perfect. Then, the simulation with rated resistive load is carried out. The transient responses of the control
system from light-load to full-load measured at analog outputs of the HIL is shown in Figure 10. By selecting
λ = 0.05 , it can be observed that the output voltage is quickly recovered within a few sampling cycles when
the load is suddenly changed. The THD analysis provided in Figure 11 shows that the THD in steady-state is
just 1.12% , which is much lower than the restriction value 5% of the EN 62040-3 standard.
The influence of λ on the output voltage transient-response is further investigated by additional HIL
simulations. In detail, Figure 12 and Figure 13 shows the results with lambda = 0.5 and λ = 0.9 , respectively.
It can be clearly seen that as λ increases, the response of the output voltage is slower which matches the
theoretical analysis in section 4.2.
The merit of the proposed capacitor voltage balance algorithm is shown in Figure 14. Without the
proposed algorithm, the ripple of the capacitor voltage at light load and full load are 7V and 65V , respectively.
The large voltage ripple at full load not only deteriorates the performance of the output voltage but also shortens
the capacitor’s life due to its raising internal temperature. With the proposed algorithm, the voltage ripple

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Figure 10. Transient response of the T-type VSI with Figure 11. THD of the T-type VSI with linear load.
resistive load.

Figure 12. Transient response of the output voltage with Figure 13. Transient response of the output voltage with
λ = 0.5 λ = 0.9

is just 2V in every load condition as seen in Figure 14(b), following that the reliability of the capacitor is
improved.
The performance of the proposed control system is then challenged by nonlinear load which is represented
by a rectifier with output capacitor. In this case, the output voltage is slightly distorted due to the high di/dt
of the load current as shown in Figure 15. However, the EN 62040-3 standard is still satisfied in this challenging
test where the THD of the output voltage is 3.35% as provided in Figure 16.
A very simple but effective solution to protect the inverter against overload is the current trimming
function which limits the amplitude of the inductor current. For most single-loop controllers, the current is not
restricted since the control variable is the output voltage. In contrast, the control strategy proposed in this
research keeps the inner inductor current-loop while the outer voltage-loop is replaced by a current command
generator, which is activated in every sampling cycle. As a result, the amplitude of the inductor current can
easily be handle cycle-by-cycle. Illustrative simulations where the amplitude of the current is limited at ±40A
are shown in Figure 17.

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(a) With proposed capacitor voltage balance algorithm

205 Vc1 Vc2

Capacitor voltage
200

195
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Time (s)

(b) Without proposed capacitor voltage balance algorithm

250
Capacitor voltage

Vc1 Vc2

200

150
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Time (s)

Figure 14. Input capacitor voltage ripple provided by HIL simulation.

Figure 15. Transient response of the T-type VSI with Figure 16. THD analysis of the T-type VSI with nonlin-
nonlinear load. ear load.

One of the most important property which guarantees the applicable of a control algorithm in practical
applications is the robustness against the modeling error since it is impossible to get a perfect model in practice.
For inverters, the tolerant of the output sine-wave filter can be ±10% whilst the internal resistance of these
devices may increase up to 50% in comparison with the nominal values. Figure 18 shows the results getting
from the HIL system under −10% tolerant of the parameters. Besides, the load is nonlinear with a rectifier and
a 100uF capacitor. It can be seen that the closed-loop system is still stable with low THD sinusoidal output
voltage, i.e., T HD = 2.74% . This robustness can be explained by considering the influence of parameters
variation to the position of the dPIOb poles. With ±10% tolerant, it can be seen from Figure 19 that the
poles of the dPIOb are still in the vicinity of their desired position, whilst the impulse responses are almost
maintained as in Figure 20. Consequently, ±10% parameters variation has little impact on the control system
performance.

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Figure 17. Simulation result when ±40A current trim- Figure 18. Simulation result with nonlinear load and
ming function is activated. inaccurate L, C values.

Pole-Zero Map
1
0.5 /T
0.6 /T 0.4 /T
0.8 0.7 /T 0.1
0.3 /T
0.2
0.6 0.3
0.8 /T 0.4 0.2 /T
0.5
0.4 0.6
0.7
Imaginary Axis

0.9 /T 0.8 0.1 /T

0.2 0.9
1 /T
0
1 /T

-0.2
0.9 /T 0.1 /T
-0.4
0.8 /T 0.2 /T
-0.6

-0.8 0.7 /T 0.3 /T

0.6 /T 0.4 /T
0.5 /T
-1
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
Real Axis

Figure 19. Pole-zeros map.

Comparative HIL simulations between the proposed method the proportional resonant (PR) controller,
which is popularly used to track the sinusoidal reference, are introduced. As can be seen in Figure 21 and
Figure 22, the proposed controller shows superior performance in comparison with the PR controller, not only
in transient but also in steady-state with same nonlinear load. In details, Figure 21 shows that it takes 5 line
cycles for the PR controller to track the reference voltage whilst the proposed method takes only few sampling
cycles. Since the proposed controller exhibits much faster response, especially in current loop, the distortion of
the output voltage can be significantly reduced as shown in Figure 22, i.e., 2.78 % with the proposed method
and 4.82 % with the PR controller. The feasibility of the controller is also expressed through its computational
cost since it takes 289 machine cycle corresponding to 1.45µs to accomplish the algorithm. In comparison with
the conventional PR controller, which takes 213 machine cycle to accomplish, the computational time of the
proposed method is just slightly increased, which means the system hardware is not necessary to be changed
while the achieved performance is superior.

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6 Impulse Response
10
2

To: Out (1)

0

-1

-2
Amplitude

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

10 5
5
To: Out (2)

-5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
10 -3
Time (seconds)

Figure 20. Impulse response.

Reference Proposed method PR controller Load current

200
Output (V)

0
-200
-400
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
t (s)
PIOb PR
240
RMS V (V)

220
200

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Time (s)

Figure 21. Comparative transient response between the proposed controller and the PR controller.
Reference voltage
300 Proposed method
PR method
200
Voltage (V)

100
0
-100
-200
-300
0.25 0.255 0.26 0.265 0.27 0.275 0.28 0.285 0.29 0.295 0.3
Time(s)

Figure 22. Comparative output voltage between the proposed controller and the PR controller with nonlinear load.

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Finally, the proposed method is also compared with the disturbance observer-based control [20], which
based on the inverse model in combination with an unity-gain low pass filter (LPF). Theoretically, both method
can force the tracking error to the small region O(Ts ). And the HIL simulation results with nonlinear load
and inaccurate model shown in Figure 23 and Figure 24 confirm the above mentioned conclusion. However, the
transient response as well as the stability margin of the method used in [20] mainly depends on the bandwidth
of the LPF, and has not been well investigated. For our proposed method, the design procedure is clear since
the stability analysis as well as the performance in both transient and steady-state can easily be carried out.

Figure 23. Proposed method with nonlinear load. Figure 24. Disturbance observer-based controller [20]
with nonlinear load.

6. Conclusion
In this paper, two solutions are offered to improve the performance of the single-phase VSI. First, the T-type
topology with eLS-PWM strategy which minimizes the capacitor voltage ripple is employed to reduce the THD
of the output voltage. Second, a new single-loop fully digital control strategy where various control techniques
such as one step-ahead minimum prediction error, proportional-integral disturbance observer are proposed to
enhance the system performance. HIL-based simulations with both linear and nonlinear load show that the
proposed strategy can achieve quick response, excellent voltage regulation, low THD satisfying EN 62040-3
standard and high robustness against the modeling error. Besides, the control design and tuning procedure are
also simple and straightforward. The low computational cost of the developed algorithm makes it possible to
be implemented in low cost digital controllers.

Acknowledgment
This research is funded by the Hanoi University of Science and Technology (HUST) under project number
T2020-SAHEP-004.

References

[1] IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems. IEEE Std 1547-2003 2003;
1-28.
[2] Ryan MJ, Brumsickle WE,Lorenz RD. Control topology options for single-phase UPS inverters. IEEE Transactions
on Industry Applications 1997; 33 (2): 493-501.

2980
 NGUYEN and VU/Turk J Elec Eng & Comp Sci

[3] Parvez M,Elias M,Rahim NA,Blaabjerg F,Abbott D et al. Comparative study of discrete pi and pr controls for
single-phase UPS inverter. IEEE Access 2020; 8: 45584-45595.
[4] Monfared M,Golestan S,Guerrero JM. Analysis, design, and experimental verification of a synchronous reference
frame voltage control for single-phase inverters. IEEE Transactions on Industrial Electronics 2014; 61 (1): 258-269.
[5] Deng H, Oruganti R,Srinivasan D. Analysis and design of iterative learning control strategies for UPS inverters.
IEEE Transactions on Industrial Electronics 2007; 54 (3): 1739-1751.
[6] Padmavathi L,Janakiraman PA. Self-tuned feed-forward compensation for harmonic reduction in single-phase low-
voltage inverters. IEEE Transactions on Industrial Electronics 2011; 58 (10): 4753-4762.
[7] Chiang SJ, Tai TL, Lee TS. Variable structure control of UPS inverters. IEEE Proceedings - Electric Power
Applications 1998; 145 (6): 559-567.
[8] Kukrer O, Komurcugil H,Doganalp A. A three-level hysteresis function approach to the sliding-mode control of
single-phase UPS inverters. IEEE Transactions on Industrial Electronics 2009; 56 (9): 3477-3486.
[9] Komurcugil H. Rotating-sliding-line-based sliding-mode control for single-phase UPS inverters. IEEE Transactions
on Industrial Electronics 2012; 59 (10): 3719-3726.
[10] Tai TL, Chen JS. UPS inverter design using discrete-time sliding-mode control scheme. IEEE Transactions on
Industrial Electronics 2002; 49 (1): 67-75.
[11] Komurcugil H, Altin N,Ozdemir S, Sefa I. An extended lyapunov-function-based control strategy for single-phase
UPS inverters. IEEE Transactions on Power Electronics 2015; 30 (7): 3976-3983.
[12] Abidi K, Xu JX,Xinghuo Y. On the discrete-time integral sliding-mode control. IEEE Transactions on Automatic
Control 2007; 52 (4): 709-715.
[13] Yang Y, Wen H,Fan M,Xie M,Chen R et al. A Constant switching frequency model predictive control without
weighting factors for t-type single-phase three-level inverters. IEEE Transactions on Industrial Electronics 2019; 66
(7): 5153-5164.
[14] Ngo VQB, Nguyen KM,Tran TT,Lim YC,Choi JH. A simplified model predictive control for T-Type inverter with
output LC filter. Energies 2019; 12 (1):31.
[15] Jeang LC. Applying discrete-time proportional integral observers for state and disturbance estimations. IEEE
Transactions on Automatic Control 2006; 51 (5): 814-818.
[16] Aly M, Ahmed EM,Orabi M,Shoyama M. An enhanced PWM method for loss balancing of five level T-type inverter
in PV systems. in IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, 2018;
pp. 2530-2535.
[17] Aly M, Ahmed EM,Shoyama M. Modulation method for improving reliability of multilevel T-Type inverter in PV
systems. IEEE Journal of Emerging and Selected Topics in Power Electronics, June 2020; 8 (2): 1298-1309.
[18] Chen W, Yang J,Guo L,Li S. Disturbance-observer-based control and related methods—an overview. IEEE Trans-
actions on Industrial Electronics 2016; 63 (2): 1083-1095.
[19] Sariyildiz E, Oboe R,Ohnishi K. Disturbance observer-based robust control and its applications: 35th Anniversary
Overview. IEEE Transactions on Industrial Electronics 2020; 67 (3): 2042-2053.
[20] Jang JY, Lee KB,Song JH,Choy I. Disturbance observer-based digital control for single-phase UPS inverters. In:
IEEE International Symposium on Industrial Electronics Proceedings (Cat. No.01TH8570), Pusan, South Korea,
2001; pp. 1095-1105.
[21] F Li et al. Review of real-time simulation of power electronics. Journal of Modern Power Systems and Clean Energy
2020; 8 (4): 796-808.
[22] Amin M, Aziz GAA,Durkin J,Mohammed OA. A hardware-in-the-loop realization of speed sensorless control of
PMa-SynRM with steady-state and transient performances enhancement. IEEE Transactions on Industry Applica-
tions 2019; 55 (5): 5331-5342.

2981
 NGUYEN and VU/Turk J Elec Eng & Comp Sci

[23] Huo, Yujia, Gruosso, Giambattista. Ancillary service with grid connected PV: a real-time hardware-in-the-loop
approach for evaluation of performances. Electronics 2019; 8 (7): 809.

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