OBJECTIVE 1 : Design of 5, 7 and 9 stages CSVCOs using 45nm CMOS technology with

Virtuoso tool in Cadence software.

5 stage Current Starved VCO

7 stage Current Starved VCO

9 stage Current Starved VCO
OBJECTIVE 2 : Design and development of low power VCO using leakage low power
techniques which can be used in PLL.

Schematic of 5 stage Sleep CSVCO

Schematic of 5 stage Stack CSVCO
Schematic of 5 stage Galeor CSVCO

Schematic of 5 stage Lector CSVCO

Schematic of 5 stage SKLCT CSVCO
 Schematic of 5 stage Sleepy stack CSVCO

OBJECTIVE 3 : To analyze the simulation results and calculate the parameters like noise, frequency,
delay using spectre simulator.

Parameters 5 Stage VCO 7 Stage VCO 9 Stage VCO

Power (nW) 42.7 50.96 59.01
Frequency (Ghz) 7.603 10.27 7.96
Delay (ps) 54.53 41.82 55.82

SNo. Low Average Area (μm2) Delay (μs) Frequency Gain Tuning
Leakage Power (W) (GHz) (Ghz/V) Range (%)
Power
Techniques
1 Galeor 48.20 e-9 37.5769 19.56 13.81 3.07 56.21
2 Lector 49.77 e-9 35.581225 32.25 14.34 3.19 6.07
3 Sleep 40.45 e-12 26.3169 327.8 72.11 16.02 98.76
4 Stack 49.56 e-9 56.4001 19.03 30.45 6.76 14.71
5 Sleep Stack 58.32 e-9 37.5769 0.4896 58.89 13.87 34.86