EE 421

Phase Locked Loop (PLL)

Students Team

Ali Alsugair Student ID: 436102257

Mohammed alfaifi Student ID: 435106908

Supervisor
Prof. Abdel-Fattah Sheta
OBJECTIVE:
1) To study, operate and analyze the PLL circuit.
2) To measure the transfer characteristics of the VCO section of the 4046 PLL IC chip.
3) To determine 𝝙ωH Hold-in range and 𝝙ωp Pull-in range.
4) To use the PLL as FM demodulator and recover an audio signal from an FM modulated
signal.

Equipment:
• Test board
• Function generator with internal & external FM capability
• Dual trace oscilloscope
• Digital multimeter
• Frequency meter
• 4046 PLL chip, resistance and capacitance

THEORY:
The PLL is basically a feed-hack controlled system intended for the applications where
frequency tracking is of great importance. It was first used for the synchronization reception of
radio signals and for keeping synchronization in TV scanning system. The block diagram of
the PLL system is shown in Fig.1

Figure 1: Block diagram of PLL

Phase detector PD: A circuit that produces a dc voltage that is proportional to the phase
difference between two signals:𝑉! (𝑠) = 𝐾! [ ∅"# (𝑠) − ∅$%& (𝑠) ]= 𝐾! . ∅' (𝑠)
𝑲𝒅 = 𝑪𝒐𝒏𝒗𝒆𝒓𝒔𝒊𝒐𝒏𝑮𝒂𝒊𝒏(𝑽/𝒓𝒂𝒅) , 𝑲𝒐 = 𝑻𝒉𝒆𝑪𝒊𝒓𝒄𝒖𝒊𝒕𝑪𝒐𝒏𝒗𝒆𝒓𝒔𝒊𝒐𝒏𝑮𝒂𝒊𝒏(𝑯𝒛/𝑽)
𝟏)𝒔𝝉𝟐
• The transfer function the loop low pass filter: 𝑭(𝒔) = 𝟏)𝒔(𝝉
𝟏 )𝝉𝟐 )

∅%&' (/) 0 0% 1(/)

• The overall transfer function: 𝑯(𝒔) = ∅() (/)
= 𝒔)0*
* 0% 1(/)

In steady state condition, i.e. the loop is locked, fout = fin. Any frequency variation will be
followed by a phase variation to keep the locking conditions.
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 Phase locked Parameters:
1) Hold-in range 𝝙ωH: This is the frequency range in which a PLL can statically maintain
phase tracking. A PLL is conditionally stable only within this range.
2) Pull-out range 𝝙ωpo : This is the dynamic limit for stable operation of a PLL. If tracking
is lost within this range, a PLL normally will lock again. It is designed for FSK, PSK, and
Frequency Synthesizers applications.
3) Pull-in range 𝝙ωp : This is the range within which a PLL will always become locked, but
the process can be rather slow. It is designed for FM, PM applications.
4) Lock-in range 𝝙ωL : This is the frequency range within which a PLL locks within one
single-beat note between reference frequency and output frequency. The operating-
frequency range of a PLL is restricted to the lock range. It is designed in critical applications
like military ones.

The quantitative relationships between these four parameters are plotted in Fig.2 for most
practical cases. (𝝙ωL < 𝝙ωpo < 𝝙ωp < 𝝙ωH).

Figure 2: The PLL key parameters

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PROCEDURE:

EXPERIMENT SETUP:
The 4046 chip is a phase-locked loop. A phase locked loop IC consists of a voltage-controlled
oscillator (VCO) and a phase detector. The 4046 is a 16-pin chip as shown in fig.3 and the experiment setup is
shown in figure 4.

Figure 3: 4046 Chip

Figure 4: Circuit for measuring the transfer curve of the VCO

MEASURING TRANSFER CHARACTHRISTICS OF THE VCO:

To measure the transfer characteristics of the VCO section of the 4046 PLL IC chip:

1) The circuit was wired as shown in Fig .4.

2) The voltage Vc at pin 9 was changed while measuring the output frequency using the frequency
counter and monitoring the waveform on the CRO.
3) The results were recorded in Table 1.

!
4) The above steps were repeated for C1 = 1 nF, 100 pF and with !! = 10 and 100 respectively.
"

Table 1: the value of frequency with difference voltage.

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 V(Volt) 𝑅" 𝑅"
= 10 = 100
𝑅# 𝑅#
Frequency (KHz) Frequency (KHz)
100pF 1nF 100pF 1nF
0 114.5 14.35 13.61 1.59
0.2 114.5 14.35 13.61 1.59
0.4 114.5 14.35 13.61 1.59
0.6 114.6 14.37 13.79 1.612
0.8 121.1 15.24 22.3 1.634
1 147.3 18.86 56.28 6.542
1.2 180.3 23.58 97.78 12.17
1.4 213.8 28.56 138.9 17.75
1.6 246 33.53 177.7 23.25
1.8 277.2 38.53 214.6 28.74
2 306.8 43.46 249.4 34.12
2.2 335.1 48.32 282.1 39.38
2.4 362 53.09 312.9 44.53
2.6 387.6 57.77 341.9 49.56
2.8 411.8 62.36 369.5 54.48
3 434.4 66.73 394.7 59.15
3.2 456.6 71.16 419.4 63.85
3.4 477.6 75.5 442.9 68.46
3.6 497.9 79.75 465.2 72.96
3.8 517.2 83.89 486.4 77.35
4 535.1 87.88 506.3 81.57
4.2 545.3 89.97 520.6 84.54
4.4 548.8 90.74 525.6 85.62
4.6 550.4 91.11 527.8 86.09
4.8 551.4 91.32 529.6 86.34
5 552 91.46 529.8 86.51

5) The measured output frequency verses Vc was plotted for the above conditions on the same graph.
6) The value of K was determined for each result.

VCO sensitivety at R1/R2=10 & c=100pF

600

500
Frequency(KHz)

400

300

200

100

0
0 1 2 3 4 5 6
Volt(V)

Figure 5: VCO sensitivety at R1/R2=10 & c=100pF

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 ! 𝟖𝟕.𝟖𝟖'𝟏𝟓.𝟐𝟒
At !! = 10 and C1 = 100 pF : Ko=slope = 𝟒'𝟎.𝟖
≈ 22.7 KHz/v
"

VCO sensitivety at R1/R2=10 & c=1nF

100
90
80
70
Frequency(KHz)

60
50
40
30
20
10
0
0 1 2 3 4 5 6
Volt(V)

Figure 6: VCO sensitivety at R1/R2=10 & c=1nF

! 𝟓𝟑𝟓.𝟏'𝟏𝟐𝟏.𝟏
At !! = 10 and C1 = 100 pF : Ko=slope = 𝟒'𝟎.𝟖
≈ 129.375 KHz/v
"

VCO sensitivety at R1/R2=100 & c=100pF

600

500
Frequency(KHz)

400

300

200

100

0
0 1 2 3 4 5 6
Volt(V)
Figure 7: VCO sensitivety at R1/R2=100 & c=100pF

! 𝟓𝟎𝟔.𝟑'𝟐𝟐.𝟑
At !! = 100 and C1 = 100 pF : Ko=slope = 𝟒'𝟎.𝟖
≈ 151.25 KHz/v
"

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 VCO sensitivety at R1/R2=100 & c=1nF
100
90
80
70
Frequency(KHz)

60
50
40
30
20
10
0
0 1 2 3 4 5 6
Volt(V)

Figure 8: VCO sensitivety at R1/R2=100 & c=1nF

! 𝟖𝟏.𝟓𝟕'𝟏.𝟔𝟑𝟒
At !! = 100 and C1 = 100 pF : Ko=slope = 𝟒'𝟎.𝟖
≈ 24.98 KHz/v
"

TUNING OF THE PLL:

1) The circuit was wired as shown in Fig. 5.

Figure 9: Circuit for tuning of the PLL

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 2) The input frequency was changed slowly around the VCO center frequency until a locking condition
is reached (both the input and output frequencies are the same).
3) The DC voltage at pin 9 was recorded when the loop is in look, and it was verified that it is within the
linear range of the control voltage Vc.
Vc = 1.89 v
4) While the loop in lock, The Hold-in range 𝝙ωH was found by slowly changing the frequency of the
input signal up and down the center frequency. The upper and lower limits was measured for which
the PLL can keep locking:
Lower Limit = 14.29 KHz
Upper Limit = 98.6 KHz

𝝙ωH = Upper Limit - Lower limit = 84.31 KHz

5) The input frequency was changed such that the PLL is out lock (input & output signals are not
triggered on the CRO). The frequency of the input signal was slowly decreased starting from the
upper limit of 𝝙ωH until locking condition is achieved, and the value was recorded.

PLL is locked at 89.5 KHz

This was repeated starting from the lower limit of 𝝙ωH, while increasing the frequency of the input
signal until locking condition is achieved, and the value was recorded.

PLL is locked at 14.5 KHz

6) The lock range of the PLL was calculated by finding the difference between these two limits.
Lock range 𝝙ωL = 89.5-14.5 = 75 KHz

FM DETECTION:
The PLL can be used as FM detector circuit by taking the output voltage from pin 9. In this situation, the VCO
control voltage (LF output) is exactly like the FM modulating signal.

1) With the same circuit used in PLL tuning, an FM signal with a frequency equals to the center
frequency of the PLL signal was applied from the function generator when used in Internal FM.
2) A suitable modulation index mf was selected.
3) The output waveform at pin 9 was observed and sketched on the oscilloscope with the following
settings: Xdiv= 1ms, Y2/div = 50 mV, Trigger LF.

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 Figure 10: The output waveform at pin 9 with suitable modulation index

Comment: The PLL worked as a demodulator to the FM modulated signal, the output signal is
the same as the modulating signal.

4) Step 3 was repeated for different values of mf.

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 Figure 11: The output waveform at pin 9 with unsuitable modulation index

Comment: When changing the modulation index to an unsuitable one, the shape of the
demodulated signal becomes distorted.

5) The signal at different frequency.

Comment: When the frequency is out of the lock in range, the shape of the demodulated signal
becomes distorted. And the PLL chip can demodulated FM signals if the frequency is in lock
range and the modulation index is suitable.

CONCLUTIONS:
In this experiment, we explored the PLL chip and its important applications in modern electrical
systems. At the first part of the experiment, the chip 4046 PLL has been examined and its pins were
understood correctly. After that, the VCO of the PLL was examined by measuring the output
frequency of each input voltage and a plot of the transfer characteristics of the VCO was plotted for
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different setups. Moreover, the tuning of the PLL was done by changing input frequency slowly and
the Hold-in range ∆wH was measured by subtracting lower limit from the upper limit of which the
PLL can keep tracking. Finally, the PLL was used as an FM demodulator by taking the output from
the loop low pass filter (LF), and it has been observed that the PLL should work in the linear region
and a modulation index mf should be in suitable values to maintain proper FM demodulation.

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