Adil Sidan

EP3291 - EP LAB – IV EP20B003

Lab Report
Exp 6: Phase detector and Phase locked loop

AIM:
To study the design and working on Phase-Locked Loops (PLLs), Phase Detectors, and using
PLL-IC565 in both Free and Locked mode.

APPARATUS:
PLL-IC565 Integrated Circuit, Breadboards, Connec ng Wires, Poten ometer, Screwdriver,
Voltage Source, Wire Strippers, Resistors, Capacitors, Oscilloscopes, Func on Generator, etc.

THEORY:
The basic working of a PLL is as follows:
• A sinusoidal signal is injected into the reference input.
• The internal oscillator then locks to the reference input.
• Frequency and Phase differences between the reference and internal sinusoidal signal is k
or O. The internal sinusoidal signal then represents a filtered version of the reference
sinusoidal signal.
A Phase-Locked Loop consists of a few parts:
• A Phase Detector (PD): This is a non-linear device whose output contains the phase
difference between the two oscilla ng input signals.
• A Voltage Controlled Oscillator (VCO): This is another non-linear device which produces an
oscilla on whose frequency is controlled by a lower frequency input voltage.
• A Loop Filter (LF): While this can be omi ed, (resul ng in what is known as a first order PLL)
it is always conceptually there since PLLs depend on some sort of low pass filtering in order
to func on properly.
• A Feedback Interconnec on: The phase detector takes as its input the reference signal and
the output of the VCO. The output of the phase detector, the phase error, is used as the
control voltage for the VCO.

Phase Detector (PD):

A phase detector is a mixer op mized for use with equal i/p frequencies. It is also called as
Phase Comparator because the amount of difference voltage 𝑉 depends on the phase angle
ϕ between the input signals. As the phase angle ϕ changes, so too does 𝑉 .
A simple phase detector circuit is constructed to study the performance in this experiment.
It gives 𝑉 propor onal to the me average of the phase difference between two signals.
The phase difference is in radians. The phase difference between the input and output signals
is measured using the scope. Let t be the period of the input signal, ∆t the me difference
between the input and output signals, and ϕ the phase difference between the two.
Then: ϕ = 2π · ∆t/t
Voltage Controlled Oscillator (VCO):
In a VCO, an input DC voltage controls the output frequency. In this experiment, an increase
in DC control voltage causes the VCO frequency to decrease.

Working of the Phase-Locked Loop (PLL):

An input signal with a frequency 𝑓 is one of the inputs to the phase detector. The other
input comes from a VCO. The output of the phase detector is filtered by a low pass filter. This
removes the original frequencies, their harmonics, and the sum frequency. Only the
difference frequency (DC voltage) comes out of the low-pass filter. This difference voltage 𝑉
then controls the frequency of the VCO. This feedback system locks the VCO frequency on to
the input frequency. When the system is working correctly, the VCO frequency equals 𝑓 , the
same as the input signal. Therefore, the phase detector has two inputs with equal frequency;
the phase angle between these inputs determines the amount of DC output.
If the input frequency changes, the VCO frequency will track it. For instance, if the input
frequency 𝑓 increases slightly, its phasor rotates faster and the phase angle increases. This
means less DC voltage will come out of the phase detector. The lower DC voltage forces the
VCO frequency to increase un l it equals 𝑓 . On the other hand, if the input frequency
decreases, its phasor slows down and the phase angle decreases. Now more 𝑉 will come
out of the phase detector; this causes the VCO frequency to decrease un l it equals the input
frequency. In other words, the PLL automa cally corrects the VCO frequency and phase angle.
The lock range 𝐵 is the range of frequencies the VCO can produce, given by:
𝐵 =𝑓 −𝑓
where 𝑓 and 𝑓 are the maximum and minimum frequencies of the VCO respec vely.
Once the PLL is locked on, the input frequency 𝑓 can vary from 𝑓 to 𝑓 ; the VCO will
track this input frequency and the locked output will equal 𝑓 .

Capture and Lock Mechanism of PLL:

Assume the PLL is free running or unlocked. The PLL can lock on to the input frequency
if it lies within the capture range, a band of frequencies centered on the free running
frequency. The formula for the capture range is given by:
𝐵 =𝑓 −𝑓
where 𝑓 and 𝑓 are the highest and lowest frequencies the PLL can lock onto. The capture
range 𝐵 is always less than or equal to the lock range 𝐵 and is related to the cut off
frequency of the low pass filter. The lower the cut off frequency, the smaller the capture
range.
In the experiment, PLL-IC565 is a 14 pin IC which can be connected to external
components to form a PLL. Pin 2 and 3 are differen al inputs to the phase detector. If a single
ended input is preferred, Pin 3 can be grounded and the input signal can be applied to Pin 2.
Pin 4 and 5 are usually connected. In this configura on, the VCO output becomes an input to
the PD. In those applica ons where the locked output is desired, Pin 4 is the output pin.
 An external ming resistor is connected to Pin 8, and an external ming capacitor is
connected to Pin 9. These two components determine the free running frequency of the VCO,
given by:
.
𝑓 =
.
where 𝑅 and 𝐶 are selected to produce a free running VCO frequency at the centre of the
input frequency range = .
Pin 7 is the FM output and is used only when an FM signal is driving the phase detector.
In FM receivers, a demodulated signal comes out of this pin. This signal then goes to other
amplifiers and eventually comes out of the loud speaker.
There is a filter capacitor 𝐶 between Pin 7 and ground. This capacitor and an internal
3.6kΩ resistor form a low pass RC filter and remove the original frequencies, their harmonics,
and the sum frequency. The cut off frequency of this filter is given by:
.
𝑓 =
. .
The lower the cut off frequency 𝑓 of this filter, the smaller the capture range. In some
applica ons, the filter capacitor is omi ed and the capacitor range equals the lock range.

DIAGRAMS:

BLOCK DIAGRAM OF PLL – 565

WORKING OF PLL IN PERSPECTIVE OF PHASORS

CIRCUIT DIAGRAM FOR PHASE SHIFTOR

EXPERIMENTAL PLL CIRCUIT

OBSERVATIONS AND PLOTS:
Part 1: Time Difference ∆t and Phase Difference ∆ϕ between the input and output signals;
Phase Shi er.

Sl no. Potentiometer Resistance (in kΩ) Phase Difference in degrees

1 0.5 -208°
2 1 -237°
3 1.5 -259°
4 2 -273°
5 2.5 -288°
6 3 -295°
7 3.5 -302°
8 4 -309°
9 4.5 -316°
10 5 -321°
11 5.5 -324°
12 6 -326°
13 6.5 -332°
14 7 -332°
15 7.5 -332°
16 8 -339°

Plot:
Part 2: Study of PLL-IC565 in Free Running Mode.

Capture Range:

Sl No. 𝐶 in µF 𝑓 in kHz 𝑓 in kHz 𝐵 in kHz 𝑓 in kHz

1 0.01 9.09 3.07 6.02 3
2 0.047 1.32 0.444 0.876 0.3

FM Output:
Sl No Frequency 𝑓 in kHz 𝑉 in V
1 5.1 8.94
2 6 8.46
3 7 7.96

RESULT:
In this way, Phase Detectors and Phase-Locked Loops have been fully studied and their
working observed. Their inner working has been derived and understood, and their physical
implementa on (PLL-IC565) has been set up and used to verify the theore cal output.

PRECAUTIONS AND SOURCES OF ERROR:

 Power Supply should not be le on for too long since it can cause overhea ng which
may damage the Power Supply as well as the circuit itself.
 Care should be taken when inser ng the PLL-IC565 into the breadboard, ensuring that
the pins are properly seated. Failure to do this may result in damage to the IC.
 Wait for voltage/phase fluctua ons to se le down to a near constant value before
taking down the reading .