EE-222: Microprocessor Systems

Introduction to CPU Architecture

Instructor: Engr. Imran Abeel[imran.abeel@seecs.edu.pk]

 Recall: Basic Ingredients of a 𝝁-Processor
• Any useful microprocessor-based computing system must
have:
1. A Processing Unit:
– complex circuitry that manipulates data and controls I/O
devices according to the program stored in memory

2. Memory:
– To store programs.
– To store data.

3. I/O Devices:
– To allow information to be input and output
– LEDs, 7-Segment Displays, Video Monitors,
Keyboards, Motors, Relays

2
Block Representation of a Microprocessor

Central processing unit Memory/Registers

Arithmetic logic unitB I/O port & buses

3
Modeling Finite State Machines

Connecting the different parts:

• Connecting memory to CPU

• Connecting I/Os to CPU

4
 Memory
• Everything that can store, retain, and recall information.
– E.g. hard disk, a piece of paper, etc.

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 Memory characteristics
• Capacity
– The number of bits that a memory can store.
▪ E.g. 128 Kbits, 256 Mbits

• Organization
– How the locations are organized 4 bits
▪ E.g. a 128 x 4 memory has 128 locations,4 bits each 0

128 locations
1
2

• Access time

…
– How long it takes to get data from memory 127

6
 Memory Pinout
• D0-D7: are for data I/O
• An: are for address inputs
• WE: Write Enable
VCC
– is for writing data into memory
• OE: Output Enable GND VCC

– Is for reading data out from memory 8

• CS: Chip Select n
D0-D7

– is used to select the memory chip A0-An-1

WE
OE
CS

7
Connecting Memory to CPU

VCC

GND VCC

8
D0-D7

CPU n
A0-An-1

WE

OE
CS

8
 Writing to Memory
Writing to memory

Address
CS
Data

WE

Time
VCC

GND VCC

8
D0-D7

CPU n
A0-An-1

WE

OE
CS

9
 Reading from Memory
Reading from memory

Address
CS
OE
Data

WE
Time VCC

GND VCC

8
D0-D7

CPU n
A0-An-1

WE

OE
CS

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 Connecting I/Os to CPU
• CPU should have
lots of pins!
Mouse

Network
CPU Keyboard

Sound Card
Graphic Card

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 Connecting I/Os to CPU using bus

Address bus

Data bus
Write
Control bus Read

CPU
I/O 0 I/O 1 I/O 2 I/O n

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Connecting I/Os and Memory to CPU
Address bus

Data bus
Write
Control bus Read

CPU I/O 0 I/O 1 I/O 2 I/O n

VCC

GND VCC

n
A0-An-1
8
D0-D7

WE

OE
CS

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 Connecting I/Os and Memory to CPU using
bus
0

VCC
1

How could we manage it? 2

3

A0-An-1
GND

D0-D7

WE

OE
CS
0
Address bus

Data bus

Control bus Write

Read

CPU
I/O 0 I/O 1 I/O 2 I/O n

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 Connecting I/Os and Memory to CPU using
bus (Peripheral I/O)

VCC
0
1
..
63

A0-An-1
GND

D0-D7

WE

OE
CS
Address bus

Data bus
Write
Control bus Read
IO/MEM
CPU
I/O 0 I/O 1 I/O 2 I/O n

15
 Connecting I/Os and Memory to CPU using
bus (Memory Mapped I/O)
The logic circuit

VCC
0
1 enables CS when
..
How could we make the logic address is
15

A0-An-1
between 0 and 15

GND
circuit?

D0-D7

WE

OE
CS
Logic circuit
Address bus

Data bus
Solution
WriteWrite
Control1.bus the address range in binary
Read
2. Separate the fixed part of address

CPU
3. Using a NAND, design a logic circuit whose output
activates when the fixed address is given to it.
a7 a6 a5 a4 a3 a2 a1 a0
From address 0 ➔ 00000000 a4
I/O 16 I/O 17 I/O a5
18
a6
I/OCSn
To address15 ➔ 00001111 a7

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 Another example for address decoder
• Design an address decoder for address of 300H to 3FFH.

Solution
1. Write the address range in binary
2. Separate the fixed part of address
3. Design the logic circuit.

a10a9a9a8a8 a7 a6 a5 a4 a3 a2 a1 a0
a11a10
a11 a8
a9
From address 300H ➔ 001100000000 a10 CS
a11
To address 3FFH ➔ 001111111111

An easy way of
designing

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Modeling Finite State Machines

CPU Architecture

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 Inside the CPU
• PC (Program Counter)
• Instruction decoder
• ALU (Arithmetic Logic Unit)
• Registers

PC A
ALU B

CPU C
D
Instruction decoder
registers

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 How computers work 0 31h
31
1 C4h A [17]
2 26h BA

VCC
3 81h A  [6]
EAh
AA+B
4
[7]A
5 0h

A0-An-1
GND
6 5h

D0-D7

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Control bus Write
Read

ALU
CPU A
B
PC: 10 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

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 How computers work 0 31h
1 C4h A [17]
2 26h BA

VCC
3 81h A  [6]
EAh
AA+B
4
[7]A
5 0h

A0-An-1
GND
6 5h

D0-D7

WE
7

OE
CS
Logic circuit
Address bus 17

Data bus
Control bus Write
Read

ALU
CPU A
B
PC: 1 C 9

D I/O 16 I/O 17 I/O 18 I/O n

Inst. Dec. registers

31

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 How computers work 0 31h
1 C4
C4h A [17]
2 26
26h BA

VCC
3 81h A  [6]
EAh
AA+B
4
[7]A
5 0h

A0-An-1
55h

GND
6

D0-D7

WE
7

OE
CS
Logic circuit
Address bus 176

Data bus
Control bus Write
Read

ALU
CPU 9
A
B
PC: 321 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

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 How computers work 0 31h
1 C4h A [17]
2 26h BA

VCC
3 81
81h A  [6]
EA
EAh
AA+B
4
[7]A
5 0h

A0-An-1
GND
6 5h

D0-D7

WE
7

OE
CS
7 Logic circuit
Address bus
Eh
Data bus
Control bus Write
Read

+
ALU
E CPU A
9
B
5E

PC: 435 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

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 How Instruction Decoder works
Opcode Operand Opcode Operand

Instruction

Instruction

Operation Code Meaning

000 Ax
0011 0001 0 31h
1100 0100 1 C4h A [17] 001 A  [x]
BA
0010 0110 2 26h 010 A  A – register (x)
1000 0001 3 81h A  [6]
1110 1010 4 EAh
AA+B 011 AA+x
[7]A
0000 0000 5 0h 100 A  A + register (x)
0000 0101 6 5h
7
101 AA–x
110 Register (xH)  Register (xL)
111 [x]  A

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Von Neumann vs. Harvard architecture

Data bus Data bus

Code Data
Memory Address bus CPU Address bus Memory
Control bus Control bus

• Harvard architecture

Code Data
Memory Memory

Data bus
CPU Address bus
Control bus

• Von Neumann architecture

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 So Far: In General

Higher-Level Language temp = v[k];

v[k] = v[k+1];
Program (e.g. C) v[k+1] = temp;
Compiler
lw $t0, 0($2)
Assembly Language lw $t1, 4($2)
Program (e.g. MIPS) sw $t1, 0($2)
sw $t0, 4($2)
Assembler
0000 1001 1100 0110 1010 1111 0101 1000
Machine Language 1010 1111 0101 1000 0000 1001 1100 0110
Program (MIPS) 1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111
Machine
Interpretation
Hardware Architecture Description
(e.g. block diagrams)
Architecture
Implementation
Logic Circuit Description
(Circuit Schematic Diagrams)

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 Hardware Design Hierarchy

system

datapath control

code state combinational

multiplexer comparator
registers registers logic

register logic

switching
networks

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 Reading Assignment
• The AVR Microcontroller and Embedded Systems: Using
Assembly and C by Mazidi et al., Prentice Hall
– Chapter-1 -> section 3 and 4

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THANK YOU