Optical Interfaces for Silicon

Photonic Circuits
One of the biggest challenges in silicon photonics is coupling the very small optical mode
in silicon wire waveguides to the much larger optical mode of single-mode fibers in an
efficient manner. This paper discusses in detail the various approaches reported and
deployed in industry today.
D IEDRIK V ERMEULEN , Member IEEE, AND C HRISTOPHER V. P OULTON , Member IEEE

ABSTRACT | Efficient optical interfaces are challenging due
to the micrometer-scale wavelength of light. We provide an
overview and classification of the most successful and most
promising optical interface methods used for silicon photonic
integrated circuits. Coupling interfaces can be divided into
three main categories: chip-to-chip, fiber-to-chip, and free-
space-to-chip. Depending on this interface and the applica-
tion, one can opt for a diffraction-based grating coupler or
a mode-evolution-based edge coupler. The functional, perfor-
mance, design, development, packaging, and cost tradeoffs
for each method are discussed. We then analyze the recent
development of arraying optical emitting elements in optical
phased arrays for free-space applications such as LiDAR and
data communication.
KEYWORDS | Chip scale packaging; free-space optical
communication; gratings; optical coupling; optical
communication; phased arrays; silicon photonics
I. I N T R O D U C T I O N
Silicon photonics is a low-cost complementary
metal–oxide–semiconductor (CMOS)-compatible inte-
grated photonics platform. The base wafers are typically
150-, 200- or 300-mm silicon-on-insulator (SOI) wafers
with a thick buried oxide layer (BOX) ranging from 500
nm to 3 μm to isolate the waveguide mode from the
substrate. Ultra-compact integrated photonic circuits can
be realized due to the high refractive index contrast
between silicon and silicon dioxide [1].
Manuscript received November 6, 2017; revised March 27, 2018; accepted
August 5, 2018. Date of publication September 14, 2018; date of current version
November 20, 2018. (Corresponding author: Diedrik Vermeulen.)
The authors are with Analog Photonics, Boston, MA 02210 USA (e-mail:
diedrikv@analogphotonics.com).
Digital Object Identifier 10.1109/JPROC.2018.2865725
Conforming to CMOS-compatible process steps is both a
blessing and a burden. It brings a specific set of challenges
when optical interfaces to the outside world are necessary,
which is the case for most traditional applications. Other
platforms that were developed from the ground up for
photonics, such as III/V-based photonics, employ custom
grown base wafers with design freedom for optical inter-
facing. Initially, silicon photonics struggled with matching
the same level of performance as more mature and higher
cost technologies. The historical lack of a highly efficient
and minimally invasive edge coupling interface has been
the main reason for the slow adoption of silicon photonics
during the first decade of the 21st century. Furthermore,
silicon photonics does not have a true native laser solution.
When using an external or chip-coupled laser, light must
pass a chip-coupling interface twice, thereby doubling the
fiber
coupling penalty.
Now, the edge coupling interface problem has been
largely solved [2] and several hybrid laser solutions have
achieved high levels of maturity [3]. In addition, effi-
cient surface out-of-plane grating couplers have enabled
fast wafer-scale photonic circuit testing and coupling to
multicore fibers. Furthermore, large-area surface coupling
to free space is enabling a whole new field of applica-
tions such as light detection and ranging (LiDAR), free-
space communication, and massive parallel readout for
biosensing.
Optical chip interfaces can be classified into three main
categories as shown in Fig. 1. Light is coupled to or
from an optical fiber, another chip, or free space. These
categories can be subdivided into different purpose groups
that give rise to fundamentally different challenges. In
this paper we will first introduce the two most commonly
used coupling techniques, i.e., edge coupling by means
of an inverted taper and surface coupling by means of a

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 Vermeulen and Poulton: Optical Interfaces for Silicon Photonic Circuits
Fig. 1. Overview of coupling interfaces divided into three main
categories: chip-to-chip coupling, fiber-to-chip coupling, and
free-space-to-chip coupling. Example applications for each category
are given, arranged in two differentiating groups.
diffractive grating. We will then go over the set of coupling
metrics that need to be considered when determining and
designing an application specific coupling interface. In
the subsequent paragraphs we will go over state-of-the-
art coupling achievements for each medium and applica-
tion. Finally, we will review the recent work using these
coupling techniques to interface with free space, including
optical phased arrays for large-surface free-space inter-
faces forming adaptive steerable beams.
II. C O U P L I N G T E C H N I Q U E S A N D
METRICS
Coupling techniques are easiest to introduce when con-
sidering coupling to an optical fiber. Fig. 2 shows a sil-
icon photonics chip edge-coupled to a standard single-
mode optical fiber (Corning SMF-28). This figure gives
a feel for the dimensions involved when interfacing to
a chip. The optical fiber is only slightly larger than a
human hair and must be aligned to the waveguide with
submicrometer precision. Fig. 3 is a zoomed-in drawing
of the optical interface with 86.5% of the light confined
within the 10.4-μm mode-field diameter (MFD) of the
optical fiber. On the other side of the interface is a typical
Fig. 2. Scaled drawing of optical fiber-to-chip edge-coupling. The
optical fiber has a typical diameter of 125 μm which is only slightly
larger than the average width of a human hair (65 μm), whereas the
waveguide is submicrometer.
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Fig. 3. Scaled zoomed-in drawing of fiber-to-chip edge-coupling
indicating the optical fiber core with a typical diameter of 8.2 μm
resulting in a mode-field diameter of 10.4 μm at 1550 nm. A
single-mode silicon waveguide with typical core dimensions of 450
nm by 220 nm with most of the light confined within the core. The
large optical mode-field mismatch introduces 30-dB insertion loss.
single-mode submicrometer silicon waveguide with 80%
of the light confined within the 450 nm by 220 nm silicon
core. Without any mode-matching structures on the chip,
regular edge-coupling would result in a 30-dB optical
mode-field mismatch loss. Several solutions have been
proposed which expand the silicon waveguide core both
in-plane and vertically [4] but none have seen wide-scale
adoption due to integration difficulty and incompatibility
with planar processing technologies. Instead, adiabatically
narrowing down the silicon waveguide to a very narrow
tip, an inverted taper, is better suited for silicon photonics.
The optical mode increases in size, easily reaching a 2-μm
mode-size which matches well to small-core fibers. As
seen in Fig. 4, at a 150-nm waveguide tip width, most of
the optical power is contained within the SiO2 cladding.
When fabricated with state-of-the-art lithography tools,
Fig. 4. Intensity profile of the fundamental transverse electric (TE)
mode for a 150-μm-long silicon inverse-taper used as a mode-size
convertor. For a waveguide tip of 150 nm, the optical mode increases
in size to a 1/e2 mode-field diameter of approximately 1.8 μm.
2271
 Vermeulen and Poulton: Optical Interfaces for Silicon Photonic Circuits
Fig. 5. Scaled cross-sectional drawing of a surface grating coupler
etched into a silicon waveguide diffracting light into the first order
under an angle θ to a single-mode optical fiber.
silicon photonic waveguides can be tapered down reliably
to 180 nm/100 nm for 248 nm/193 nm deep-UV (DUV)
steppers [5]. Expanding the waveguide mode diameter
beyond 2 μm not only requires ultrathin and very long
tapers but one must also take into consideration the optical
leakage to the silicon substrate. Additionally, the mode
size becomes sensitive to the taper tip width fabrication
variations.
The alternative to edge coupling is surface or out-
of-plane coupling. Due to planar processing technology,
a structure that acts as a 45◦ tilted mirror is not an
option [6]. Instead, a grating is etched into the waveguide,
diffracting the light into the corresponding diffraction
orders. When the period of the grating is small enough
(smaller than one optical wavelength, which is about
550 nm for 1550-nm light in a silicon slab waveguide),
light will diffract in only one diffraction order. This compo-
nent is called a grating coupler and a cross section is shown
in Fig. 5.
Besides the fact that edge couplers and grating cou-
plers emit light along different geometrical axes, they
are fundamentally different components. An edge coupler
is an adiabatic transition, similar to impedance matched
transitions for high speed electrical signals, and are thus
very broadband (40 THz or several hundreds of nanome-
ters). A grating coupler, on the other hand, is by design a
grating and thus wavelength dependent with a typical 1-dB
optical bandwidth of 5 THz, or 40 nm, which matches the
telecom C-band. Furthermore, the large birefringence of
the silicon waveguide makes it difficult to fulfill the Bragg
condition for both transverse electric (TE) and transverse
magnetic (TM) mode at the same time. The nominal grat-
ing coupler is actually very polarization dependent, acting
as a 60-dB polarization filter [7]. Another key metric for
optical interfaces is the reflection or return loss. Coupling
loss is direction independent for single-mode nonmagnetic
systems due to reciprocity (the fiber-to-chip or chip-to-fiber
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coupling efficiency is the same). However, reflection can
be vastly different depending on which medium light is
transmitted from. Edge couplers and grating couplers both
suffer from Fresnel reflections at the coupling interface.
This can be readily solved by sufficiently angling the com-
ponents similar to angled optical fiber connectors, using
index matched epoxies between the two media, or using
anti-reflection coatings. The grating coupler has an extra
reflection source from the second diffraction order when
coupling perfectly vertical. This is the reason the nominal
grating coupler is designed to emit light under a small
angle as shown in Fig. 5.
Table 1 gives an overview of the most important met-
rics for optical interfaces. The nominal edge and grat-
ing couplers are the most straightforward realization of
these components. The optimized and specialized cou-
plers typically involve more invasive substrate engineer-
ing, extra photonic layers, specialized etches, increased
packaging challenges, grating apodization, or custom pho-
tonic design. The nominal edge coupler component is very
efficient, i.e., −0.5 dB, but can only address spot-sizes
up to 3 μm × 3 μm without coupling penalty. A grating
coupler on the other hand can address large spot-sizes
and even millimeter-scale spot-sizes with much better spot-
size to footprint ratio. However, it is more challenging
to decrease the coupling loss below 1 dB, couple both
polarizations at the same time, or increase the optical 1-dB
bandwidth.
III. F I B E R-T O-C H I P C O U P L I N G
Grating couplers [7]–[9] are very convenient components
for optical wafer probing and circuit testing with a fiber.
They do not require access to the edge of a chip such
that they can be accessed anywhere on an undiced wafer.
A more extreme example of wafer-scale probing is shown
in Fig. 6 where a gold metal grating was fabricated on
the fiber itself by nano-imprint transfer, thereby being
able to optically probe any silicon waveguide [10]. Once
the chips are yielded, the wafer is diced and packaged.
Table 1 Metric Table for Optical Interfaces. Nominal Edge Coupler and
Grating Coupler Metrics Are Compared. State-of-the-Art Edge Coupler
and Grating Coupler Metrics Are Given. Note that in Specialized Grating
Coupler No One Design Meets All Metrics and 1-dB Bandwidth Decreases
with Spot Size
 Vermeulen and Poulton: Optical Interfaces for Silicon Photonic Circuits

Fig. 7. SEM pictures of focusing 2-D grating couplers. (Left) Short

nonadiabatic taper configuration. (Right) Shallow aperture
configuration. Reprinted with permission from [23]. 2008,
c IEEE.

Fig. 6. (a) Testing an integrated nanophotonic circuit using metal

grating fiber probes. (b) Light is coupled between the fiber and the
waveguide via metal grating attached to the fiber facet.
(c) Two-dimensional field plot of metal grating-induced light
coupling between the waveguide and the fiber probe. Reproduced
reflection back into the waveguide [31], [32]. A grat-
from [10], 2008,
c AIP Publishing. ing coupler can be designed to couple any wavelength
by changing the period of the grating. Visible and mid-
infrared infrared grating couplers have been shown with
decent efficiency [33], [34] in Si3 N4 and Si, respectively.
The optical 1 dB bandwidth of a grating coupler can be
Finally, a fiber in a ferrule or fiber array is attached improved from 30 to 80 nm when Si3 N4 instead of Si
permanently using UV curable epoxy. A typical single-mode gratings are used due to the lower refractive index [35],
fiber (SMF-28) array with eight fibers costs less than $10. [36] and several wavelength bands can be coupled at the
A custom fiber array with small-core or lensed/tapered same time by accessing multiple sides of a grating [37]–
fibers is on the order of $50 to $300. Lensed fibers also [39]. Multicore or multimode fiber coupling is especially
need to be metalized for microwelding and packaged in suited for grating couplers because they can be arranged
a hermetic environment. This is why it is crucial to have in 2-D patterns [40]–[42]. An overview of grating coupler
good coupling efficiency to SMF-28 (10.4-μm MFD at optimization tradeoffs and technology can be found in [15]
1550 nm) when cost is a big driver for the final packaged and [43]–[45].
device. Furthermore, a large spot-size increases alignment Edge coupling by means of an inverted taper is the
tolerances and is thus beneficial for fiber packaging cost most broadly adopted fiber coupling method. Multiple
and post-bond shift power penalties [11]. When flatness chips can be tested simultaneously by dicing the wafer
of the package is a concern, grating couplers matched to in narrow strips, so-called bars, and perform bar testing.
SMF-28 are a less attractive coupling option due to the The inherent broadband and low polarization dependent
large 1.5-cm fiber bending radius. Nonetheless, companies loss makes them ideal for high-performance devices. Cou-
are using high-efficiency grating couplers in data-center pling efficiencies down to −0.5 dB [2], [46]–[49] have
transceiver products [12] and angle polished fiber arrays been demonstrated by removing the substrate under the
are a promising approach to reduce the package height inverted taper as shown in Fig. 8 [50]. Multiple fibers or
[13], [14].
Grating coupler efficiencies have been steadily improv-
ing over the last ten years with up to −1-dB coupling
efficiency to SMF-28 [15]–[20] and better than −0.5 dB
to small-core fiber [21]. Gratings can be made 2-D [22]
thereby coupling both fiber polarizations in orthogonal
directions on the chip, acting as a simultaneous polar-
ization splitter [23]; see Fig. 7 where the gratings were
curved to focus the light in a single-mode waveguide
and reduce the device footprint [24]. The best achievable
coupling efficiency to date for 2-D grating couplers is
around −3 dB [12], [25]–[27] with a 1-dB bandwidth of
30 nm, slightly smaller than the nominal 40 nm for 1-
D gratings. Alternatively, 1-D polarization splitting grat-
ing couplers have been demonstrated using both sides of
Fig. 8. Schematic structure of the mode-size converter. Left: top
the grating [28], [29] or using subwavelength engineer- view of converter; Right: 3-D structure of converter; Inset: the
ing [30]. Ultra-low reflection single polarization grating location of Si tapers (beams and air trenches are hidden for
coupling has been demonstrated with less than −40-dB simplicity). Reprinted with permission from [50]. 2011,
c OSA.

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 Vermeulen and Poulton: Optical Interfaces for Silicon Photonic Circuits

fiber cores can be connected simultaneously but only when

they are aligned in one dimension [51].

IV. C H I P-T O-C H I P C O U P L I N G

The monolithic silicon photonics photodetector solution
is based on an epitaxially grown germanium layer. These
detectors have very high speeds and have a typical 1A/W
responsivity up to 1550 nm. Above 1600 nm the respon-
sivity is poor, and to alleviate this, external photodetectors
are a viable solution. These can be either edge-coupled
or attached on top of a grating coupler as shown in Fig. 10. Photograph of fabricated Si hybrid laser. SOA chip is
Fig. 9 [52]. The grating coupled photodetector is a very butt-coupled to a silicon photonics chip by means of an angled edge
coupler to minimize reflections. Reprinted with permission
attractive solution because the detectors can be placed on
from [55]. 2012,
c OSA.
a wafer-scale without any special wafer preparations. Most
photodetectors work uncooled and heat sinking is not a
big concern. They also have a large aperture such that
the needed pick and place accuracy is well within current −1.6 dB between chips have been demonstrated. Although
technological capabilities. assembly throughput is still a bottleneck for this tech-
Coupling laser chips to silicon photonics is more chal- nology (∼1 min per bond), it can be expected that with
lenging than photodetectors due to the small laser mode the advancement of 3-D printing technologies in general,
spot-size and heat sinking requirements [53], [54]. Fur- photonic wirebonding could become common practice.
thermore, lasers are very sensitive to back reflections, Fig. 12 shows an overview of popular solutions for
which need to be reduced to −50 dB. Alternatively, an chip-to-chip coupling, commonly used when co-packaging
off/on-chip isolator can be used at the cost of complexity fully processed III/V-based optical amplifiers, lasers, and
and insertion loss. Laser-to-chip coupling efficiencies of photodetectors. Although many of them look similar at
−0.5 dB have been demonstrated with submicrometer first sight, there is a big difference in terms of heat
accurate chip placement tools. When coupling a semi- sinking, vertical/horizontal alignment tolerances, testing,
conductor optical amplifier (SOA), one mostly opts for packaging, and chip versality. Table 2 is an overview of
a reflective SOA (RSOA) to avoid the need to couple how each coupling method performs with respects to these
both sides of the SOA chip. Fig. 10 is a photograph of a metrics. The lowest thermal resistance is achieved by flip
butt-coupled reflective SOA chip, coupled by means of an chipping the dies onto a highly thermal conductive carrier
angled edge coupler to a wavelength dependent reflector such as AlN [method (b)] but this method has a bad
circuit on the silicon chip, forming a hybrid laser [55].
An exciting chip-to-chip coupling development is pho-
tonic wirebonding [56]. In electronic packaging, multiple
chips can be electrically connected by for example Au wire-
bonds. Similar technology for optical chip-to-chip packag-
ing is shown in Fig. 11. A high-resolution 3-D printer based
on two-photon polymerization allows for submicrometer
resolution printing, with feature sizes down to 200 nm and
optical quality surface finishes. Coupling losses down to

Fig. 11. Example of photonic wire bonds (PWB). (a) PWB

prototype connecting two SOI waveguides on the same chip. PWB
waveguide core consists of SU-8 and features a rectangle-like cross
section of approximately 2-μm width and 1.6-μm height. (b) PWB
chip-to-chip interconnect: SOI waveguides are displaced with
respect to each other by approximately 25 μm in the horizontal and
Fig. 9. Coupling scheme for III-V photodetectors bonded to SOI by approximately 12 μm in the vertical direction. (c) Optical
waveguide circuitry. Reprinted with permission from [52]. 2005,
c characterization setup of a PWB assembly linking two SOI chips.
OSA. Reprinted with permission from [56]. 2012,
c OSA.

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 Vermeulen and Poulton: Optical Interfaces for Silicon Photonic Circuits
Fig. 12. Schematic overview of popular chip-to-chip coupling and
packaging techniques. (a) Substrate-down edge-coupling. (b) Flip
chip edge-coupling. (c) Photonic wirebond assisted coupling. (d) Ball
lens assisted edge-coupling with isolator. (e) Ball lens assisted
edge-coupling with isolator in cavity. (f) Flip-chip edge-coupling in
cavity. (g) Dual-sided flip-chip edge-coupling in cavity. (h) Grating
coupler assisted vertical coupling.
score for almost all other metrics. Coupling methods where
the III/V chip is embedded into a silicon photonics cavity
for edge-coupling [methods (e), (f), and (g)], or placed
on top a grating coupler in the case of vertical coupling
[method (h)] enable wafer-scale packaging by means
of vision alignment and/or self-alignment features [57],
wafer-scale testability, and wafer-scale micropackaging for
hermetic sealing. However, these optimized production
methods require custom III/V and silicon photonics dies.
V. F R E E-S PA C E C O U P L I N G
There are many optical systems that utilize free-space
propagating beams for communication and sensing appli-
cations such as free-space data communication, optical
coherence tomography (OCT), ion and particle trapping,
LiDAR, and chemical sensing. With the tight integration of
silicon photonics, and the ability to create complex pho-
tonic circuits with waveguide routing, photodetectors, and
modulators, many of the complex systems used for these
applications can have integrated chip-scale realizations
with the proper chip-to-free-space emission technique.
Table 2 Relative metric score for chip-to-chip coupling methods shown
schematically in Fig. 12. (“N” stands for a neutral score)
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These applications can be broken up into two main
requirements of fixed beams and adaptive beams. Fixed
beams can be created with passive structures such as
grating couplers (emitting out-of-plane) and edge cou-
plers (emitting in-plane). Ranging applications such as
OCT [58], [59] and LiDAR [60] have been shown in sili-
con photonics using a fixed beam emitted from the chip
through an edge coupler incident on a sample/target. The
back-scattered light was also received through an edge
coupler and coherently processed leveraging the integra-
tion phase control capability of silicon photonics. However,
in these systems, due to the large divergence angle of a
single edge coupler, an off-chip external lens was needed
to adequately collimate the light for the application.
Grating couplers can also be used to transmit and
receive fixed beams via free space. Free-space grating
couplers have been used to realize a fixed-beam high-
resolution nanophotonic imager with an array of coherent
receivers, each with a receiver grating coupler [61]. Laser-
Doppler vibrometry has also been demonstrated with grat-
ing couplers combined with an on-chip optical frequency
shifter [62]. Grating couplers can also be engineered to
focus free-space beams above-chip for particle trapping
and addressing [63]. This is accomplished by engineer-
ing the grating pitch and emission strength to mimic a
Gaussian beam with the minimum beam waist above the
chip.
Fixed optical beams can also realize rapid large-scale
parallel readout without the need of aligning or packaging
output optical fibers. For applications that require dispos-
able inexpensive photonic systems, such as biosensors,
parallel readout of many emitted fixed beams onto an
infrared camera can be an inexpensive method to mea-
sure a set of output signals. This concept was achieved
in [64] where the resonances of multiple ring resonators
with different chemical receptors were rapidly measured
with parallel output optical beams from grating couplers
(see Fig. 13).
Fig. 13. Illustration of a biosensor platform utilizing ring
resonators that archives parallel readout of resonance frequencies
through free-space emitted beams. Reprinted with permission
from [64]. 2009,
c IEEE.
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 Vermeulen and Poulton: Optical Interfaces for Silicon Photonic Circuits
Fig. 14. (a) Schematic of phased array operation with a linear
phase front applied to the elements. (b) Large-pitched elements
producing grating lobes. (c) Small-pitched elements with no grating
lobes. (d) Increased number of elements to produce a smaller
divergence angle. Figure inspiration from [65].
Adaptive beams emitted off-chip can be created with
integrated optical phased arrays (OPA) that achieve beam
forming by tuning the individual phases and amplitudes
of arrayed emitting elements [65] [Fig. 14(a)]. Arbitrary
element tuning reconstructs a near field on the surface
of the chip which creates a given propagation profile
through Fresnel diffraction or far field through Fraunhofer
diffraction. If a linear phase front is applied across the
emitting elements, a diffraction-limited beam will form
with a certain angle of propagation. Altering this linear
phase front then steers the emitted beam. Electromagnetic
phased array technology has been well developed in the
microwave regime for RADAR applications, and has gained
great interest in the optical regime during the past decade
for on-chip solid-state beam steering. Originally introduced
in silicon photonics by Acoleyen et al. [66]–[68], since its
original publication in 2009, OPAs have seen tremendous
progress in scale, performance, and system integration
due to foundry-enabled large-scale photonic integration
and the development of advanced silicon photonic plat-
forms such as III/V-Si hybrid platforms and monolithic
CMOS. Furthermore, OPAs in InP-based platforms have
been realized [69] with monolithic lasers, phase shifters,
emitters, and detectors. However, demonstrations have not
scaled in size and complexity recently perhaps due to cost
limitations.
Conventional integrated OPAs can be realized with
a 1-D or 2-D array of emitters. Two-dimensional arrays
can achieve greater manipulation of the emitted electric
field allowing for arbitrary radiation patterns and 2-D
beam steering with element phase control [70], [71].
To perform 2-D beam steering with 1-D architectures,
the wavelength dependence of a grating-based emitting
element is commonly used (i.e., a wavelength-dependent
element factor) [72]. In general, both grating couplers
or edge couplers can be employed as emitting elements
in OPAs. However, for edge coupler elements, multiple
layers of edge couplers or a cylindrical lens is needed to
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have a reasonable vertical divergence angle. In 2-D arrays,
compact grating couplers are commonly used to minimize
element pitch. For example, in [70] the emitters used are
∼ 3 × 3 μm2 which is smaller than many grating couplers
used for fiber coupling.
For 1-D OPAs, millimeter-long grating couplers, alterna-
tively called waveguide grating antennas, can be combined
to form 1-D OPAs and create a large aperture in one dimen-
sion (i.e., highly directional element factor). They also
have the capability of achieving a tight spacing between
adjacent elements, on the order of a couple wavelengths.
This enables 1-D arrays to have a larger steering range
than 2-D arrays. Waveguide grating antennas have been
realized by creating very small perturbations along the
waveguide to emit over millimeters of length. This has
been done with a shallow partial etch [73], dielectric
overlays [74], or side corrugations [75]. These perturba-
tions can be apodized, along the length of the antenna for
uniform emission and designed for unidirectional emission
for high efficiency.
The spacing between emitting elements in an OPA
determines the location of grating lobes, i.e., diffraction
orders, which limits the nonaliased steering range of the
device [Fig. 14(b)]. The ideal spacing between elements
is λ/2, which does not produce grating lobes and allows
for a full 180◦ steering range. However, due to the small
wavelength of light and limitations in optical confinement
and fabrication, this pitch has yet to be achieved in out-of-
plane emitting OPAs. A demonstration with edge-coupler
emitters placed at λ/2 has been shown in [76]. Surface-
emitting OPAs with a uniform element pitch of 2.0 μm have
been demonstrated [77], [78] which enables 45◦ steering
range with 1550-nm input light. Recently, OPAs utilizing
nonperiodic element spacings have been demonstrated to
increase the steering range [73] (see Fig. 15) at the cost
Fig. 15. (a) Initial far field of an OPA without element phase
tuning. (b) Far field of an aperiodically pitched OPA after element
tuning and (c) far field of a uniformally pitched OPA showing grating
lobes. (d) Beam steering with 75 different element phase
distributions on the uniformally pitched phased array. Reprinted
with permission from [73]. 2016,
c OSA.
 Vermeulen and Poulton: Optical Interfaces for Silicon Photonic Circuits
Fig. 16. (a) Photograph of a 4 × 4mm2 OPA. (b) Main beam of the
OPA on an infrared card with a divergence angle of 0.021◦ × 0.021◦ .
Reprinted by permission from [79]. 2017,
c OSA.
of insertion loss in the main beam. In this work, an 80◦
steering range was achieved with a beam divergence of
0.14◦ × 0.14◦ , resulting in more than 60 000 resolvable
points when 2-D beam steering with a 100-nm tunable
laser. If utilizing a uniform emitter pitch, an 80◦ steering
range would require a 0.78λ pitch.
For long-range applications, an important parameter
of free-space coupling with lens-free OPAs is the emis-
sion aperture size which determines the diffraction-limited
divergence angle of the emitted beam [see Fig. 14 (c)
and (d)]. An OPA aperture size of 4 × 4 mm2 on a passive
silicon photonics chip has been shown with a divergence
angle of 0.021◦ × 0.021◦ [79] (see Fig. 16). This diver-
gence angle produces a small centimeter-scale beam width,
even after 100 m of free-space propagation. Furthermore,
a large receiver aperture size allows for a large collection
area which is crucial in applications such as LiDAR and
free-space communication. For uniformally pitched ele-
ments, due to the small spacing between elements required
to achieve a large steering range, the necessity for a large
aperture effectively becomes a need for a large number of
elements. This is a challenge for OPAs in standard silicon
photonics platforms due to the limitation of the number of
I/O. Furthermore, since grating antennas emit light out-
of-plane, conventional flip chip techniques may not be
useable in certain configurations. Monolithic integration
of photonics and driving electronics for element control in
commercial CMOS platforms have the potential to alleviate
these issues. In [77] an OPA with 1024 active elements was
shown with a unique control scheme based on grouping
subarrays that allows for the number of digital-to-analog
converters to scale with the square root of the number of
elements. This work demonstrated 45◦ beam steering of
a 0.03◦ × 20◦ beam (the 20◦ is estimated here and was
limited by the short grating coupler used).
Another interesting platform for OPAs is hybrid silicon
photonics with indium phosphide. Such a platform enables
lasers and even individual element optical amplifiers to
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be integrated with the OPA on a single chip, simplifying
packaging and alleviating the coupling loss from an off-
chip laser or an SOA. Integrated OPAs have been shown
in this platform with a 35-nm tunable laser coupled to
a 32-element OPA formed with waveguide grating anten-
nas [72]. In this work, 2-D beam steering was achieved
with a tunable on-chip laser and carrier injection-based
phase shifters. A steering range of 23◦ × 3.6◦ with a beam
divergence angle of 1◦ × 0.6◦ was demonstrated.
A major application of adaptive beams and OPAs is low-
form-factor solid-state LiDAR. The mass producibility and
tight integration of silicon photonics technology could real-
ize inexpensive LiDAR systems with on-chip beam steerers
combined with receiver photonic circuits with integrated
photodetectors. Recently, integrated LiDAR with silicon
photonic OPAs was shown for the first time with sepa-
rate transmitter and receiver OPAs coupled to a coherent
receiver [80] (see Fig. 17). These OPAs had an aperture
size of 500 μm× 100 μm and utilized a grouped cascaded
thermal phase shifter architecture for a simplified control
scheme. This control scheme can be beneficial for a small
number of elements (50 in this work) but a more robust
and scalable control scheme such as in [77] may be benefi-
cial for a larger number of elements. Frequency-modulated
continuous-wave LiDAR was performed and ranging was
achieved up to 0.5 m over a 20◦ steering range. The
steering range was limited by thermal crosstalk from the
element phase shifters. Resulting from the coherent LiDAR
detection method used, both velocity and distance could
be measured simultaneously.
Adaptive beams and OPAs also have applications in
free-space optical communication (FSO) due to the
ability to create a large on-chip aperture with inte-
grated optical modulators and photodetectors. A proof-
of-principle demonstration of a free-space optical link was
demonstrated in [81]. A data link with a range of 50 m
was achieved with an on-chip silicon modulator and OPA
Fig. 17. (a) Optical micrograph of an integrated LIDAR system
with a transmitter and receiver OPA coupled to a coherent receiver.
(b) Packaged system with epoxied fiber and wirebonds. Reprinted
with permission from [80]. 2017,
c OSA.
2277
 Vermeulen and Poulton: Optical Interfaces for Silicon Photonic Circuits

The unique flexibility of OPA emission profiles enables

the formation of exotic free-space adaptive beams. Optical
beams with angular momentum, which have applications
in data communication, can be generated and received
with an array of elements and a radial phase front as seen
in [42], [82], and [83] (see Fig. 18). Furthermore, applica-
tions requiring optical intensity gradients such as particle
trapping and lithography can benefit from OPAs forming
focusing beams [84] or quasi-nondiffracting beams such as
a Bessel beam [85]. These OPAs can emit beams that focus
at a point (or a line for quasi-Bessel beams) that have full-
width half-maximums on the order of 10 μm.

Fig. 18. (a) Layout and (b) optical micrograph of a silicon OAM
VI. C O N C L U S I O N
device for multiplexing five free-space beam OAM modes based on

the input port of the device. Inset shows the radial grating emitter.
(c), (d) Simulated and measured near field when port 0 is excited. (e),
(f) Simulated and measured far field when utilizing phase correction
with thermal phase shifters. Reprinted with permission from [82].
2012,
c OSA.
(however on separate chips) at a data rate of 100 Mb/s,
limited by the bandwidth of the commercial off-the-shelf
free-space photodetector used.
In conclusion, we have introduced the basic concepts
and tradeoffs of silicon photonics interfaces using edge
couplers and grating couplers. The application categories
of fiber-to-chip, chip-to-chip, and chip-to-free-space have
been explored with state-of-the-art examples. Silicon pho-
tonic optical interfaces have reached a maturity level com-
parable to other integrated photonic platforms, hence the
success in commercial applications. A whole suite of novel
free-space applications is enabled by phased arrayed grat-
ing couplers and edge couplers forming fixed or adaptive
beams.

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[85] J. Notaros, C. V. Poulton, M. J. Byrd, M. Raval, and
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2279
 Vermeulen and Poulton: Optical Interfaces for Silicon Photonic Circuits
Diedrik Vermeulen (Member, IEEE)
received the Ph.D. degree from Ghent
University/IMEC, Ghent, Belgium.
After his Ph.D. work, where his work
on silicon photonics fiber-to-the-home
transceivers was commercialized by a
university spin-off Caliopa (later acquired by
Huawei), he joined Acacia Communications
and worked there as a Principal Member
of the silicon photonics team, bringing the first silicon photonics
100G coherent transceiver to market for metro and long-haul
applications. In 2015, he joined the Photonics Microsystems Group,
Massachusetts Institute of Technology, Cambridge, MA, USA, as
a Research Scientist. He is currently the Director of Engineering
of Analog Photonics with more than ten years of experience in
the field of commercializing silicon photonics technology. He has
authored and coauthored more than 50 papers and conference
contributions in letters, journals, and conferences and is the
inventor of 15 patents.
2280 P ROCEEDINGS OF THE IEEE | Vol. 106, No. 12, December 2018
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Christopher V. Poulton (Member, IEEE)
received the B.Sc. degree (summa cum
laude) in electrical and computer engineer-
ing from the University of Colorado, Boulder,
CO, USA, in 2014, where he developed pho-
tonic crystal devices in an advanced CMOS
monolithic photonic platform. He received
the M.S. degree from the Massachusetts
Institute of Technology (MIT), Cambridge,
MA, USA, in 2016.
He joined the Photonic Microsystems Group, MIT, as an NSF Fellow
and an MIT Jacobs Irvine Fellow with the Morris Joseph Levin Award
for Outstanding Masterworks. There he was the Lead Researcher
on the LIDAR effort of the DARPA E-PHI program, demonstrated
the first coherent LIDAR with optical phased arrays and the first
millimeter-scale optical phased array, and was denoted a DARPA
Riser. He is currently the Optical Phased Array Lead at Analog
Photonics. He has authored or coauthored more than 30 peer-
reviewed journal and conference publications along with several
patents.