2019 IEEE 69th Electronic Components and Technology Conference (ECTC)

Flip-Chip III-V-to-Silicon Photonics Interfaces for Optical Sensor

Yves Martin, Jason S. Orcutt, Chi Xiong, Laurent Schares, Tymon Barwicz, Martin Glodde, Swetha
Kamlapurkar, Eric J. Zhang, William M. J. Green
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
Victor Dolores-Calzadilla*, Ariane Sigmund, Martin Moehrle
Fraunhofer Heinrich-Hertz Institute, Germany
*Present: Institute for Photonic Integration, Eindhoven U. of Technology, Eindhoven 5600 MB, The Netherlands
ymartin@us.ibm.com

Abstract - We demonstrate flip-chip solder assembly of InP
chips on Silicon-Photonic (Si-Ph) substrates aimed at high
volume manufacturing using typical microelectronic lead-free
solders.
In our show-case application, an InP die is both a light source
and a detector in an integrated optical methane gas sensor that
operates near 1.6mm. For high-resolution laser absorption
spectroscopy sensing, a single-mode tunable laser is desired. We
create an external cavity laser with InP as optical gain, butt-
coupled to a Si-Ph external cavity, which incorporates the laser’s
frequency selective elements. For minimal reflection at the InP-
Si interface, waveguides are angled to the facet, an index-
matching medium is applied between the mating surfaces, and
an anti-reflection coating designed for the index-matching
medium is applied to the optical coupling facet of InP chip.
Sub-micron alignment accuracy is obtained without high-
accuracy assembly tooling. Lithographically defined alignment
features on both InP and Si components allow reproducible
high-accuracy alignment. Interface throughput loss were
measured to be as low as 1.4 dB, and interface reflections are
more than 30dB smaller than main signal beams.
provide high optical throughput and very wide spectral
bandwidth suitable to the fabrication of high performance
external cavity lasers [5-10].
In many butt-coupled demonstrations, the required high-
alignment accuracy between single-mode waveguides from
III-V chip to Si-Ph substrates was provided via high-accuracy
alignment & bonding tools, often equipped with advanced
image recognition systems. This low-throughput assembly
technique brings high assembly cost and low scalability in
volume production. In this paper, we demonstrate an
assembly method where precision primarily resides in the
components themselves, with the goal of making the chip
placement a low precision operation. Highly optimized
lithographic and etching steps, inherited from decades of
innovation and development in micro-electronics, enable
wafer-level fabrication of micro-alignment features on Si
wafers that are key to the low-loss waveguide-to-waveguide
interface.

Our bonding method includes the well-known lead-free solder

Keywords - Silicon & III-V photonics; heterogeneous assembly;
flip-chip assembly; solder reflow;
I - INTRODUCTION
Heterogeneous photonics offers potential for high
performance and low cost in integrated optics devices [1]. A
cost-effective and high precision technology that combines
III-V chips and Silicon Photonics (Si-Ph) substrates enables
the fabrication of complex devices for optical communication
and for integrated optical sensing. A range of nascent
heterogeneous fabrication techniques [2,3,4] address the issue
of coupling single-mode III-V light sources to silicon
photonic components. Among them, butt-coupling can
joints that are prevalent in the microelectronic industry.
Solder provides a four-fold bond & connectivity between InP
and Silicon components: mechanical, electrical, thermal and
optical. The thermal contact, in particular, is highly efficient
through solder which is kept thin in our configuration. Heat
dissipated in the InP lasing junction is effectively conducted
through thin layers of InP and solder to the bulk silicon of the
substrate where it is efficiently spread and removed. A thin
solder layer also provides good mechanical stability even
under variation of ambient temperature. Furthermore, we
selected lead-free tin-based solder rather than gold-tin
eutectic: tin-based solder is more developed and available in
the microelectronic industry, the melting point is substantially
lower, and the alloy is more malleable and less brittle than
gold-tin thereby reducing fracture risks.

2377-5726/19/$31.00 ©2019 IEEE 1060

DOI 10.1109/ECTC.2019.00166
 II- SENSOR OVERVIEW
The motivation of this work was the fabrication of optical
integrated spectrometers for the detection of traces of
methane. They are to be deployed at natural gas production
fields, as well as at gas storage and distribution sites, and
serve as sensitive gas leak sensors. Details of the spectroscopy
and applications are described elsewhere [11-13]. The heart
of the sensor is a small (approx. 10 by 8 mm) Si-Ph
component with a bonded InP chip, shown on Figure 1. The
InP chip is butt coupled to waveguides on the Si-Ph substrate.
One essential component is a wavelength tunable External
Cavity Laser (ECL) having one reflector on one end of the
InP chip (the high-reflectivity coated rear facet) and the
Figure 1. CSi-Photonic integrated spectroscopic sensor. Top is a
view of the full sensor which measures approximately 10 x 8 mm.
Bottom is a diagram depicting the essential Si-photonic waveguides
and the InP chip
second one on the Si-Ph substrate (a Bragg-reflector). An
intra-cavity tunable ring filter, depicted on Fig.1, is part of the
ECL laser. The detailed operation of the ECL laser is the
subject of a separate publication [12].
TE radiation emitted by the ECL is rotated [14] to TM, split,
and directed into two long coiled waveguides at the surface of
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the Si-Ph chip for the purpose of sensing ambient gas.
Thereafter, the transmitted TM radiation is rotated back to TE
and directed to two sensitive photodetectors built inside the
InP chip. When the wavelength matches a resonance peak of
ambient gas (methane gas in our application where λabs =
1.656 um), some of the evanescent radiation around the
waveguides is absorbed by the gas and the resultant decreased
amplitude is detected by the photodetectors. One of the coiled
waveguides is enclosed in a sealed silicon cavity filled with
methane, and serves as a reference cell to precisely tune the
ECL wavelength at the peak gas absorption. Our InP chip was
therefore built with two purposes. As active component of the
ECL laser, it was designed to be a Reflective Semiconductor
Optical Amplifier (RSOA), with one reflective facet coated
with a high-reflective multilayer coating, and one facet coated
with an anti-reflective coating. The active III-V stripe is
forward biased and extends the full length of the chip. As a
second purpose, two side-detectors are built in the same
epitaxial layers as the main lasing strip, but extend only a
small fraction of the full chip length. Without forward bias,
radiation is absorbed over a few tens of microns and induces
photo-currents.
Butt-coupling of radiation was selected for several reasons.
Low coupling loss over broad wavelength range can be
obtained when III-V and Si-Ph components are precisely
aligned. Most importantly, our previous work had
demonstrated the ability to precisely align and bond the two
components in a way conducive to volume production
[15,16]. For this purpose, lithographically defined mechanical
stops are etched in both Si-Ph substrate and InP chip. External
forces, either mechanically applied or via surface tension of
solder when melted between substrate and chip, push the chip
into precise X-Y-Z alignment against the substrate.
III- DESIGN OF INP AND SI-PH COMPONENTS
Figure 2 shows details of an InP chip, with several key
elements indicated with arrows in Fig. 2.a. Four gold-coated
electrical contact pads appear in yellow, as well as the contact
strip which covers the emitter gain section of the InP chip, in
the center and along the full length of the chip. Five brown
recessed areas are built for mechanical positioning of the chip.
The outer four recesses will land on top of standoffs (posts)
formed on the Si-Ph substrate to provide alignment
registration in the vertical (Z) direction. The central recess is
deeper than the outer four recesses and is part of the lateral
alignment feature that is described later. The three ridge
waveguides correspond to the central IR emitter and to the
two IR photodetectors on either side of it. To facilitate the
separate biasing conditions needed for the RSOA and
photodetector sections, electrical isolation trenches are etched
to remove any p-doped or quantum well material below the
depth of the standard ridge etch. Fig. 2.b is a cross section
 alignment edge. The edge is angled to be parallel to the angled
waveguide to allow for positional uncertainty of the front
facet, defined by cleaving with a typical +/-10 μm variability.

Figure 3 shows the region of the Si-Ph substrate that receives

the InP chip. Through semiconductor processing steps, three
general types of features were created in the substrate for
coupling with the InP chip and are highlighted on Fig. 3 & 4:
mechanical structures for precise X-Y-Z alignment, solder
pads for bonding and for surface-tension induced pulling
forces during the melting phase, and optical waveguides with
mode widening. The overall area that receives the InP chip
has been recessed by nearly 20 μm below the top surface via

Figure 2. a. Bottom view of the InP chip which is 750 x 500 um in

size. Four electrical contact pads are visible, three of them are
connected to the three P-doped anodes of the three ridge
waveguides. Five brown areas correspond to recessed areas that
will land on 5 standoffs (pedestals) of the Si-Ph substrate. The
picture was inverted in the horizontal direction to match the views
of the Si-Ph chip below. Figure 3. View of the Si-Ph substrate. The final location of the
b. cross-section diagram of the InP chip, at the dotted line InP chip has been delineated with a dotted rectangle.
location on a., that schematically depict several of the doped and
electrical layers as well as ridges and isolation trenches at the
bottom of the chip.

diagram (not entirely to scale) of the chip along the dotted line
of Fig. 2.a. The 3 main components, forward biased gain
region of the emitter, and reverse biased detectors are
highlighted and built in close proximity to the active layer
near the bottom surface of the chip.

Another essential feature visible on Fig. 2.a is the lateral

alignment edge. The primary function of the trapezoidal-
looking central recess is for lateral alignment (in X-direction)
of the chip to the Si-Ph substrate. Precise X-alignment occurs
when the chip’s lateral alignment edge butts against the Figure 4. Cross sectional diagram of substrate and chips,
showing approximately scaled layers in the vertical direction and
central standoff of the Si-Ph substrate. Spacing between this structures for mechanical alignment in the Y-Z directions. Dotted
edge and the angled waveguides is highly accurate, since lines represent waveguides in both substrate (in the SOI layer) and
owing to lithography and process design: a single mask in the InP chip.
defines both the waveguides and the location of the lateral

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etching, as shown on the cross sectional diagram of Fig. 4.
Five standoffs (or posts) were left remaining at a height
corresponding to the top Silicon layer in the original Silicon-
On-Insulator (SOI) wafer. Four solder plated pads with round
reservoirs were defined at the bottom of the recessed area and
are electrically connected to lines at the top of the recess. Fig.
4 illustrates the vertical layers in both substrate and chip.
Using the SOI layer in the substrate and the optical active
layer in the InP chip as references and etch stops, the relative
height of the waveguides in both components can be precisely
set with an accuracy on the order of 0.1 μm or better. Fig. 4
illustrates Z-alignment of the two waveguides in dotted lines
facing each other, after the InP chip is placed over the
standoffs.
vertical offset is only 100 nm, precise control of the height of
the standoffs is possible. Electroplating involves deposition
of an Under-Bump Metallization (UBM) layer of Nickel, and
of lead-free solder. The final step removes a thin oxide
protection layer from the coiled sensing waveguides.
Waveguide cross-sections have been optimized near the
interface for both InP and Si-Ph chips to match the optical
modes for minimum insertion loss. Calculated elliptical cross-
sections of the modes are shown on Fig. 6. The resulting
insertion loss as a function of mechanical alignment
considerations is then shown in Fig. 7. The mode of the InP
chip can be widened further to relax the alignment precision
in the X direction by tapering the waveguides at the front
facet, but this initial demonstration was designed to use the
standard single-mode waveguide width of the InP chip.

Figure 6. Left: Calculated optical mode in the InP chip, in the

region near the coupling edge. Right: Calculated optical mode in
the Si-Ph chip in the region near the coupling edge. The waveguide
width and refractive index of deposited dielectrics have been
optimized to minimize coupling loss to the InP chip.

Figure 5. Overall process flow for the micro-fabrication of the Si-

Ph substrate

Figure 5 gives the overall sequence for the fabrication of the

Si-Ph substrate. Starting with an SOI wafer, the first steps
involve 193nm UV lithography to define the sub-micron
optical waveguides and associated components for ECL,
beam splitting and polarization control. Low roughness and
dimensional control of the waveguides is essential for low
transmission loss and for minimizing etalon fringes [17].
Next steps in the process flow involved mid-UV lithography
and thicker photoresist patterning, especially for deep RIE
etching or for contact patterning at the bottom of the recess
region. The recesses and standoffs are formed by first etching
down to the buried oxide layer of the silicon-on-insulator
substrate in the regions that standoffs are formed. The second,
full depth, etch step is patterned to form the standoff and
recess geometries. This process enables precise mechanical
definition of the lateral alignment features to the limit of the Figure 7. Calculated insertion loss between the InP and Si-Ph
mid-UV lithography alignment and CD control. The vertical chips for the case of a fixed 0.5μm gap of refractive index 1.48
material in the direction of optical propagation (Y-direction) as a
alignment precision is limited by the timed etch required to
function of vertical (Z-direction) and lateral (X-direction)
offset the optimal alignment of the InP chip mode. Since the misalignment..

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 VI - ALIGNMENT & BONDING OF THE INP CHIP
Assembly of the InP on Si-Ph calls for picking and placing
the flipped InP chip at a distance 10 to 20 μm from the desired
butting position, in both X and Y. This placement position
corresponds to having the five Si-Ph standoffs (visible on Fig.
3) being nearly centered in the InP landing regions (in brown
on Fig. 2). In this position, the chip rests on the four outer
standoffs and has free but limited motion range in X and Y,
as illustrated on Fig. 4. During the solder melting phase, the
plated solder on the Si-Ph substrate balls up and touches the
metal pads of the InP chip, subsequently to wet the entire
surface of the pad. Corresponding metal pads have been offset
in both X and Y directions, as illustrated in Fig. 4 and Fig. 8.
While in the melted phase, the solder surface tension pulls the
chip against the alignment stops in both X and Y direction
[18,19]. Fig. 8 shows the InP solder pads (in yellow) being
offset in the negative X and negative Y directions. Hence, the
overall pulling force and chip motion occur in the positive X
and Y directions on the figure, until the chip comes into
contact with X and Y alignment stops.
Figure 8. Composite picture of the 750x500 μm InP chip (rendered
transparently) overlaid over the Si-Ph substrate with highlighted
mechanical alignment stops.
The proper working of the solder surface tension forces hangs
on an optimized balance between lateral and vertical forces.
The vertical force is predominantly solder-induced, while
weight accounts for only approximately 1% of the total force.
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Two types of solder-induced forces account for the resulting
vertical force:
a. the vertical component of the tension force, around the
perimeter of solder pads, is a pulling downward oriented
force.
b. the hydrostatic pressure within the liquid solder, can
produce a relatively large vertical force. It can range from a
large downward pulling force to a large upward pushing
force, pending on the solder curvature according to the
Young-Laplace equation.
Ultimately, the hydrostatic pressure is a strong function of the
relative amount of plated solder. A shallow plated thickness
leads to a large downward pulling force which creates a
binding friction between the chip and standoffs and prevents
chip motion. An excess plating induces a large pushing force
that lifts the chip off the standoffs and fails the alignment in
Z.
To broaden the solder plating window, we had introduced
the concepts of solder reservoirs [20,21], seen as the round-
shaped pads on Fig. 3. Hydrostatic pressure in the molten
phase drives solder flow between reservoirs and chip-joining
pads to equilibrate solder volumes and compensate for over
or under plating. Meanwhile, the solder curvature sustained
by the reservoirs stays relatively shallow and constant, and
yields a desired small pushing force. Calculations were done
according to the model shown in [20]. Fig. 9 illustrates the
dependency of the vertical force on solder thickness, for
different reservoir diameters. Selection of reservoir diameter
and thickness were done for a small attractive vertical force
on the order of 40 μN and a plating window around +/- 2 μm.
Figure 9. Calculated vertical force on the chip solder pad (in
yellow) as a function of the solder thickness, for different solder
reservoir diameters. The overall vertical force must be attractive
(positive on the scale) and smaller than the lateral force, which is
on the order of 60 μN
Our initial attempts to align chips via solder tension forces
were hampered by unforeseen alloying effects between gold
on the InP pads and solder on the Si-Ph substrate. A protective
platinum barrier on the InP pads did not perform as expected,
exposing thick Au to solder and resulting in solid Au-Sn
intermetallic compounds formed before chip motion was
induced. In our earlier work [15], a thin Au layer served as the
wetting layer and we did not encounter this issue. As a
temporary solution, we manually pushed the chips into X-Y
alignment stops, and shortened the melting time of the solder
to a few seconds to minimize the amount of intermetallic
formation. The process was aided with the addition of a
temporary adhesive gel between chip and substrate, and by
loading the chip with an external weight. We are in the
process of modifying the InP pad metallization to minimize
the amount of gold and eliminate solid intermetallic
formation, and thereby recover self-alignment via solder
surface tension.
V - OPTICAL COUPLING AND RESULTS
Optical coupling was measured using modified Si-Ph
substrates having additional waveguides and optical ports that
were externally coupled to lensed fibers at the periphery of
the Si-Ph substrates. One waveguide in particular allowed
input of metered external light directly onto one of the photo-
detector through one optical coupling between Si-Ph substrate
and InP chip. A separate loop-back waveguide and two lensed
1 mm
Figure 10. I-R microscopy of a 30cm coiled sensing waveguide of the gas sensor under operation.
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fiber couplings served to calibrate the lensed fiber input loss.
Using an approximate photodetector efficiency of 0.9 A/W,
estimated previously in actively-aligned component testing,
we measured an optical transmission coefficient of about 0.73
which corresponds to a 1.4 dB loss through the InP to Si-Ph
coupling, which is similar to earlier results [15].
Proper tuning of the ECL is also pending on minimal
reflections at interfaces, going from the InP chip to the Si-Ph
substrate. To this effect, angled waveguides were selected and
designed for the interface to minimize specular reflections
back into the InP waveguide. Furthermore, anti-reflection
coating was deposited on the exiting surface of the InP chip
and a 1.4 index adhesive was applied between the butting
surfaces. Additional measurements indicated a minimized
reflection down to nearly -40dB of the transmitted radiation.
As a result, good single-mode ECL operation was obtained
with side mode suppression ratio of 50dB. Wavelength
tunability was obtained around a methane absorption line near
1650nm, and methane absorption peak was clearly resolved
with the coiled sensing waveguide [12]. Figure 10 illustrates
sub-milliwatt laser radiation going through a 30cm long
exposed waveguide. Weak scattering at imperfect transitions
between curved and straight portions of the waveguide, as
well as a few scattering particles, serve as hallmark for the
presence of the radiated light throughout the length of the
waveguide.
 VI - CONCLUSION
We demonstrate flip-chip assembly of an InP chip precisely
aligned and soldered to a Si-Ph substrate for the fabrication of
a spectroscopic sensor. Heterogeneous integrated components
include a tunable External Cavity Laser, sensor waveguides,
polarization rotators and splitters, and detectors, all operating
at a wavelength around 1.6um. Measured optical throughput
between butt-coupled InP chip and Si-Ph substrate indicated
a modest loss of 1.4dB, and a small reflections (between -30
and -40dB) that enables ECL single mode operation with
better than 50dB side-band suppression.
Our integrated optical gas sensor highlights a path to low cost
mass production of spectroscopic sensors with small form
factor and low power consumption. Butt coupling of
waveguides between heterogeneous electro-optic components
is demonstrated as a solution to an otherwise delicate and
costly operation and can find application in a broad array of
integrated optic products.
ACKNOWLEDGEMENT
The information, data, or work presented herein was funded
in part by the Advanced Research Projects Agency-Energy
(ARPA-E), U.S. Department of Energy, under Award
Number DE-AR0000540. The views and opinions of authors
expressed herein do not necessarily state or reflect those of
the United States Government or any agency thereof. The
authors would like to thank the staff at the IBM
Microelectronics Research Laboratory and Central Scientific
Services for their assistance in the fabrication of the Si-Ph
components, as well as Theodore van Kessel, Levente Klein,
Ramachandran Muralidhar, and Hendrik Hamann (all of IBM
Research) for many discussions.
REFERENCES
1. T. Komljenovic et al., “Heterogeneous Silicon Photonic
Integrated Circuits”, J. LightwaveTechn. 2016
2. J.E. Bowers et al., “A Comparison of Four Approaches to
Photonic Integration”, OFC, 2017
3. Bowen Song et al., “3D integrated hybrid silicon laser”, Opt.
Express 2016
4. M.R. Billah et al., “Hybrid integration of silicon photonics
circuits and InP lasers by photonic wire bonding”, Optica 2018
5. A. J. Zilkie et al., “Power Efficient III-V/Silicon external cavity
DBR lasers”, Optics Express Vol.20, 2012
6. S. Tanaka et al., “High-output-power, single-wavelength
silicon hybrid laser using precise flip-chip bonding
technology”, Optics Express Vol.20, 2012
1066
7. S. Tanaka et al., “Four-Wavelength Silicon Hybrid Laser Array
with Ring-Resonator Based Mirror for Efficient CWDM
Transmitter”, OFC/NFOEC Technical Digest 2013
8. J.H. Lee et al., “High power and widely tunable Si hybrid
external-cavity laser for power efficient Si photonics WDM
links”, Optics Express Vol.22, 2014
9. J. Bovington et al., “III–V/Si Vernier-Ring Comb Lasers
(VRCLs)”, IEEE Quant.Elect.(23), 2017
10. B. Song et al., “High-Thermal Performance 3D Hybrid Silicon
Lasers”, IEEE Phot.Techn.Let. Vol.29, 2017
11. E.J. Zhang et al., “Methane absorption spectroscopy with a
hybrid III-V silicon external cavity laser”, CLEO: Science and
Innovations (STh1B.2), San Jose CA, May 5-10, 2018.
12. Chi Xiong et al., “Silicon photonic integrated circuit for on-
chip spectroscopic gas sensing”, Proc. of Photonics West
Conf., 2019
13. W.M. Green et al., “Silicon Photonic Gas Sensing”, OFC 2019
14. W.D.Sacher et al., “Polarization rotator-splitters in standard
active silicon photonics platforms”, Optics Express Vol. 22,
2014
15. T. Barwicz et al., “Demonstration of Self-Aligned Flip-Chip
Photonic Assembly with 1.1dB Loss and >120nm Bandwidth”,
2016 Frontiers in Optics, OSA Technical Digest (online)),
paper FF5F.3.
16. T. Barwicz et al., “Automated, high-throughput photonic
packaging”, Optical Fiber Technology 44, 24-35 (2018).
17. C.Xiong et al, “Correlation between optical return loss and
transmission fringe noise in high-index contrast waveguides”,
CLEO (OSA) 2017, paper SW1N.5.
18. K.P. Jackson et al., “A High-Density, Four-Channel, OEIC
Transceiver Module Utilizing Planar-Processed Optical
Waveguides and Flip-Chip Solder-Bump Technology”, J.
Lightwave Techn. (12), 1994
19. J.-W. Nah, Y. Martin, S. Kamlapurkar, S.Engelmann, R.L.
Bruce, and T.Barwicz, “Flip chip assembly with sub-micron
3D re-alignment via solder surface tension,” in IEEE Proc.
2015 ECTC, pp.35-40.
20. Y. Martin et al., “Toward high-yield 3D self-alignment of flip-
chip assemblies via solder surface tension”, in IEEE Proc. of
2016 ECTC, pp.588-594.
21. Y. Martin et al, “Novel solder pads for self-aligned flip-chip
assembly “, in IEEE Proc. of 2019 ECTC.