SINGAPORE POLYTECHNIC ET1006 SAS Code 2018/2019 SEMESTER ONE MID-SEMESTER TEST. MST Diploma in Aerospace Electronics (DASE) 1® Year FT Diploma in Energy Systems and Management (DESM) 1* Year FT Diploma in Computer Engineering (DCPE) 1** Year FT Diploma in Electrical & Electronic Engineering (DEER) 1* Year FT Common Engineering Programme (DCEP) 1" Year FT Diploma in Engineering with Business (DEB) 2™ Year FT PRINCIPLES OF ELECTRICAL & ELECTRONIC ENGINEERING II Time Allowed: 12 Hours Instructions to Candidates 1, The Singapore Polytechnic Examination Rules are to be complied with, This paper consists of TWO sections: Section A - 10 Multiple Choice Questions, 3 marks each. Section B - 5 Short Questions, 14 marks each. 3, ALL questions are COMPULSORY. 4. All questions are to be answered in the answer booklet. Start each question in Section B ‘ona new page. 5. _ Fill in the Question Numbers, in the order that it was answered in the boxes found on the front cover of the answer booklet under the column “Question Answered”. 6. This paper consists of 7 pages (inclusive of the cover page and the formulae sheet), 2018/2019/S1 MST Page 1 of 8SINGAPORE POLYTECHNIC ET1006 L 2, AL. A2. Ag AS. SECTION A MULTIPLE CHOICE QUESTIONS [3 marks each] Please tick your answers in the MCQ box on the second page of the answer booklet. ‘No marks will be deducted for incorrect answers. ‘The purpose of adding trivalent impurity to silicon is to (a) create minority carriers. (b) _ increase the number of holes. (©) increase the number of free electrons. (d)_ reduce the conductivity of silicon. Recombination is when (a) an electron falls into a hole. (b)acrystal is formed. (©) apositive ion and a negative ion bond together. (@)__avalence electron becomes a conduction electron. A12 mA change in Zener current produces a 0.13 V change in the Zener voltage, The Zener impedance is equal to (a) 0.108 () 1.569 © 1083.2 @ 232 The internal resistance of a photo diode (@) increases with light intensity when forward-biased. (b) decreases with light intensity when forward-biased. (©) increases with light intensity when reverse-biased, @ decreases with light intensity when reverse-biased. ‘The circuit shown in Figure AS uses silicon diodes. The current I is equal to (@) OmA 5kQ. (b) 0.73 mA (© 08mA I () 1.46mA av V Figure AS L_ 2018/2019/S1 MST Page 2 of 8SINGAPORE POLYTECHNIC ET1006 A6. Al. AB. AS. Al0. Which one of the devices in a DC power supply produces a pulsating de output voltage? (@) Filter (b) Rectifier (©) Voltage regulator (@__Step-down transformer When a 50 Hz sinusoidal voltage is applied to the input of a full-wave rectifier, the output frequency is equal to (@ 25 Hz (b) 50 Hz (© 100Hz (@ 150Hz A voltage regulator has a 9 V output when there is no load (load current = 0). When the full-load current of 1.1 A is supplied by the regulator, the output voltage drops to 8.6 V. The load regulation is equal to (a) 1.2% (bo) 4.44% ©) 4.65% @ 40% Which one of the following regions of operation of a bipolar junction transistor is, Tinear? (@) Breakdown (b) Saturation (©) Cutoff @ Active ‘The majority carriers in the P region of an NPN transistor are (@) holes (b) protons (©) electrons @__ neutrons 2018/2019/S1 MST Page 3 of 8SINGAPORE POLYTECHNIC ET1006 ECTION B (14 marks each) BI. (a) Explain how a barrier potential is established across the pn junction. [3 marks] (6) For the cireuit shown in Figure B1 which uses silicon diode, (state with reason whether the diode is reverse-biased or forward-biased. [2 marks] i) calculate the currents flowing through resistors Ri and Ra. Indicate the directions of both currents, [8 marks] (iii) calculate the current flowing through the diode. [I mark] Me x 6x02 7 FigureB1 = B2.(a) For the circuit shown in Figure B2-A, calculate the value of R if Vz = 10 V at 25 mA. [5 marks] R 15 v= Figure B2-A () _Forthe circuit shown in Figure B2-B, calculate the limiting resistor R if the supply current = 60 mA, Assume that the LED used in the circuit has a forward voltage drop of 2.1 V. [9 marks] I Vv R x x x Figure 2B-B 2018/2019/S1 MST Page 4 of &SINGAPORE POLYTECHNIC ET1006 B3. For the circuit shown in Figure B3, @ ® © @ © state the type of rectifier cireuit. (2 marks] calculate the peak voltage of the secondary coil. [2 marks] calculate the peak current flowing through the load resistor, Rr [5 marks] calculate the PIV for each diode. [3 marks] calculate Va when the secondary voltage is at its positive peak. [2 marks] Assume that the diodes used are silicon diodes. B4. (a) (b) 10:1 A Di 200V | Ry De 1.2kQ Figure B3 = For the circuit shown in Figure B4-A, sketch the output voltage waveform across the resistor Ri. Indicate the minimum and maximum values of the waveform, The circuit uses licon diodes. [8 marks] 15kQ Ru Van 2-V OY) 3k Figure B4-A Figure B4-B shows the filtered waveform at the output of a rectifier. (i) What component can be added to the output of the rectifier to produce the filtered waveform? [2 marks] (i) Calculate the ripple voltage Vip ifthe ripple factor is 0.8% and Vas is 38V. [4 marks] 4 Veep) Figure B4-B 2018/2019/S1 MST Page 5 of 8SINGAPORE POLYTECHNIC ET1006 BS. For the circuit shown in Figure BS, the transistor is biased in the active region. Given that the current gain f is 200 calculate (@ the base current, In [3 marks} (b) the collector current, le [2 marks] (©) the voltage across the transistor, Ver [3 marks] (@ the minimum value of Vox to ensure the transistor operates in the saturation region when Vcc is increased to 13 V. (Take Vcrjay=0.2V) [6 marks] - End of Paper— 2018/2019/S1 MST Page 6 of 8SINGAPORE POLYTECHNIC BT1006 Formulae Energy, Work Done, Charge, Power: Ww W=QV P=— I= @ t t ‘The maximum number of electrons in a shell (band) = 2N* 6.25 x 10'S electrons > 1C of negative charge Diodes: Forward voltage drop Ve is 0.7 V for silicon diode and 0.3 V for germanium diode Zener dynamic resistance Zz = AVz, Aly AC Voltages and Currents: Inns = Ip /V 2 = 0.7071 Ip Typ = 2y avg = 2p / = 0.637Iy Vins =Vp/N2= 0.7071 Vp Vpp=2Vp Vave= 2Vp f= 0.637V Half-Wave Rectifier: Fontes = Veco) — 0-7 PIV = Vecccpy Centre-Tapped Full-Wave Rectifier: Vay) = Lt —0.1V V, Foo pyy =2y, 0.7 oma) =~ . avg = = Woncp) + 0. Full-Wave Bridge Rectifier: 2 Vouacny = Veectyy VA V Vay = PIV =Vguyeyy #07 V Ripple Factor: V, V, r(rms) (pp) here Vrcrmsy = 5 Ta Ving “Nee orem) 2/3 AV our Vu -¥; Line Regulation = (t=) 00% — Load Regulation (at 100% Py ‘rs Transistors: Boe Boe an 2018/2019/S1 MST Page 7 of 8SINGAPORE POLYTECHNIC ET1006 ANSWERS [Al Jaz AB Ad AS AG AT Ag AQ Alo | \B A Cc D D iB Cc Cc D A BI(b)(i) Ve=-12 V Diode forward biased. Gi) Ikv=15.71mA — Izy=16.62 mA (iii) 16.62 mA B2(a) 2002 (b) 285 2 B3(a) Full wave bridge rectifier (b) 28.284 V (c) 22.4 Mi mA (©) 27.584.V (d)27.584.V Bd (a) Vout 7.533 V ov (©) Capacitor (fi) 1.053 V BS(a) 0.1SmA (b)30mA ()19V (@)5.914V 2018/2019/S1 MST Page 8 of 8