J.N.T.

U College of Engineering Page No:

Anantapur. Date:

EXPERIMENT NO:12
FINITE STATE MACHINE BASED LOGIC CIRCUIT
VENDING MACHINE

AIM: To design and simulate vending machine by using Verilog

TOOLS USED: Mentorgraphics –Questa sim simulator

Operating system: Centos6

THEORY:
A vending machine is an automated machine that provides items such as
snacks, beverages, cigarettes and lottery tickets to consumers after money, a credit card, or
specially designed card is inserted into the machine. The first modern vending machines were
developed in England in the early 1880s and dispensed postcards. Vending machines exist in
many countries, and in more recent times, specialized vending machines that provide less
common products compared to traditional vending machine items have been created and
provided to consumers.
Mechanisms
Internal communication in vending machines is typically based on the MDB
standard, supported by National Automatic Merchandising Association (NAMA) and
European Vending & Coffee Service Association (EVA).
After payment has been tendered, a product may become available by:

 The machine releasing it, so that it falls in an open compartment at the bottom, or
into a cup, either released first, or put in by the customer, or
Some products need to be prepared to become available. For example, tickets are printed
or magnetized on the spot, and coffee is freshly concocted. One of the most common form of
vending machine, the snack machine, often uses a metal coil which when ordered rotates to
release the product.
The main example of a vending machine giving access to all merchandise after
paying for one item is a newspaper vending machine (also called vending box) found mainly in
the U.S. and Canada. It contains a pile of identical newspapers. After a sale the door
automatically returns to a locked position. A customer could open the box and take all of the
newspapers or, for the benefit of other customers, leave all of the newspapers outside of the
box, slowly return the door to an unlatched position, or block the door from fully closing, each
of which are frequently discouraged, sometimes by a security clamp. The success of such
machines is predicated on the assumption that the customer will be honest (hence the nickname
"honor box"), and need only one copy.
 J.N.T.U College of Engineering Page No:
Anantapur. Date:

LINUX COMMANDS:
Right click on the DESKTOP
Open in terminal

(1) To create folder->mkdir folder name

(2) To enter into folder ->cd folder name

(3) Create a new file

Give file type as FILENAME (filename.v)press enter
Write the source code
(4) For TEST BENCH
Create a new file
Give file type as VERILOGFILENAME (filename_tb.v) press enter
Write the test bench.

(5) Type csh

To enter into MENTORGRAPHICS tool
(6) Type source /home/mentorgraphics/cshrc/ams_2009.cshrc

(7) Type vsim &

MENTORGRAPHICS TOOL IS OPENED NOW

PROCEDURE:
RTL DESIGN AND FUNCTIONAL VERIFICATION:
1) click on the Transcripts

2) Create library file  vlib work press enter

then vmap work workpress enter

3) To compile vlog design unit.v testbench filename.v

4) To simulate  vsim –debugdb –vopt work. Testbench filename

5) For Waveform add wave sim:/testbench/design unit/*

press ctrl+w to add all items into wave
 J.N.T.U College of Engineering Page No:
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(6) Type Run press enter

(7) For Schematic Diagram add schematic sim:/testbench/design unit

SCHEMATIC DIAGRAM
 J.N.T.U College of Engineering Page No:
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SOURCE CODE:
module vendingmachine(clk,rst,i,j,k,p,c1,c2);
input clk,rst;
input [2:0] i,j,k;
output reg p;
output [3:0]c1,c2;
reg [3:0] c1,c2;
reg [3:0]state,n_state;
parameter a=1,b=2,c=5;
parameter
s0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0011,s4=4'b0100,s5=4'b0101,s6=4'b0110,s7=4'b0111,
s8=4'b1000,s9=4'b1001;
always @(posedge clk or posedge rst)
begin
if(rst==1)
state<=s0;
else
state<=n_state;
end
always @(state,i,j,k)
begin
case(state)
s0:if(i==0&&j==0&&k==0)
begin
n_state<=s0;
p=0;c1=0;c2=0;
end
else if(i==0&&j==0&&k==a)
begin
n_state<=s1;
p=0;c1=0;c2=0;
end
else if(i==0&&j==b&&k==0)
begin
n_state<=s2;
p=0;c1=0;c2=0;
end
else if(i==c&&j==0&&k==0)
begin
n_state<=s5;
p=0;c1=0;c2=0;
end
s1:if(i==0&&j==0&&k==0)
 J.N.T.U College of Engineering Page No:
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begin
n_state<=s1;
p=0;c1=0;c2=0;
end
else if(i==0&&j==0&&k==a)
begin
n_state<=s2;
p=0;c1=0;c2=0;
end
else if(i==0&&j==b&&k==0)
begin
n_state<=s3;
p=0;c1=0;c2=0;
end
else if(i==c&&j==0&&k==0)
begin
n_state<=s6;
p=0;c1=0;c2=0;
end
s2:if(i==0&&j==0&&k==0)
begin
n_state<=s2;
p=0;c1=0;c2=0;
end
else if(i==0&&j==0&&k==a)
begin
n_state<=s3;
p=0;c1=0;c2=0;
end
else if(i==0&&j==b&&k==0)
begin
n_state<=s4;
p=0;c1=0;c2=0;
end
else if(i==c&&j==0&&k==0)
begin
n_state<=s7;
p=0;c1=0;c2=0;
end
s3:if(i==0&&j==0&&k==0)
begin
n_state<=s3;
p=0;c1=0;c2=0;
end
 J.N.T.U College of Engineering Page No:
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else if(i==0&&j==0&&k==a)
begin
n_state<=s4;
p=0;c1=0;c2=0;
end
else if(i==0&&j==b&&k==0)
begin
n_state<=s5;
p=0;c1=0;c2=0;
end
else if(i==c&&j==0&&k==0)
begin
n_state<=s0;
p=1;c1=0;c2=0;
end
s4:if(i==0&&j==0&&k==0)
begin
n_state<=s4;
p=0;c1=0;c2=0;
end
else if(i==0&&j==0&&k==a)
begin
n_state<=s5;
p=0;c1=0;c2=0;
end
else if(i==0&&j==b&&k==0)
begin
n_state<=s6;
p=0;c1=0;c2=0;
end
else if(i==c&&j==0&&k==0)
begin
n_state<=s8;
p=1;c1=0;c2=0;
end
s5:if(i==0&&j==0&&k==0)
begin
n_state<=s5;
p=0;c1=0;c2=0;
end
else if(i==0&&j==0&&k==a)
begin
n_state<=s6;
p=0;c1=0;c2=0;
end
else if(i==0&&j==b&&k==0)
 J.N.T.U College of Engineering Page No:
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begin
n_state<=s7;
p=0;c1=0;c2=0;
end
else if(i==c&&j==0&&k==0)
begin
n_state<=s9;
p=1;c1=0;c2=0;
end
s6:if(i==0&&j==0&&k==0)
begin
n_state<=s6;
p=0;c1=0;c2=0;
end
else if(i==0&&j==0&&k==a)
begin
n_state<=s7;
p=0;c1=0;c2=0;
end
else if(i==0&&j==b&&k==0)
begin
n_state<=s0;
p=1;c1=0;c2=0;
end
else if(i==c&&j==0&&k==0)
begin
n_state<=s9;
p=1;c1=1;c2=0;
end
s7:if(i==0&&j==0&&k==0)
begin
n_state<=s7;
p=0;c1=0;c2=0;
end
else if(i==0&&j==0&&k==a)
begin
n_state<=s0;
p=1;c1=0;c2=0;end

else if(i==0&&j==b&&k==0)
 J.N.T.U College of Engineering Page No:
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begin
n_state<=s8;
p=1;c1=0;c2=0;
end
else if(i==c&&j==0&&k==0)
begin
n_state<=s8;
p=1;c1=1;c2=1;
end
s8:if(i==0&&j==0&&k==0)
begin
n_state<=s0;
p=0;c1=1;c2=0;
end
else if(i==0&&j==0&&k==a)
begin
n_state<=s2;
p=0;c1=0;c2=0;
end
else if(i==0&&j==b&&k==0)
begin
n_state<=s3;
p=0;c1=0;c2=0;
end
else if(i==c&&j==0&&k==0)
begin
n_state<=s6;
p=0;c1=0;c2=0;
end
s9:if(i==0&&j==0&&k==0)
begin
n_state<=s0;
p=0;c1=0;c2=1;
end
else if(i==0&&j==0&&k==a)
begin
n_state<=s3;
p=0;c1=0;c2=0;
end
else if(i==0&&j==b&&k==0)
begin
n_state<=s4;
p=0;c1=0;c2=0;
end
else if(i==c&&j==0&&k==0)
 J.N.T.U College of Engineering Page No:
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begin
n_state<=s7;
p=0;c1=0;c2=0;

end
default :n_state<=s0;
endcase

end
endmodule
WAVEFORM:
 J.N.T.U College of Engineering Page No:
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TEST BENCH:
module vendingmachine_tb;
wire p,c1,c2;
reg clk,rst;
reg [2:0] i,j,k;
vendingmachine dut(clk,rst,i,j,k,p,c1,c2);
initial
begin
rst=1;
clk=0;
forever #5 clk=!clk;
end
initial
begin
i=3'b000;j=3'b000;k=3'b000;
#10 rst=0;

#10 i=3'b101;j=3'b000;k=3'b000;
#10 i=3'b101;
#10 i=3'b000;j=3'b000;k=3'b000;
//#10 i=3'b000;j=3'b010;k=3'b000;
//#10 i=3'b000;j=3'b000;k=3'b001;

#50 $stop;
end
initial
begin
$monitor($time,"clk=%b,p=%b,c1=%b,c2=%b,i=%b,j=%b,k=%b",clk,p,c1,c2,i,j,k);
end
endmodule

RESULT:
Thus the vending machine was designed and simulated by using mentor graphics