Clock Generator PLL with Integrated VCO

ADF4360-9
FEATURES GENERAL DESCRIPTION
Primary output frequency range: 65 MHz to 400 MHz The ADF4360-9 is an integrated integer-N synthesizer and
Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz voltage-controlled oscillator (VCO). External inductors set the
3.0 V to 3.6 V power supply ADF4360-9 center frequency. This allows a VCO frequency
1.8 V logic compatibility range of between 65 MHz and 400 MHz.
Integer-N synthesizer
An additional divider stage allows division of the VCO signal.
Programmable output power level
The CMOS level output is equivalent to the VCO signal divided
3-wire serial interface
by the integer value between 2 and 31. This divided signal can
Digital lock detect
be further divided by 2, if desired.
Software power-down mode
Control of all the on-chip registers is through a simple 3-wire
APPLICATIONS interface. The device operates with a power supply ranging
System clock generation from 3.0 V to 3.6 V and can be powered down when not in use.
Test equipment
Wireless LANs
CATV equipment

FUNCTIONAL BLOCK DIAGRAM

AVDD DVDD RSET

ADF4360-9
LD
REFIN 14-BIT R
COUNTER
LOCK
MUTE
DETECT

CLK 24-BIT
24-BIT DATA CHARGE
DATA FUNCTION CP
REGISTER PUMP
LATCH
LE PHASE
VVCO
COMPARATOR
VTUNE

L1
L2
CC
CN

13-BIT B VCO OUTPUT RFOUTA

COUNTER CORE STAGE
RFOUTB
N=B

DIVIDE-BY-A
(2 TO 31)

DIVIDE-BY-2
MULTIPLEXER DIVOUT
07139-001

AGND DGND CPGND

Figure 1.

Rev. A
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ADF4360-9
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 10
Reference Input Section............................................................. 10
N Counter.................................................................................... 10
R Counter .................................................................................... 10
PFD and Charge Pump.............................................................. 10
Lock Detect ................................................................................. 10
REVISION HISTORY
3/08—Rev. 0 to Rev. A
Changes to Table 1 ........................................................................... 3
Changes to Figure 23...................................................................... 14
Changes to Output Matching Section.......................................... 23
1/08—Revision 0: Initial Version
Rev. A | Page 2 of 24
Input Shift Register .................................................................... 10
VCO ............................................................................................. 11
Output Stage................................................................................ 12
DIVOUT Stage............................................................................ 12
Latch Structure ........................................................................... 13
Power-Up..................................................................................... 17
Control Latch .............................................................................. 18
N Counter Latch......................................................................... 19
R Counter Latch ......................................................................... 19
Applications..................................................................................... 20
Choosing the Correct Inductance Value................................. 20
Encode Clock for ADC.............................................................. 20
GSM Test Clock .......................................................................... 21
Interfacing ................................................................................... 22
PCB Design Guidelines for Chip Scale Package .................... 22
Output Matching ........................................................................ 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
 ADF4360-9

SPECIFICATIONS
AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. 1

Table 1.
Parameter B Version Unit Conditions/Comments
REFIN CHARACTERISTICS
REFIN Input Frequency 10/250 MHz min/MHz max For f < 10 MHz, use a dc-coupled, CMOS-compatible
square wave, slew rate > 21 V/μs
REFIN Input Sensitivity 0.7/AVDD V p-p min/V p-p max AC-coupled
0 to AVDD V max CMOS-compatible
REFIN Input Capacitance 5.0 pF max
REFIN Input Current ±60 μA max
PHASE DETECTOR
Phase Detector Frequency 2 8 MHz max
CHARGE PUMP
ICP Sink/Source 3 With RSET = 4.7 kΩ
High Value 2.5 mA typ
Low Value 0.312 mA typ
RSET Range 2.7/10 kΩ min/kΩ max
ICP Three-State Leakage Current 0.2 nA typ
Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V
ICP vs. VCP 1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V
ICP vs. Temperature 2 % typ VCP = 2.0 V
LOGIC INPUTS
Input High Voltage, VINH 1.5 V min
Input Low Voltage, VINL 0.6 V max
Input Current, IINH/IINL ±1 μA max
Input Capacitance, CIN 3.0 pF max
LOGIC OUTPUTS
Output High Voltage, VOH DVDD − 0.4 V min CMOS output chosen
Output High Current, IOH 500 μA max
Output Low Voltage, VOL 0.4 V max IOL = 500 μA
POWER SUPPLIES
AVDD 3.0/3.6 V min/V max
DVDD AVDD
VVCO AVDD
AIDD 4 5 mA typ
DIDD4 2.5 mA typ
IVCO4, 5 12.0 mA typ ICORE = 5 mA
IRFOUT4 3.5 to 11.0 mA typ RF output stage is programmable
Low Power Sleep Mode4 7 μA typ
RF OUTPUT CHARACTERISTICS5
Maximum VCO Output Frequency 400 MHz ICORE = 5 mA; depending on L1 and L2; see the
Choosing the Correct Inductance Value section
Minimum VCO Output Frequency 65 MHz
VCO Output Frequency 90/108 MHz min/MHz max L1, L2 = 270 nH; see the Choosing the Correct
Inductance Value section for other frequency values
VCO Frequency Range 1.2 Ratio fMAX/fMIN
VCO Sensitivity 2 MHz/V typ L1, L2 = 270 nH; see the Choosing the Correct
Inductance Value section for other sensitivity values
Lock Time 6 400 μs typ To within 10 Hz of final frequency

Rev. A | Page 3 of 24
ADF4360-9
Parameter B Version Unit Conditions/Comments
Frequency Pushing (Open Loop) 0.24 MHz/V typ
Frequency Pulling (Open Loop) 10 Hz typ Into 2.00 VSWR load
Harmonic Content (Second) −16 dBc typ
Harmonic Content (Third) −21 dBc typ
Output Power5, 7 −9/0 dBm typ Using tuned load, programmable in 3 dB steps;
see Figure 35
Output Power5, 8 −14/−9 dBm typ Using 50 Ω resistors to VVCO, programmable in
3 dB steps; see Figure 33
Output Power Variation ±3 dB typ
VCO Tuning Range 1.25/2.5 V min/V max
VCO NOISE CHARACTERISTICS
VCO Phase Noise Performance 9,10 −91 dBc/Hz typ @ 10 kHz offset from carrier
−117 dBc/Hz typ @ 100 kHz offset from carrier
−139 dBc/Hz typ @ 1 MHz offset from carrier
−140 dBc/Hz typ @ 3 MHz offset from carrier
−147 dBc/Hz typ @ 10 MHz offset from carrier

Normalized In-Band Phase Noise 10, 11 −218 dBc/Hz typ

In-Band Phase Noise10, 11 −110 dBc/Hz typ @ 1 kHz offset from carrier
RMS Integrated Jitter 12 1.4 ps typ Measured at RFOUTA
Spurious Signals Due to PFD Frequency 13 −75 dBc typ
DIVOUT CHARACTERISTICS12
Integrated Jitter Performance VCO frequency = 320 MHz to 380 MHz
(Integrated from 100 Hz to 1 GHz)
DIVOUT = 180 MHz 1.4 ps rms A = 2, A output selected
DIVOUT = 95 MHz 1.4 ps rms A = 2, A/2 output selected
DIVOUT = 80 MHz 1.4 ps rms A = 2, A/2 output selected
DIVOUT = 52 MHz 1.4 ps rms A = 3, A/2 output selected (VCO = 312 MHz,
PFD = 1.6 MHz)
DIVOUT = 45 MHz 1.4 ps rms A = 4, A/2 output selected
DIVOUT = 10 MHz 1.6 ps rms A = 18, A/2 output selected (VCO = 360 MHz,
PFD = 1.6 MHz)
DIVOUT Duty Cycle
A Output 1/A × 100 % typ Divide-by-A selected
A/2 Output 50 % typ Divide-by-A/2 selected
1
Operating temperature range is −40°C to +85°C.
2
Guaranteed by design. Sample tested to ensure compliance.
3
ICP is internally modified to maintain constant loop gain over the frequency range.
4
TA = 25°C; AVDD = DVDD = VVCO = 3.3 V.
5
Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.
6
Jumping from 90 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7
For more detail on using tuned loads, see the Output Matching section.
8
Using 50 Ω resistors to VVCO into a 50 Ω load.
9
The noise of the VCO is measured in open-loop conditions. L1, L2 = 56 nH.
10
The phase noise is measured with the EVAL-ADF4360-9EBZ1 evaluation board and the Agilent E5052A signal source analyzer.
11
fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop B/W = 40 kHz. The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the
VCO and subtracting 20logN (where N is the N divider value) and 10logfPFD. PNSYNTH = PNTOT − 10logfPFD − 20logN.
12
The jitter is measured with the EVAL-ADF4360-9EBZ1 evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REFIN for the
synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop BW = 40 kHz, unless otherwise
noted.
13
The spurious signals are measured with the EVAL-ADF4360-9EBZ1 evaluation board and the Agilent E5052A signal source analyzer. The spectrum analyzer provides
the REFIN for the synthesizer; fREFIN = 10 MHz @ 0 dBm. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop BW = 40 kHz.

Rev. A | Page 4 of 24
 ADF4360-9
TIMING CHARACTERISTICS 1
AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.

Table 2.
Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments
t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
1
Refer to the Power-Up section for the recommended power-up procedure for this device.

t4 t5

CLK

t2 t3

DB1 DB0 (LSB)

DATA DB23 (MSB) DB22 DB2
(CONTROL BIT C2) (CONTROL BIT C1)

t7

LE

t1 t6

07139-002
LE

Figure 2. Timing Diagram

Rev. A | Page 5 of 24
ADF4360-9

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
Table 3. may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
Parameter Rating
other conditions above those indicated in the operational
AVDD to GND 1 −0.3 V to +3.9 V
section of this specification is not implied. Exposure to absolute
AVDD to DVDD −0.3 V to +0.3 V
maximum rating conditions for extended periods may affect
VVCO to GND −0.3 V to +3.9 V
device reliability.
VVCO to AVDD −0.3 V to +0.3 V
Digital Input/Output Voltage to GND −0.3 V to VDD + 0.3 V This device is a high performance RF integrated circuit with an
Analog Input/Output Voltage to GND −0.3 V to VDD + 0.3 V ESD rating of <1 kV, and it is ESD sensitive. Proper precautions
REFIN to GND −0.3 V to VDD + 0.3 V should be taken for handling and assembly.
Operating Temperature Range −40°C to + 85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TRANSISTOR COUNT
LFCSP θJA Thermal Impedance The transistor count is 12,543 (CMOS) and 700 (bipolar).
Paddle Soldered 50°C/W
Paddle Not Soldered 88°C/W
Lead Temperature, Soldering
ESD CAUTION
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
GND = CPGND = AGND = DGND = 0 V.

Rev. A | Page 6 of 24
 ADF4360-9

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DIVOUT
AGND
DVDD
CP
LD

LE
20
19
21
24
23
22
PIN 1
CPGND 1 INDICATOR 18 DATA
AVDD 2 17 CLK
AGND 3 ADF4360-9 16 REFIN
RFOUTA 4 TOP VIEW 15 DGND
RFOUTB 5 (Not to Scale) 14 CN
VVCO 6 13 RSET

11
9
10

12
7
8

07139-003
L2
L1

CC
AGND

AGND
VTUNE
Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2 AVDD Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must have the same value as DVDD.
3, 8, 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO.
4 RFOUTA VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a
description of the various output stages.
5 RFOUTB VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output
Matching section for a description of the various output stages.
6 VVCO Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. VVCO must have the same value as AVDD.
7 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
output voltage.
9 L1 An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
10 L2 An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
12 CC Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the
synthesizer. The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is
ICPmax = 11.75/RSET
For example, RSET = 4.7 kΩ and ICPmax = 2.5 mA.
14 CN Internal Compensation Node. This pin must be decoupled to VVCO with a 10 μF capacitor.
15 DGND Digital Ground.
16 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
17 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
20 DIVOUT This output allows the user to select VCO frequency divided by A or VCO frequency divided by 2A.
Alternatively, the scaled RF, or the scaled reference frequency, can be accessed externally through this output.
21 DVDD Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DVDD must have the same value as AVDD.
23 LD Lock Detect. The output on this pin is logic high to indicate that the part is in lock. Logic low indicates loss of lock.
24 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the
internal VCO.

Rev. A | Page 7 of 24
ADF4360-9

TYPICAL PERFORMANCE CHARACTERISTICS

–20 –60

–70
–40
–80

–60
PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

–90

–100
–80
–110
–100
–120

–120 –130

–140
–140

07139-004

07139-007
–150

–160 –160
1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 4. Open-Loop VCO Phase Noise at 218 MHz, L1, L2 = 56 nH Figure 7. DIVOUT Phase Noise, 95 MHz, VCO = 380 MHz,
PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,
Divide-by-A/2 Selected, A = 2

–60 –60

–70 –70

–80 –80
PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

–90 –90

–100 –100

–110 –110

–120 –120

–130 –130

–140 –140
07139-005

07139-008
–150 –150

–160 –160
100 1k 10k 100k 1k 10M 100 1k 10k 100k 1M 10M
FREQUENCY OFFSET (Hz) FREQUENCY OFFSET (Hz)

Figure 5. VCO Phase Noise, 360 MHz, 1 MHz PFD, 40 kHz Loop Bandwidth, Figure 8. DIVOUT Phase Noise, 80 MHz, VCO = 320 MHz,
RMS Jitter = 1.4 ps PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,
Divide-by-A/2 Selected, A = 2

–60 –60

–70 –70

–80 –80
PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

–90 –90

–100 –100

–110 –110

–120 –120

–130 –130

–140 –140
07139-006

07139-009

–150 –150

–160 –160
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M
FREQUENCY OFFSET (Hz) FREQUENCY OFFSET (Hz)

Figure 6. DIVOUT Phase Noise, 180 MHz, VCO = 360 MHz, Figure 9. DIVOUT Phase Noise, 52 MHz, VCO = 312 MHz,
PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps, PFD Frequency = 1.6 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.4 ps,
Divide-by-A Selected, A = 2 Divide-by-A/2 Selected, A = 3

Rev. A | Page 8 of 24
 ADF4360-9
–60

–70

–80
PHASE NOISE (dBc/Hz)

–90

–100
1
–110

–120

–130 C1 FREQUENCY: 90MHz

C1 + DUTY: 28.98%
–140 C1 PEAK TO PEAK: 1.55V

07139-013
07139-010
–150

–160
100 1k 10k 100k 1M 10M CH1 500mV M 2.00ns A CH1 20mV
FREQUENCY OFFSET (Hz)

Figure 10. DIVOUT Phase Noise, 45 MHz, VCO = 360 MHz, Figure 13. DIVOUT 90 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected,
PFD Frequency = 1.6 MHz, Loop Bandwidth = 60 kHz, Jitter = 1.4 ps, A = 4, Duty Cycle = ~25%
Divide-by-A/2 Selected, A = 2

–100

+25°C
–110 –40°C
+85°C
PHASE NOISE (dBc/Hz)

–120

1
–130

–140
C1 FREQUENCY: 36.01MHz
C1 + DUTY: 13.13%
C1 PEAK TO PEAK 1.28V
–150

07139-014
07139-011

–160
1k 10k 100k 1M 10M CH1 500mV M 5.00ns A CH1 920mV
FREQUENCY OFFSET (Hz)

Figure 11. DIVOUT Phase Noise over Temperature, 52 MHz, VCO = 312 MHz, Figure 14. DIVOUT 36 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected,
PFD Frequency = 1 MHz, Loop Bandwidth = 60 kHz, A = 10, Duty Cycle = ~10%
Divide-by-A/2 Selected, A = 3

C1 FREQUENCY: 180MHz
C1 + DUTY: 45.32%

1 1
07139-012

07139-015

C1 FREQUENCY: 36MHz
C1 + DUTY: 49.41%

CH1 500mV M 2.00ns A CH1 20mV CH1 500mV M 12.5ns A CH1 920mV

Figure 12. DIVOUT 180 MHz Waveform, VCO = 360 MHz, Figure 15. DIVOUT 36 MHz Waveform, VCO = 360 MHz,
Divide-by-A Selected, A = 2, Duty Cycle = ~50% Divide-by-A/2 Selected, A = 5, Duty Cycle = ~50%

Rev. A | Page 9 of 24
ADF4360-9

CIRCUIT DESCRIPTION
VP
REFERENCE INPUT SECTION CHARGE
PUMP
The reference input stage is shown in Figure 16. SW1 and SW2 UP
HI D1 Q1
are normally closed switches, and SW3 is normally open. When
U1
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin at R DIVIDER
CLR1
power-down.
POWER-DOWN
CONTROL
PROGRAMMABLE U3 CP
DELAY
NC 100kΩ

SW2 ABP1 ABP2

REFIN NC TO R COUNTER
BUFFER
SW1 CLR2
DOWN
07139-016
SW3 HI D2 Q2
NO
U2
Figure 16. Reference Input Stage
N DIVIDER
CPGND
N COUNTER
The CMOS N counter allows a wide division ratio in the PLL
feedback counter. The counters are specified to work when the R DIVIDER

VCO output is 400 MHz or less. To avoid confusion, this is

N DIVIDER
referred to as the B counter. It makes it possible to generate
output frequencies that are spaced only by the reference

frequency divided by R. The VCO frequency equation is
fVCO = B × fREFIN/R
where:
fVCO is the output frequency of the VCO.
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
fREFIN is the external reference frequency oscillator.
R COUNTER
The 14-bit R counter allows the input reference frequency
to be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N = B)
and produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function and
minimizes phase noise and reference spurs. Two bits in the R
counter latch, ABP2 and ABP1, control the width of the pulse
(see Figure 25).
07139-017
CP OUTPUT
Figure 17. PFD Simplified Schematic and Timing (In Lock)
LOCK DETECT
The LD pin outputs a lock detect signal. Digital lock detect is
active high. When lock detect precision (LDP) in the R counter
latch is set to 0, digital lock detect is set high when the phase error
on three consecutive phase detector cycles is <15 ns.
When LDP is set to 1, five consecutive cycles of <15 ns phase
error are required to set the lock detect. It stays set high until a
phase error of >25 ns is detected on any subsequent PD cycle.
INPUT SHIFT REGISTER
The digital section of the ADF4360 family includes a 24-bit
input shift register, a 14-bit R counter, and an 18-bit N counter,
comprising a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,
are shown in Figure 2.

Rev. A | Page 10 of 24
 ADF4360-9
3.5
The truth table for these bits is shown in Table 5. Figure 22
shows a summary of how the latches are programmed. Note 3.0
that the test modes latch is used for factory testing and should
not be programmed by the user. 2.5

Table 5. C2 and C1 Truth Table

VTUNE (V)
2.0
Control Bits
C2 C1 Data Latch 1.5

0 0 Control
1.0
0 1 R Counter
1 0 N Counter (B) 0.5

07139-019
1 1 Test Modes
0
80 85 90 95 100 105 110 115
VCO FREQUENCY (MHz)

Figure 18. VTUNE, ADF4360-9, L1 and L2 = 270 nH vs. Frequency

The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 18, to allow a wide frequency range
to be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated.
It is important that the correct write sequence be followed at
power-up. The correct write sequence is as follows:
1. R Counter Latch
2. Control Latch
3. N Counter Latch
During band selection, which takes five PFD cycles, the VCO
VTUNE is disconnected from the output of the loop filter and
connected to an internal reference voltage.
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8
and is controlled by the BSC1 bit and the BSC2 bit in the R counter
latch. Where the required PFD frequency exceeds 1 MHz, the
divide ratio should be set to allow enough time for correct band
selection. For many applications, it is usually best to set this to 8.
After band selection, normal PLL action resumes. The value of
KV is determined by the value of the inductors used (see the
Choosing the Correct Inductance Value section). The ADF4360
family contains linearization circuitry to minimize any variation
of the product of ICP and KV.
The operating current in the VCO core is programmable in four
steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by
the PC1 bit and the PC2 bit in the control latch.
It is strongly recommended that only the 5 mA setting be used.
However, in applications requiring a low VCO frequency, the
high temperature coefficient of some inductors may lead to the
VCO tuning voltage varying as temperature changes. The 7.5 mA
VCO core power setting shows less tuning voltage variation over
temperature in these applications and can be used, provided that
240 Ω resistors are used in parallel with Pin 9 and Pin 10, instead of
the default 470 Ω.

Rev. A | Page 11 of 24
ADF4360-9
DVDD
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360 family are
connected to the collectors of an NPN differential pair driven A COUNTER/2 OUTPUT
by buffered outputs of the VCO, as shown in Figure 19. To A COUNTER OUTPUT
MUX CONTROL DIVOUT
allow the user to optimize the power dissipation vs. the output R COUNTER OUTPUT
power requirements, the tail current of the differential pair is N COUNTER OUTPUT

programmable via Bit PL1 and Bit PL2 in the control latch.
Four current levels can be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.

These levels give output power levels of −9 dBm, −6 dBm,
−3 dBm, and 0 dBm, respectively, using the correct shunt inductor
to VDD and ac coupling into a 50 Ω load. Alternatively, both
outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section).
Another feature of the ADF4360 family is that the supply
current to the RF output stage is shut down until the part
achieves lock, as measured by the digital lock detect circuitry.
This is enabled by the mute-till-lock detect (MTLD) bit in the
control latch.
RFOUTA RFOUTB
VCO BUFFER
07139-020
07139-018
DGND
Figure 20. DIVOUT Circuit
The primary use of this pin is to derive the lower frequencies
from the VCO by programming various divider values to the
auxiliary A divider. Values ranging from 2 to 31 are possible.
The duty cycle of this output is 1/A times 100%, with the logic
high pulse width equal to the inverse of the VCO frequency.
That is,
Pulse Width [seconds] = 1/fVCO (Frequency [Hz])
See Figure 21 for a graphical description. By selecting the
divide-by-2 function, this divided down frequency can in turn
be divided by 2 again. This provides a 50% duty cycle in contrast to
the A counter output, which may be more suitable for some
applications (see Figure 21).
fVCO

Figure 19. RF Output Stage fVCO/A (A = 4)

DIVOUT STAGE
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of DIVOUT fVCO/2A (A = 4)

07139-021
is controlled by D3, D2, and D1 in the control latch. The full
truth table is shown in Figure 23. Figure 20 shows the DIVOUT Figure 21. DIVOUT Waveforms
section in block diagram form.

Rev. A | Page 12 of 24
 ADF4360-9
LATCH STRUCTURE
Figure 22 shows the three on-chip latches for the ADF4360-9. The two LSBs decide which latch is programmed.
CONTROL LATCH

MUTE-TILL-
RESERVED

RESERVED

DETECTOR
POLARITY

COUNTER
CP GAIN
POWER-

POWER-

THREE-
DOWN 2

DOWN 1 OUTPUT CORE

PHASE

RESET
STATE
CURRENT CURRENT DIVOUT CONTROL

LD
POWER POWER

CP
SETTING 2 SETTING 1 CONTROL BITS
LEVEL LEVEL

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RSV RSV PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP PDP D3 D2 D1 CR PC2 PC1 C2 (0) C1 (0)

N COUNTER LATCH
RESERVED

RESERVED

RESERVED
CP GAIN

CONTROL
13-BIT B COUNTER 5-BIT DIVOUT BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RSV RSV CPG B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 RSV A5 A4 A3 A2 A1 C2 (1) C1 (0)

R COUNTER LATCH
TEST MODE

PRECISION
RESERVED

RESERVED

DETECT

BAND ANTI-
LOCK

CONTROL
BIT

SELECT BACKLASH 14-BIT REFERENCE COUNTER BITS

CLOCK PULSE WIDTH

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

07139-034
RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (1)

Figure 22. Latch Structure

Rev. A | Page 13 of 24
ADF4360-9

MUTE-TILL-
RESERVED

RESERVED

DETECTOR
POLARITY

COUNTER
CP GAIN
POWER-

POWER-

THREE-
DOWN 2

DOWN 1
OUTPUT CORE

PHASE
STATE

RESET
CURRENT CURRENT DIVOUT CONTROL
POWER POWER

LD

CP
SETTING 2 SETTING 1 CONTROL BITS
LEVEL LEVEL

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RSV RSV PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP PDP D3 D2 D1 CR PC2 PC1 C2 (0) C1 (0)

PC2 PC1 CORE POWER LEVEL

0 0 2.5mA
0 1 5mA (RECOMMENDED)
1 0 7.5mA
1 1 10mA

CPI6 CPI5 CPI4 ICP (mA) PHASE DETECTOR

CPI3 CPI2 CPI1 4.7kΩ PDP POLARITY
0 NEGATIVE COUNTER
0 0 0 0.31 CR OPERATION
0 0 1 0.62 1 POSITIVE
0 NORMAL
0 1 0 0.93 1 R, A, B COUNTERS
0 1 1 1.25 CHARGE PUMP HELD IN RESET
1 0 0 1.56 CP OUTPUT
1 0 1 1.87 0 NORMAL
1 1 0 2.18 1 THREE-STATE
1 1 1 2.50
CPG CP GAIN
0 CURRENT SETTING 1
1 CURRENT SETTING 2

MTLD MUTE-TIL-LOCK DETECT

0 DISABLED
1 ENABLED

PL2 PL1 OUTPUT POWER LEVEL D3 D2 D1 MUXOUT

CURRENT USING TUNED LOAD USING 50Ω TO VVCO 0 0 0 DVDD
0 0 3.5mA –9dBm –19dBm 0 0 1 DIGITAL LOCK DETECT
0 1 5.0mA –6dBm –15dBm (ACTIVE HIGH)
1 0 7.5mA –3dBm –12dBm 0 1 0 N DIVIDER OUTPUT
1 1 11.0mA 0dBm –9dBm 0 1 1 DVDD
1 0 0 R DIVIDER OUTPUT
1 0 1 A CNTR/2 OUT
1 1 0 A CNTR OUT
1 1 1 DGND

CE PIN PD2 PD1 MODE

0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRONOUS POWER-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN

THESE BITS ARE

NOT USED BY THE

07139-022
DEVICE AND ARE
DON'T CARE BITS.

Figure 23. Control Latch

Rev. A | Page 14 of 24
 ADF4360-9

RESERVED
CP GAIN
CONTROL
RESERVED 13-BIT B COUNTER 5-BIT DIVOUT BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RSV RSV CPG B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 RSV A5 A4 A3 A2 A1 C2 (1) C1 (0)

THIS BIT IS NOT

USED BY THE
DEVICE AND IS A
DON'T CARE BIT.

A5 A4 A2 A1 OUTPUT DIVIDE RATIO

0 0 ............ 0 0 NOT ALLOWED
0 0 ............ 0 1 NOT ALLOWED
0 0 ............ 1 0 2
0 0 ............ 1 1 3
. . ............ . . .
. . ............ . . .
. . ............ . . .
1 1 ............ 0 0 28
1 1 ............ 0 1 29
1 1 ............ 1 0 30
1 1 ............ 1 1 31

B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO

0 0 0 ............ 0 0 0 NOT ALLOWED
0 0 0 ............ 0 0 1 NOT ALLOWED
0 0 0 ............ 0 1 0 NOT ALLOWED
0 0 0 ............ 1 1 1 3
. . . ............ . . . .
. . . ............ . . . .
. . . ............ . . . .
1 1 1 ............ 1 0 0 8188
1 1 1 ............ 1 0 1 8189
1 1 1 ............ 1 1 0 8190
1 1 1 ............ 1 1 1 8191

CP GAIN OPERATION

0 CHARGE PUMP CURRENT SETTING 1

IS PERMANENTLY USED
1 CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED

THESE BITS ARE

NOT USED BY THE

07139-023
DEVICE AND ARE
DON'T CARE BITS.

Figure 24. N Counter Latch

Rev. A | Page 15 of 24
ADF4360-9
RESERVED

RESERVED

PRECISION
ANTI-

DETECT
BAND

MODE

LOCK
BACKLASH

TEST
CONTROL

BIT
SELECT PULSE 14-BIT REFERENCE COUNTER
CLOCK BITS
WIDTH

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (1)

R14 R13 R12 R3 R2 R1 DIVIDE RATIO

0 0 0 .......... 0 0 1 1
0 0 0 .......... 0 1 0 2
0 0 0 .......... 0 1 1 3
TEST MODE 0 0 0 .......... 1 0 0 4
BIT SHOULD . . . .......... . . . .
BE SET TO 0 . . . .......... . . . .
THESE BITS ARE FOR NORMAL . . . .......... . . . .
NOT USED BY OPERATION.
1 1 1 .......... 1 0 0 16380
THE DEVICE 1 1 1 .......... 1 0 1 16381
AND ARE DON'T
1 1 1 .......... 1 1 0 16382
CARE BITS.
1 1 1 .......... 1 1 1 16383

ABP2 ABP1 ANTIBACKLASH PULSE WIDTH

0 0 3.0ns
0 1 1.3ns
1 0 6.0ns
1 1 3.0ns

LDP LOCK DETECT PRECISION

0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

BSC2 BSC1 BAND SELECT CLOCK DIVIDER

0 0 1
0 1 2

07139-024
1 0 4
1 1 8

Figure 25. R Counter Latch

Rev. A | Page 16 of 24
 ADF4360-9
POWER-UP During initial power-up, a write to the control latch powers up
Power-Up Sequence the part, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steady-
The correct programming sequence for the ADF4360-9 after
state value, and if the N counter latch is then programmed, the
power-up is as follows:
VCO may not oscillate at the desired frequency, which does not
1. R Counter Latch allow the band select logic to choose the correct frequency
2. Control Latch band, and the ADF4360-9 may not achieve lock. If the
recommended interval is inserted, and the N counter latch is
3. N Counter Latch
programmed, the band select logic can choose the correct
Initial Power-Up frequency band, and the part locks to the correct frequency.
Initial power-up refers to programming the part after the The duration of this interval is affected by the value of the
application of voltage to the AVDD, DVDD, and VVCO pins. On capacitor on the CN pin (Pin 14). This capacitor is used to
initial power-up, an interval is required between programming reduce the close-in noise of the ADF4360-9 VCO. The
the control latch and programming the N counter latch. This recommended value of this capacitor is 10 μF. Using this
interval is necessary to allow the transient behavior of the value requires an interval of ≥15 ms between the latching in
ADF4360-9 during initial power-up to settle. of the control latch bits and latching in of the N counter latch
bits. If a shorter delay is required, the capacitor can be reduced.
A slight phase noise penalty is incurred by this change, which is
further explained in Table 6.

Table 6. CN Capacitance vs. Interval and Phase Noise

Recommended Interval Between Open-Loop Phase Noise @ 10 kHz Offset
CN Value Control Latch and N Counter Latch L1 and L2 = 18.0 nH L1 and L2 = 110.0 nH L1 and L2 = 560.0 nH
10 μF ≥15 ms −100 dBc/Hz −97 dBc/Hz −99 dBc/Hz
440 nF ≥600 μs −99 dBc/Hz −96 dBc/Hz −98 dBc/Hz

POWER-UP

CLK

R COUNTER CONTROL N COUNTER

DATA
LATCH DATA LATCH DATA LATCH DATA

LE

REQUIRED INTERVAL
07139-033

CONTROL LATCH WRITE TO

N COUNTER LATCH WRITE

Figure 26. Power-Up Timing

Rev. A | Page 17 of 24
ADF4360-9
Software Power-Up/Power-Down
If the part is powered down via the software (using the control
latch) and powered up again without any change to the N counter
latch during power-down, the part locks at the correct frequency
because the part is already in the correct frequency band. The
lock time depends on the value of capacitance on the CN pin,
which is <15 ms for 10 μF capacitance. The smaller capacitance
of 440 nF on this pin enables lock times of <600 μs.
The N counter value cannot be changed while the part is in
power-down because the part may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the part after power-up is to the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
CONTROL LATCH
With (C2, C1) = (0, 0), the control latch is programmed. Figure 23
shows the input data format for programming the control latch.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable power-
down modes.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 is loaded with a 0. In the programmed
synchronous power-down, the device power-down is gated by
the charge pump to prevent unwanted frequency jumps. Once
the power-down is enabled by writing a 1 into Bit PD1 (on the
condition that a 1 is also loaded in PD2), the device goes into
power-down on the second rising edge of the R counter output,
after LE goes high. When a power-down is activated (either
synchronous or asynchronous mode), the following events occur:
• All active dc current paths are removed.
• The R, N, and timeout counters are forced to their load
state conditions.
• The charge pump is forced into three-state mode.
• The digital lock detect circuitry is reset.
• The RF outputs are debiased to a high impedance state.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading
and latching data.
Rev. A | Page 18 of 24
Charge Pump Currents
CPI3, CPI2, and CPI1 in the ADF4360 family determine
Current Setting 1. CPI6, CPI5, and CPI4 determine Current
Setting 2 (see the truth table in Figure 23).
Output Power Level
Bit PL1 and Bit PL2 set the output power level of the VCO (see
the truth table in Figure 23).
Mute-Till-Lock Detect
DB11 of the control latch in the ADF4360 family is the mute-
till-lock detect bit. This function, when enabled, ensures that
the RF outputs are not switched on until the PLL is locked.
CP Gain
DB10 of the control latch in the ADF4360 family is the charge
pump gain bit. When it is programmed to 1, Current Setting 2
is used. When programmed to 0, Current Setting 1 is used.
Charge Pump Three-State
This bit (DB9) puts the charge pump into three-state mode
when programmed to a 1. For normal operation, it should be
set to 0.
Phase Detector Polarity
The PDP bit in the ADF4360 family sets the phase detector
polarity. The positive setting enabled by programming a 1 is
used when using the on-chip VCO with a passive loop filter or
with an active noninverting filter. It can also be set to 0, which
is required if an active inverting loop filter is used.
DIVOUT Control
The on-chip multiplexer is controlled by D3, D2, and D1 (see
the truth table in Figure 23).
Counter Reset
DB4 is the counter reset bit for the ADF4360 family. When this
is 1, the R counter and the A, B counters are reset. For normal
operation, this bit should be 0.
Core Power Level
PC1 and PC2 set the power level in the VCO core. The
recommended setting is 5 mA. The 7.5 mA setting is
permissible in some applications (see the truth table in Figure 23).

N COUNTER LATCH
Figure 24 shows the input data format for programming the
N counter latch.
5-Bit Divider
A5 to A1 program the output divider. The divide range is 2 (00010)
to 31 (11111). If unused, this divider should be set to 0. The output
or the output divided by 2 is available at the DIVOUT pin.
Reserved Bits
DB23, DB22, and DB7 are spare bits and are designated as
reserved. They should be programmed to 0.
B Counter Latch
B13 to B1 program the B counter. The divide range is 3
(00 … 0011) to 8191 (11 … 111).
Overall Divide Range
The overall VCO feedback divide range is defined by B.
CP Gain
DB21 of the N counter latch in the ADF4360 family is the
charge pump gain bit. When it is programmed to 1, Current
Setting 2 is used. When programmed to 0, Current Setting 1 is
used. This bit can also be programmed through DB10 of the
control latch. The bit always reflects the latest value written to it,
whether this is through the control latch or the N counter latch.
Rev. A | Page 19 of 24
ADF4360-9
R COUNTER LATCH
With (C2, C1) = (0, 1), the R counter latch is programmed.
Figure 25 shows the input data format for programming the
R counter latch.
R Counter
R1 to R14 set the counter divide ratio. The divide range is
1 (00 … 001) to 16,383 (111 … 111).
Antibacklash Pulse Width
DB16 and DB17 set the antibacklash pulse width.
Lock Detect Precision
DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with <15 ns phase error for entering the locked
state. With LDP at 1, five cycles are taken; with LDP at 0, three
cycles are taken.
Test Mode Bit
DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs, as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be
programmed by the user.
Band Select Clock
These bits (DB20 and DB21) set a divider for the band select
logic clock input. The output of the R counter is, by default, the
value used to clock the band select logic; if this value is too high
(>1 MHz), a divider can be switched on to divide the R counter
output to a smaller value (see Figure 25). A value of 8 is
recommended.
Reserved Bits
DB23 to DB22 are spare bits that are designated as reserved.
They should be programmed to 0.
ADF4360-9

APPLICATIONS
12
CHOOSING THE CORRECT INDUCTANCE VALUE
The ADF4360-9 can be used at many different frequencies 10
simply by choosing the external inductors to give the correct
output frequency. Figure 27 shows a graph of both minimum

SENSITIVITY (MHz/V)
8
and maximum frequency vs. the external inductor value. The
correct inductor should cover the maximum and minimum 6
frequencies desired. The inductors used are 0603 CS or 0805 CS
type from Coilcraft. To reduce mutual coupling, the inductors 4
should be placed at right angles to one another.
The lowest center frequency of oscillation possible is approximately 2

07139-026
65 MHz, which is achieved using 560 nH inductors. This
relationship can be expressed by 0
0 100 200 300 400 500 600
INDUCTANCE (nH)
1
fO =
2π 9.3 pF(0.9 nH + L EXT )
Figure 28. Tuning Sensitivity vs. Inductance

ENCODE CLOCK FOR ADC

where:
fO is the center frequency. Analog-to-digital converters (ADCs) require a sampling clock
LEXT is the external inductance. for their operation. Generally, this is provided by TCXO or VCXOs,
450
which can be large and expensive. The frequency range is usually
quite limited. An alternative solution is the ADF4360-9, which can
400
be used to generate a CMOS clock signal suitable for use in all
350 but the most demanding converter applications.
Figure 29 shows an ADF4360-9 with a VCO frequency of 320 MHz
FREQUENCY (MHz)

300

250
and a DIVOUT frequency of 80 MHz. Because a 50% duty cycle
is preferred by most sampling clock circuitry, the A/2 mode is
200
selected. Therefore, A is programmed to 2, giving an overall
150 divide value of 4. The AD9215-80 is a 10-bit, 80 MSPS ADC
100
that requires an encode clock jitter of 6 ps or less. The ADF4360-9
takes a 10 MHz TCXO frequency and divides this to 1 MHz;
07139-025

50
therefore, R = 10 is programmed and N = 320 is programmed
0
0 100 200 300 400 500 600
to achieve a VCO frequency of 320 MHz. The resultant 80 MHz
INDUCTANCE (nH) CMOS signal has a jitter of <1.5 ps, which is more than adequate
Figure 27. Output Center Frequency vs. External Inductor Value for the application.
SPI
The approximate value of capacitance at the midpoint of the
center band of the VCO is 9.3 pF, and the approximate value of
internal inductance due to the bond wires is 0.9 nH. The VCO TCXO ADF4360-9
10MHz 80MHz
sensitivity is a measure of the frequency change vs. the tuning
voltage. It is a very important parameter for the low-pass filter.
Figure 28 shows a graph of the tuning sensitivity (in MHz/V) PC
vs. the inductance (nH). It can be seen that as the inductance 21nH
increases, the sensitivity decreases. This relationship can be 470Ω 21nH
derived from the previous equation; that is, because the USB
inductance increased, the change in capacitance from the 470Ω

varactor has less of an effect on the frequency.

SIGNAL
GENERATOR
ENCODE HC-ADC-
AIN CLOCK EVALA-SC
LPF AD9215-80
07139-036

Figure 29. The ADF4360-9 Used as an Encode Clock for an ADC

Rev. A | Page 20 of 24
 ADF4360-9
GSM TEST CLOCK Two 21 nH inductors are required for the specified frequency
Figure 30 shows the ADF4360-9 used to generate three different range. The reference frequency is from a 20 MHz TCXO from
frequencies at DIVOUT. The frequencies required are 45 MHz, Fox; therefore, an R value of 20 is programmed. Taking into
80 MHz, and 95 MHz. This is achieved by generating 360 MHz, account the high PFD frequency and its effect on the band
320 MHz, and 380 MHz and programming the correct A divider select logic, the band select clock divider is enabled. In this case,
ratio. Because a 50% duty cycle is required, the A/2 DIVOUT a value of 8 is chosen. A very simple shunt resistor and dc-blocking
mode is selected. This means that A values of 4, 2, and 2 are capacitor complete the RF output stage. Because these outputs
selected, respectively, for each of the output frequencies are not used, they are terminated in 50 Ω resistors. This is
previously mentioned. recommended for circuit stability. Leaving the RF outputs
open is not recommended.
The low-pass filter was designed using ADIsimPLL™ for a
channel spacing of 1 MHz and an open-loop bandwidth of The CMOS level output frequency is available at DIVOUT. If
40 kHz. Larger PFD frequencies can be used to reduce in-band the frequency has to drive a low impedance load, a buffer is
noise and, therefore, rms jitter. However, for the purposes of recommended.
this example, 1 MHz is used. The measured rms jitter from this
circuit at each frequency is less than 1.5 ps.

LOCK
VVCO VVDD DETECT

10µF 6 2 21 23
VVCO AVDD DVDD LD VTUNE 7
12kΩ
CP 24
14 CN 2.2nF
FOX 1nF 1nF
150pF 56pF
801BE-160 16 REFIN
5.6kΩ
20MHz 51Ω
17 CLK
18 DATA ADF4360-9 DIVOUT 20
19 LE VVCO
SPI-COMPATIBLE SERIAL BUS

12 CC
13 RSET 51Ω 51Ω 100pF
1nF 51Ω
RFOUTA 4
4.7kΩ
CPGND AGND DGND L1 L2 RFOUTB 5
1 3 8 11 22 15 9 10 100pF 51Ω
21nH

470Ω

470Ω 21nH
07139-027

Figure 30.GSM Test Clock

Rev. A | Page 21 of 24
ADF4360-9
INTERFACING
The ADF4360 family has a simple SPI-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits that are clocked into
the appropriate register on each rising edge of CLK are transferred
to the appropriate latch. See Figure 2 for the timing diagram
and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible is 833 kHz, or
one update every 1.2 μs. This is more than adequate for systems
that have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 31 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter®. Because the ADuC812 is based
on an 8051 core, this interface can be used with any 8051-based
microcontrollers. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three
8-bit bytes from the MicroConverter to the device. After the
third byte is written, the LE input should be brought high to
complete the transfer.
SCLOCK SCLK
MOSI SDATA
ADuC812 LE ADF4360-x
I/O PORTS CE
MUXOUT
(LOCK DETECT)
07139-028
Figure 31. ADuC812 to ADF4360-x Interface
I/O port lines on the ADuC812 are used to detect lock (MUXOUT
configured as lock detect and polled by the port input). When
operating in the described mode, the maximum SCLOCK rate
of the ADuC812 is 4 MHz. This means that the maximum rate
at which the output frequency can be changed is 166 kHz.
Rev. A | Page 22 of 24
ADSP-21xx Interface
Figure 32 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated.
SCLOCK SCLK
MOSI SDATA
TFS LE ADF4360-x
ADSP-21xx
CE
I/O PORTS
MUXOUT
(LOCK DETECT)
07139-029
Figure 32. ADSP-21xx to ADF4360-x Interface
Set up the word length for 8 bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the 8-bit bytes, enable the autobuffered mode, and write to
the transmit register of the DSP. This last operation initiates the
autobuffer transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The leads on the chip scale package (CP-24-2) are rectangular.
The PCB pad for these should be 0.1 mm longer than the
package lead length and 0.05 mm wider than the package lead
width. The lead should be centered on the pad to ensure that
the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern to ensure that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated into the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with 1 ounce of copper to plug the via.
The user should connect the printed circuit thermal pad to AGND.
This is internally connected to AGND.
 ADF4360-9
OUTPUT MATCHING The recommended value of this inductor changes with the VCO
There are a number of ways to match the VCO output of the center frequency. Figure 35 shows a graph of the optimum
ADF4360-9 for optimum operation; the most basic is to use a inductor value vs. center frequency.
300
51 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is connected
in series, as shown in Figure 33. Because the resistor is not
250
frequency dependent, this provides a good broadband match.
The output power in the circuit in Figure 33 typically gives
200

INDUCTANCE (nH)
−9 dBm output power into a 50 Ω load.
VVCO
150

51Ω

100pF 100
RFOUT 07139-030

50Ω
50

07139-032
Figure 33. Simple Output Stage 0
0 100 200 300 400 500
A better solution is to use a shunt inductor (acting as an RF CENTER FREQUENCY (MHz)
choke) to VVCO. This gives a better match and, therefore, more Figure 35. Optimum Shunt Inductor vs. Center Frequency
output power.
Both complementary architectures can be examined using the
Experiments have shown that the circuit shown in Figure 34 EVAL-ADF4360-9EBZ1 evaluation board. If the user does not
provides an excellent match to 50 Ω over the operating range of need the differential outputs available on the ADF4360-9, the
the ADF4360-9. This gives approximately 0 dBm output power user should either terminate the unused output with the same
across the specific frequency range of the ADF4360-9 using the circuitry as much as possible or combine both outputs using a
recommended shunt inductor, followed by a 100 pF dc-blocking balun. Alternatively, instead of the LC balun, both outputs can
capacitor. be combined using a 180° rat-race coupler.
VVCO
If the user is only using DIVOUT and does not use the RF
L
outputs, it is still necessary to terminate both RF output pins
with a shunt inductor/resistor to VVCO and also a dc bypass
100pF
RFOUT capacitor and a 50 Ω load. The circuit in Figure 33 is probably
07139-031

50Ω the simplest and most cost-effective solution. It is important

that the load on each pin be balanced because an unbalanced
Figure 34. Optimum Output Stage load is likely to cause stability problems. Terminations should
be identical as much as possible.

Rev. A | Page 23 of 24
ADF4360-9

OUTLINE DIMENSIONS

4.00 0.60 MAX

BSC SQ 0.60 MAX PIN 1
INDICATOR
19 24 1
0.50 18
PIN 1 *2.45
INDICATOR TOP BSC
3.75 EXPOSED
VIEW BSC SQ PAD 2.30 SQ
(BOTTOMVIEW) 2.15
0.50
13 6
0.40 12 7
0.30 0.23 MIN
0.80 MAX 2.50 REF
1.00 12° MAX 0.65 TYP
0.85 0.05 MAX
0.80 0.02 NOM

0.30 COPLANARITY
0.23 0.20 REF 0.08
SEATING
PLANE 0.18

*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2

EXCEPT FOR EXPOSED PAD DIMENSION

Figure 36. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Package Description Frequency Range Package Option
ADF4360-9BCPZ 1 −40°C to +85°C 24-Lead LFCSP_VQ 65 MHz to 400 MHz CP-24-2
ADF4360-9BCPZRL1 −40°C to +85°C 24-Lead LFCSP_VQ 65 MHz to 400 MHz CP-24-2
ADF4360-9BCPZRL71 −40°C to +85°C 24-Lead LFCSP_VQ 65 MHz to 400 MHz CP-24-2
EVAL-ADF4360-9EBZ11 Evaluation Board
1
Z = RoHS Compliant Part.

©2008 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D07139-0-3/08(A)

Rev. A | Page 24 of 24