SH68N65DM6AG

Datasheet

Automotive-grade N-channel 650 V, 35 mΩ typ., 64 A MDmesh DM6 half-bridge

topology Power MOSFET in an ACEPACK SMIT package

8
9
Features
7
Order code VDS RDS(on) max. ID
1
3 SH68N65DM6AG 650 V 41 mΩ 64 A
4
6
7
8 • AQG 324 qualified
9
• Half-bridge power module
6 • 650 V blocking voltage
4
3 • Fast recovery body diode
1
ACEPACK SMIT • Very low switching energies
GADG060720221002SA 9 (DC+)
• Low package inductance
• Dice on direct bond copper (DBC) substrate
• Low thermal resistance
1 (GHS) • Isolation rating of 3.4 kVrms/min
2 (KHS)

7 (U)
Applications
3, 4 (NC)

• Switching applications
6 (GLS)

5 (KLS) Description
8 (DC-)
This device combines two MOSFETs in a half-bridge topology. The ACEPACK SMIT
is a very compact and rugged power module in a surface mount package for easy
assembly. Thanks to the DBC substrate, the ACEPACK SMIT package offers low
thermal resistance coupled with an isolated top-side thermal pad. The high design
flexibility of the package enables several configurations, including phase legs, boost,
and single switch through different combinations of the internal power switches.

Product status link

SH68N65DM6AG

Product summary

Order code SH68N65DM6AG

Marking H68N65DM6
Package ACEPACK SMIT
Packing Tape and reel

DS14027 - Rev 1 - July 2022 www.st.com

For further information contact your local STMicroelectronics sales office.
 SH68N65DM6AG
Electrical ratings

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VGS Gate-source voltage ±25 V

ID Drain current (continuous) at TC = 25 °C 64 A

ID Drain current (continuous) at TC = 100 °C 40 A

IDM (1)
Drain current (pulsed) 280 A

PTOT Total power dissipation at TC = 25 °C 379 W

dv/dt (2) Peak diode recovery voltage slope 100 V/ns

di/dt (2) Peak diode recovery current slope 1000 A/μs

dv/dt (3) MOSFET dv/dt ruggedness 100 V/ns

Isolation withstand voltage applied between each pin and heat sink plate
VISO 3.4 kVrms
(AC voltage (50/60 Hz, t = 60 s)
TSTG Storage temperature range °C
-55 to 150
TJ Operating junction temperature range °C

1. Pulse width limited by safe operating area.

2. ISD ≤ 64 A, VDS (peak) < V(BR)DSS, VDD = 400 V.
3. VDS ≤ 520 V.

Table 2. Thermal data

Symbol Parameter Value Unit

RthJC Thermal resistance, junction-to-case 0.33 °C/W

Table 3. Avalanche characteristics

Symbol Parameter Value Unit

IAR Avalanche current, repetitive or not repetitive (tp limited by TJ max) 9 A

EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR) 1.9 J

DS14027 - Rev 1 page 2/15

 SH68N65DM6AG
Electrical characteristics

2 Electrical characteristics

TC = 25 °C unless otherwise specified

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 650 V

VGS = 0 V, VDS = 650 V 5

IDSS Zero gate voltage drain current μA
VGS = 0 V, VDS = 650 V, TC = 125 °C (1)
300

IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 μA

VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA 3.25 4 4.75 V

RDS(on) Static drain-source on resistance VGS = 10 V, ID = 23 A 35 41 mΩ

1. Defined by design, not subject to production test.

Table 5. Dynamic characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitance - 5900 -

Coss Output capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V - 260 -

pF
Crss Reverse transfer capacitance - 2.6 -

Coss eq.(1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 867 -

RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 1.4 - Ω

Qg Total gate charge - 116 -

VDD = 520 V, ID = 72 A, VGS = 0 to 10 V
Qgs Gate-source charge (see Figure 13. Test circuit for gate - 37 - nC

Qgd charge behavior)

Gate-drain charge - 45 -

1. Coss eq is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.

Table 6. Switching characteristics (resistive load)

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time VDD = 325 V, ID = 36 A, - 42 - ns

tr Rise time RG = 4.7 Ω , VGS = 10 V - 19 - ns

td(off) Turn-off delay time (see Figure 12. Switching times - 108 - ns
test circuit for resistive load and
tf Fall time Figure 17. Switching time waveform) - 11 - ns

DS14027 - Rev 1 page 3/15

 SH68N65DM6AG
Electrical characteristics

Table 7. Switching characteristics (inductive load)

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(v) Voltage delay time VDD = 400 V, VGS = 0 to 10 V, ID = 72 A, - 117 -

tr(v) Voltage rise time RG = 6.8 Ω (see Figure 14. Test - 10 -

circuit for inductive load switching
tf(i) Current fall time and diode recovery times and - 18 -
Figure 18. Turn-off switching time
tc(off) Crossing time off waveform on inductive load) - 24 -
ns
td(i) Current delay time VDD = 400 V, VGS = 0 to 10 V, ID = 72 A, - 354 -

tf(i) Current rise time RG = 82 Ω (see Figure 14. Test - 140 -

circuit for inductive load switching
tf(v) Voltage fall time and diode recovery times and - 14 -
Figure 19. Turn-on switching time
tc(on) Crossing time on waveform on inductive load) - 252 -

Table 8. Source-drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD Source-drain current - 64 A

ISDM(1) Source-drain current (pulsed) - 280 A

VSD(2) Forward on voltage VGS = 0 V, ISD = 46 A - 1.6 V

trr Reverse recovery time - 166 ns

ISD = 72 A, di/dt = 100 A/μs, VDD = 60 V
Qrr Reverse recovery charge (see Figure 14. Test circuit for inductive - 1.1 µC

IRRM load switching and diode recovery times)

Reverse recovery current - 11 A

trr Reverse recovery time ISD = 72 A, di/dt = 100 A/μs, - 336 ns

Qrr Reverse recovery charge VDD = 60 V, TJ = 150 °C - 5.1 µC

(see Figure 14. Test circuit for inductive
IRRM Reverse recovery current - 26 A
load switching and diode recovery times)

1. Pulse width is limited by safe operating area.

2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.

DS14027 - Rev 1 page 4/15

 SH68N65DM6AG
Electrical characteristics (curves)

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Maximum transient thermal impedance

ID GADG200720201639SOA ZthJC GADG050720221012ZTH

(A) IDM (°C/W)
tp =1µs duty=0.5
ea
10 2
s ar
i )
10 -1
th (on 0.4
in R DS
io n y tp =10µs 0.1
at d b 0.3
10 1 er ite V(BR)DSS 0.05
Op lim
is RDS(on) max. 0.2
10 -2
tp =100µs
10 0
RthJC = 0.33 °C/W

TC = 25 °C tp =1ms 10 -3 duty = ton / T

10 -1
TJ ≤ 150 °C Single pulse
ton
VGS=10 V
single pulse tp =10ms T
10 -2 10 -4
10 -1 10 0 10 1 10 2 VDS (V) 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 tp (s)

Figure 3. Typical output characteristics Figure 4. Typical transfer characteristics

ID GADG050720221014OCH ID GADG050720221014TCH
(A) (A)
VGS=9, 10 V
250 250

VGS=8 V VGS = 20 V
200 200

150 150

VGS=7 V
100 100

50 50
VGS=6 V

0 0
0 4 8 12 16 VDS (V) 5 6 7 8 9 VGS (V)

Figure 5. Typical gate charge characteristics Figure 6. Typical drain-source on-resistance

VDS GADG050720221014QVG VGS RDS(on) GADG050720221015RID

(V) (V) (mΩ)
Qg

500 10
37
VGS VGS= 10 V
400 8
Qgs Qgd

300 6 36

VDD= 520 V
200 4
ID = 72 A
35
100 2
VDS
0 0 34
0 20 40 60 80 100 120 Qg (nC) 20 30 40 50 60 70 ID (A)

DS14027 - Rev 1 page 5/15

 SH68N65DM6AG
Electrical characteristics (curves)

Figure 7. Typical capacitance characteristics Figure 8. Normalized gate threshold vs temperature

C GADG200720201040CVR VGS(th) GADG050720221015VTH

(pF) (norm.)
1.1
10 4
Ciss ID = 250 μA
1.0

10 3
0.9

Coss 0.8
10 2

0.7
10 1 f = 1 MHz Crss
0.6

10 0 0.5
10 -1 10 0 10 1 10 2 VDS (V) -75 -25 25 75 125 TJ (°C)

Figure 9. Normalized on-resistance vs temperature Figure 10. Normalized breakdown voltage vs temperature

RDS(on) GADG050720221017RON V(BR)DSS GADG050720221017BDV

(norm.) (norm.)

2.0 1.10
ID = 1 mA ID = 1 mA

1.5 1.05

1.0 1.00

0.5 0.95

0.0 0.90
-75 -25 25 75 125 TJ (°C) -75 -25 25 75 125 TJ (°C)

Figure 11. Typical reverse diode forward characteristics

VSD GADG050720221018SDF
(V)
TJ= -40 °C
1.1

1.0
TJ= 25 °C

0.9

0.8
TJ= 150 °C
0.7

0.6

0.5
0 10 20 30 40 50 60 70 ISD (A)

DS14027 - Rev 1 page 6/15

 SH68N65DM6AG
Test circuits

3 Test circuits

Figure 13. Test circuit for gate charge behavior

Figure 12. Switching times test circuit for resistive load

VDD

RL

RL 2200 3.3
µF µF
+ VDD IG= CONST D.U.T.
VD VGS 100 Ω
VGS
RG pulse width +
2.7 kΩ
D.U.T. 2200 VG
μF
PW 47 kΩ

GND1 GND2 1 kΩ
(driver signal) (power)

AM15855v1 GND1 GND2

GADG180720181011SA

Figure 14. Test circuit for inductive load switching and

Figure 15. Unclamped inductive load test circuit
diode recovery times

A A A L
D
FAST L=100µH
G D.U.T. DIODE VD
2200 3.3
S B 3.3 1000 µF µF VDD
B B µF µF +
25Ω D + VDD
ID
G
RG S
D.U.T.
Vi D.U.T.

GND2
Pw
GND1
GND1 GND2 AM15858v1
AM15857v1

Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform

ton toff
V(BR)DSS
td(on) tr td(off) tf
VD

90% 90%
IDM

10% VDS 10%

ID 0

VDD VDD
VGS 90%

0 10%

AM01472v1 AM01473v1

DS14027 - Rev 1 page 7/15

 SH68N65DM6AG
Test circuits

Figure 18. Turn-off switching time waveform Figure 19. Turn-on switching time waveform
on inductive load on inductive load

ID VDS VDS ID
90%VDS 90%ID 90%ID 90%VDS

VGS 90%VGS 90%VGS

10%VDS 10%ID 10%ID 10%VDS

10%VGS
tr(v) tf(i) ID tr(i) tf(v) VDS
VDS ID

td(v) tc(off) td(i) tc(on)

AM05540v3 GADG241120211046SWTW

DS14027 - Rev 1 page 8/15

 SH68N65DM6AG
Package information

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

4.1 ACEPACK SMIT package information

Figure 20. ACEPACK SMIT package outline

DM00447519_Rev.6

DS14027 - Rev 1 page 9/15

 SH68N65DM6AG
ACEPACK SMIT package information

Table 9. ACEPACK SMIT package mechanical data

mm
Dim.
Min. Typ. Max.

A 19.50 20.00 20.50

B 21.50 22.00 22.50
C 22.80 23.00 23.20
D 24.80 25.00 25.20
E 32.20 32.70 33.20
b 9.00
b1 4.00
b2 6.75
b3 9.50
c 0.95 1.00 1.10
c1 1.95 2.00 2.10
d 0.00 0.15
d1 0.45 0.55 0.65
e 1.30 1.50 1.70
e1 4.65 4.85 5.05
L 3.95 4.00 4.05
L1 5.40 5.50 5.60
m 1.30 1.50 1.80
m1 1.30 1.50 1.80
V 0° 2° 4°
aaa 0.01 0.05
bbb 0.00 0.10

DS14027 - Rev 1 page 10/15

 SH68N65DM6AG
ACEPACK SMIT package information

Figure 21. ACEPACK SMIT recommended footprint

2.75 (x4)
4.00 (x9)

9.00 (x2)

4.00 (x2)
2.40 (x3)

1.40 (x6)

30.10 DM00447519_FP_Rev.6

Note: Dimensions in mm.

Figure 22. ACEPACK SMIT marking orientation vs pinout

FRONT SIDE

9 7

B
A C D

F G H I J K L

1 6

BACK SIDE

7 9

D A B C

E F G H

6 1

DM00447519_MO_Rev.6

DS14027 - Rev 1 page 11/15

 SH68N65DM6AG
ACEPACK SMIT packing information

4.2 ACEPACK SMIT packing information

Figure 23. ACEPACK SMIT tape outline

DM00631393_Tape_Rev.1

Note: Dimensions in mm.

DS14027 - Rev 1 page 12/15

 SH68N65DM6AG

Revision history

Table 10. Document revision history

Date Revision Changes

25-Jul-2022 1 First release.

DS14027 - Rev 1 page 13/15

 SH68N65DM6AG
Contents

Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1 ACEPACK SMIT package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 ACEPACK SMIT packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

DS14027 - Rev 1 page 14/15

 SH68N65DM6AG

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DS14027 - Rev 1 page 15/15