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MOSFET– POWERTRENCH),
P-Channel
-30 V, -122 A, 3.2 mW
General Description
The FDMS6681Z has been designed to minimize losses in load www.onsemi.com
switch applications. Advancements in both silicon and package
technologies have been combined to offer the lowest rDS(on) and ESD
protection.
D 5 4 G
Features
• Max rDS(on) = 3.2 mW at VGS = −10 V, ID = −21.1 A D 6 3 S
DBV DSS Breakdown Voltage Temperature ID = −250 mA, referenced to 25°C 20 mV/°C
Coefficient
DT J
IDSS Zero Gate Voltage Drain Current VDS = −24 V, VGS = 0 V −1 mA
IGSS Gate to Source Leakage Current VGS = ±25 V, VDS = 0 V ±10 mA
ON CHARACTERISTICS
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = −250 mA −1 −1.7 −3 V
DV GS(th) Gate to Source Threshold Voltage ID = −250 mA, referenced to 25°C −7 mV/°C
Temperature Coefficient
DT J
rDS(on) Static Drain to Source On Resistance VGS = −10 V, ID = −22.1 A 2.7 3.2 mW
VGS = −4.5 V, ID = −15.7 A 4.0 5.0
VGS = −10 V, ID = −22.1 A, 3.9 5.0
TJ = 125°C
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FDMS6681Z
NOTES:
1. RqJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 × 1.5 in. board of FR−4 material. RqJC is guaranteed
by design while RqCA is determined by the user’s board design.
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
4. Pulsed ID please refer to Figure 12 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal
electro−mechanical application board design.
90 5
PULSE DURATION = 80 ms
VGS = −3.5 V VGS = −3 V DUTY CYCLE = 0.5% MAX
Normalized Drain to Source
75 4
−ID, Drain Current [A]
VGS = −4 V
On−Resistance
VGS = −3.5 V
60 VGS = −4.5 V
3
VGS = −10 V
45 VGS = −4.5 V
VGS = −4 V
2
30
VGS = −3 V
1
15 VGS = −10 V
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
0 0
0 1 2 3 0 15 30 45 60 75 90
−VDS, Drain to Source Voltage [V] −ID, Drain Current [A]
1.4
On−Resistance [mW]
9
ID = −22.1 A
On−Resistance
1.2
6
TJ = 125°C
1.0
3
0.8 TJ = 25°C
0.6 0
−75 −50 −25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, Junction Temperature [5C] −VGS, Gate to Source Voltage [V]
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FDMS6681Z
90 100
PULSE DURATION = 80 ms VGS = 0 V
60 TJ = 150°C
1
TJ = 150°C
45 TJ = 25°C
0.1
30
TJ = 25°C
0.01
15 TJ = −55°C TJ = −55°C
0 0.001
0 1 2 3 4 0 0.2 0.4 0.6 0.8 1.0 1.2
−VGS, Gate to Source Voltage [V] −VSD, Body Diode Forward Voltage [V]
10 20000
ID = −22.1 A
−VGS, Gate to Source Voltage [V]
8 10000
VDD = −10 V
Capacitance [pF]
Ciss
6
VDD = −15 V
4
VDD = −20 V Coss
f = 1 MHz
2 Crss
1000 VGS = 0 V
0 600
0 50 100 150 200 0.1 1 10 30
Qg, Gate Charge [nC] −VDS, Drain to Source Voltage [V]
100 140
50 120
−IAS, Avalanche Current [A]
100
80
TJ = 100°C
60 VGS = −4.5 V
TJ = 125°C 40
20
RqJC = 1.7°C/W
1 0
0.001 0.01 0.1 1 10 100 25 50 75 100 125 150
tAV, Time in Avalanche [ms] TC, Case Temperature [5C]
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FDMS6681Z
10−4 1000
VGS = 0 V 10 us
Ig, Gate Leakage Current [A]
10−5
100
10−6 TJ = 150°C
THIS AREA IS 1 ms
10 LIMITED BY rDS(on)
10−7 10 ms
TJ = 25°C
DC
1 SINGLE PULSE
10−8 TJ = MAX RATED
CURVE BENT TO RqJC = 1.7°C/W
MEASURE DATA TC = 25°C
10−9 0.1
0 5 10 15 20 25 30 0.1 1 10 80
VGS, Gate to Source Voltage [V] −VDS, Drain to Source Voltage [V]
Figure 11. Igss vs. Vgss Figure 12. Forward Bias Safe Operating Area
100000
SINGLE PULSE
P(PK), Peak Transient Power [W]
RqJC = 1.7°C/W
TC = 25°C
10000
1000
100
10
10−5 10−4 10−3 10−2 10−1 1
t, Pulse Width [s]
2
1 DUTY CYCLE−DESCENDING ORDER
Transient Thermal Resistance
r(t), Normalized Effective
D = 0.5
0.2
0.1 PDM
0.1 0.05
0.02
0.01 t1
t2
0.01 NOTES:
ZqJC (t) = r(t) × RqJC
SINGLE PULSE RqJC = 1.7°C/W
PEAK TJ = PDM × ZqJC (t) + TC
Duty cycle, D = t1/t2
0.001
10−5 10−4 10−3 10−2 10−1 1
t, Pulse Width [s]
POWERTRENCH is registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in
the United States and/or other countries.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DOCUMENT NUMBER: 98AON13655G Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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