FDC6312P

January 2001

FDC6312P
Dual P-Channel 1.8V PowerTrench Specified MOSFET

General Description Features

These P-Channel 1.8V specified MOSFETs are • –2.3 A, –20 V. RDS(ON) = 115 mΩ @ VGS = –4.5 V
produced using Fairchild Semiconductor's advanced
PowerTrench process that has been especially tailored RDS(ON) = 155 mΩ @ VGS = –2.5 V
to minimize on-state resistance and yet maintain low RDS(ON) = 225 mΩ @ VGS = –1.8 V
gate charge for superior switching performance.
• High performance trench technology for extremely
Applications low RDS(ON)

• Power management
• SuperSOTTM-6 package: small footprint (72%
• Load switch smaller than standard SO-8); low profile (1mm thick)

D2
S1 4 3
D1
5 2
G2
S2 6 1
TM
SuperSOT -6 G1

Absolute Maximum Ratings TA=25oC unless otherwise noted

Symbol Parameter Ratings Units

VDSS Drain-Source Voltage –20 V
VGSS Gate-Source Voltage ±8 V
ID Drain Current – Continuous (Note 1a) –2.3 A
– Pulsed –7
PD Power Dissipation for Single Operation (Note 1a) 0.96 W
(Note 1b) 0.9
(Note 1c) 0.7
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C

Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 130 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity
.312 FDC6312P 13’’ 12mm 3000 units

2001 Fairchild Semiconductor Corporation FDC6312P Rev C (W)

 FDC6312P
Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = –250 µA –20 V
∆BVDSS Breakdown Voltage Temperature
ID = –250 µA,Referenced to 25°C –11 mV/°C
∆TJ Coefficient
IDSS Zero Gate Voltage Drain Current VDS = –16 V, VGS = 0 V –1 µA
IGSSF Gate–Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA
IGSSR Gate–Body Leakage, Reverse VGS = –8 V, VDS = 0 V –100 nA

On Characteristics (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = –250 µA –0.4 –0.9 –1.5 V
∆VGS(th) Gate Threshold Voltage ID = –250 µA,Referenced to 25°C
2 mV/°C
∆TJ Temperature Coefficient
RDS(on) Static Drain–Source VGS = –4.5 V, ID = –2.3 A 92 115 mΩ
On–Resistance VGS = –2.5 V, ID = –1.9 A 116 155
VGS = –1.8 V, ID = –1.6 A 166 225
VGS=–4.5 V, ID =–2.3A, TJ=125°C 112 150
ID(on) On–State Drain Current VGS = –4.5 V, VDS = –5 V –7 A
gFS Forward Transconductance VDS = –5 V, ID = –3.5 A 5.3 S

Dynamic Characteristics
Ciss Input Capacitance VDS = –10 V, V GS = 0 V, 467 pF
Coss Output Capacitance f = 1.0 MHz 85 pF
Crss Reverse Transfer Capacitance 38 pF

Switching Characteristics (Note 2)

td(on) Turn–On Delay Time VDD = –10 V, ID = –1 A, 8 16 ns
tr Turn–On Rise Time VGS = –4.5 V, RGEN = 6 Ω 13 23 ns
td(off) Turn–Off Delay Time 18 32 ns
tf Turn–Off Fall Time 8 16 ns
Qg Total Gate Charge VDS = –10 V, ID = –2.3 A, 4.4 7 nC
Qgs Gate–Source Charge VGS = –4.5 V 1.0 nC
Qgd Gate–Drain Charge 0.8 nC

Drain–Source Diode Characteristics and Maximum Ratings

IS Maximum Continuous Drain–Source Diode Forward Current –0.8 A
Drain–Source Diode Forward
VSD VGS = 0 V, IS = –0.8 A (Note 2) –0.7 –1.2 V
Voltage
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.

a) 130 °C/W when

b) 140°/W when mounted
mounted on a 0.125 c) 180°/W when mounted on a
on a .004 in2 pad of 2 oz
in2 pad of 2 oz. minimum pad.
copper
copper.

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%

FDC6312P Rev C (W)

 FDS6312P
Typical Characteristics

6 2.5
VGS = -4.5V

DRAIN-SOURCE ON-RESISTANCE
-3.0V 2.25
5 -3.5V VGS = -1.8V
-ID, DRAIN CURRENT (A)

RDS(ON), NORMALIZED
-2.5V
2
4
-2.0V
1.75
-2.0V
3
1.5
-1.8V
-2.5V
2 1.25 -3.0V
-3.5V
1 1 -4.5V
-1.5V

0.75
0
0 1 2 3 4 5 6
0 0.5 1 1.5 2 2.5
-ID, DRAIN CURRENT (A)
-VDS, DRAIN-SOURCE VOLTAGE (V)

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage.

1.6 0.35
ID = -2.3A
ID = -0.8 A
DRAIN-SOURCE ON-RESISTANCE

VGS =-4.5V
RDS(ON), ON-RESISTANCE (OHM)

0.3
1.4
RDS(ON), NORMALIZED

0.25
1.2

0.2
1 TA = 125oC
0.15

0.8
0.1
TA = 25oC
0.6
0.05
-50 -25 0 25 50 75 100 125 150
1 2 3 4 5
TJ, JUNCTION TEMPERATURE (oC) -VGS, GATE TO SOURCE VOLTAGE (V)

Figure 3. On-Resistance Variation with Figure 4. On-Resistance Variation with

Temperature. Gate-to-Source Voltage.

6 10
VGS = 0V
TA = -55oC
-IS, REVERSE DRAIN CURRENT (A)

VDS = 5V 25oC
5 1
TA = 125oC
-ID, DRAIN CURRENT (A)

125oC
4 25oC
0.1
-55oC
3
0.01
2
0.001
1

0.0001
0
0 0.2 0.4 0.6 0.8 1 1.2
0.5 1 1.5 2 2.5 3
-VSD, BODY DIODE FORWARD VOLTAGE (V)
-VGS, GATE TO SOURCE VOLTAGE (V)

Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation

with Source Current and Temperature.

FDC6312P Rev C (W)

 FDS6312P
Typical Characteristics

5 700
ID = -2.3A VDS = -5V f = 1MHz
-VGS, GATE-SOURCE VOLTAGE (V)

-10V 600 VGS = 0 V

4
-15V

CAPACITANCE (pF)
500
CISS
3
400

300
2

200
1
100 COSS
CRSS
0 0
0 1 2 3 4 5 6 0 5 10 15 20
Qg, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.

100 5
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
4 RθJA = 180°C/W
-ID, DRAIN CURRENT (A)

10 1ms TA = 25°C
RDS(ON) LIMIT
10ms
100ms 3
1s
1
10s
DC 2
VGS = -4.5V
SINGLE PULSE
0.1
RθJA = 180oC/W 1
TA = 25oC

0.01 0
0.1 1 10 100 0.01 0.1 1 10 100 1000
-VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)

Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.

1
TRANSIENT THERMAL RESISTANCE

D = 0.5
r(t), NORMALIZED EFFECTIVE

0.2 RθJA(t) = r(t) + RθJA

RθJA = 180°C/W
0.1 0.1
0.05
0.02
P(pk)
0.01 t1
0.01 t2

SINGLE PULSE
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2

0.001
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)

Figure 11. Transient Thermal Response Curve.

Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.

FDC6312P Rev C (W)

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™ FAST  OPTOLOGIC™ SMART START™ VCX™
Bottomless™ FASTr™ OPTOPLANAR™ STAR*POWER™
CoolFET™ FRFET™ PACMAN™ Stealth™
CROSSVOLT™ GlobalOptoisolator™ POP™ SuperSOT™-3
DenseTrench™ GTO™ Power247™ SuperSOT™-6
DOME™ HiSeC™ PowerTrench  SuperSOT™-8
EcoSPARK™ ISOPLANAR™ QFET™ SyncFET™
E2CMOSTM LittleFET™ QS™ TinyLogic™
EnSignaTM MicroFET™ QT Optoelectronics™ TruTranslation™
FACT™ MicroPak™ Quiet Series™ UHC™
FACT Quiet Series™ MICROWIRE™ SILENT SWITCHER  UltraFET 
STAR*POWER is used under license
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4