--tp1--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41 IS
PORT (
E:in std_logic_vector (3 downto 0);
sel: in STD_LOGIC_VECTOR (1 DOWNTO 0);
S:OUT STD_LOGIC);
END MUX41 ;
Architecture flot_MUX41 of MUX41 is
Begin
S <=(((not sel(0) and not sel(1)) and E(0)) or
((sel(0) and not sel(1)) and E(1)) or
((not sel(0) and sel(1)) and E(2)) or
(sel(0) and sel(1) and E(3)));
End flot_MUX41;
--tp2—
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41 IS
PORT (
E:in std_logic_vector (3 downto 0);
SEL:in STD_LOGIC_VECTOR (1 DOWNTO 0);
S:OUT STD_LOGIC);
END MUX41 ;
Architecture CDT_MUX41 of MUX41 is
Begin
S<= E(0) WHEN (SEL="00")ELSE
E(1) WHEN (SEL="01")ELSE
E(2) WHEN (SEL="10")ELSE
E(3);
END CDT_MUX41;
--tp3—
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41 IS
PORT (
E:in std_logic_vector (3 downto 0);
A: in STD_LOGIC_VECTOR (1 DOWNTO 0);
S:OUT STD_LOGIC);
END MUX41 ;
Architecture selec_MUX41 of MUX41 is
Begin
with A select
s<= E(0) WHEN "00",
E(1) WHEN "01",
E(2) WHEN "10",
E(3) WHEN OTHERS;
END selec_MUX41;
--tp3—
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41 IS
PORT (
E:in std_logic_vector (3 downto 0);
SEL:in STD_LOGIC_VECTOR (1 DOWNTO 0);
S:OUT STD_LOGIC);
END MUX41 ;
Architecture Compor1_MUX41 of MUX41 is
Begin
Process (SEL)
Begin
if (SEL(0) = '0' and SEL(1) = '0' ) then S <= E(0);
elsif (SEL(0) = '1' and SEL(1) = '0') then S <= E(1);
elsif (SEL(0) = '0' and SEL(1) = '1' ) then S <= E(2);
Else S <= E(3);
End if;
END Process;
END Compor1_MUX41;
--tp4—

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41 IS
PORT (
E:in std_logic_vector (3 downto 0);
SEL:in STD_LOGIC_VECTOR (1 DOWNTO 0);
S:OUT STD_LOGIC);
END MUX41 ;
Architecture Compor2_MUX41 of MUX41 is
Begin
Process (SEL)
Begin
Case SEL is
when "00"=> S <= E(0);
when "01"=> S <= E(1);
when "10" => S <= E(2);
when "11" => S <= E(3);
End case;
End process;
End Compor2_MUX41;