Learning Maps

Cadence Training Services learning maps provide a comprehensive visual overview of the
learning opportunities for Cadence customers. They provide recommended course flows as well
as tool experience and knowledge levels to guide students through a complete learning plan.
Learning Maps cover all Cadence® technologies and reference courses available worldwide.
For course names, descriptions, and schedules, please select the Browse Catalog button at
https://www.cadence.com/training.
Contents
• PCB Design and Analysis • System Design and Analysis • Computational Fluid Dynamics
• Custom IC, Analog, and RF Design • IC Package Design and Analysis
• Digital Design and Signoff • Tensilica® Processor IP
 PCB Design
Learning Mapand Analysis
Digital Learning
Design Map
and Signoff
Logic Design PCB Design SI/PI Analysis Library Development
Allegro® Design Entry Allegro Design Entry Allegro PCB Editor Basic Essential High-Speed PCB Allegro PCB Librarian
Beginner

Beginner
HDL Front-to-Back Using OrCAD® Techniques Design for Signal Integrity
Flow Capture
PCB Design at RF – Multi-
Allegro Design Entry OrCAD CIS Allegro PCB Editor Allegro EDM PCB Librarian
Gigabit Transmission, EMI
HDL Intermediate Techniques
Control, and PCB Materials
Basics
OrCAD Capture
Constraint Manager
Allegro System Allegro PCB Router Basics Allegro Sigrity™ SI Foundations
PCB Flow
Capture
Allegro EDM Design Allegro Sigrity PI
Entry HDL Front-to-
Allegro System Back Flow Allegro PCB Editor Advanced
Sigrity PowerDC™ and
Architect Methodologies
OptimizePI™
Allegro Team Design
Authoring
Allegro Design Reuse Sigrity Aurora
Allegro High-Speed Constraint
Management
Analog Simulation
with PSpice® TopXplorer SystemSI for Allegro Design Entry HDL SKILL®
Parallel Bus and Serial Link Programming Language
Analog Simulation Analysis
Allegro AMS Allegro Update Training
with PSpice ® using
Simulator Model Generation and Analysis
System Capture
using PowerSI and Broadband Allegro PCB Editor SKILL
SPICE Programming Language
Allegro AMS Analog Simulation Advanced Design Verification
Simulator with PSpice with the RAVEL Programming Clarity 3D Solver
Advanced Advanced Language Celsius Thermal Solver

Advanced
Advanced

Analysis Analysis
New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2020 Cadence Design Systems, Inc.
 IC Package
Learning Design and Analysis
Map Digital Learning
Design and SignoffMap
IC Package Design SI/PI Analysis

SiP Layout Allegro Sigrity™ SI Foundations

Beginner

Beginner
Allegro® Package Designer Allegro Sigrity PI

Allegro FPGA System Planner Sigrity PowerDC™ and OptimizePI™

Allegro Sigrity Package Assessment and Model Extraction TopXplorer SystemSI for Parallel Bus and Serial Link Analysis

OrbitIO™ System Planner Model Generation and Analysis using PowerSI and Broadband SPICE

Advanced Design Verification with the RAVEL Programming Clarity 3D Solver

Language

Allegro Package Designer Plus Celsius Thermal Solver

Advanced
Advanced

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2020 Cadence Design Systems, Inc.
 Custom IC,Learning
Analog,Map Digital Design
Microwave and RFand Signoff
Design Learning Map 1 of 2 – see next page

Circuit Modeling, Analog/Mixed-Signal/RF Circuit Design and Simulation

Mixed-Signal Simulation Virtuoso Schematic Editor Spectre ® Simulator
Beginner

Beginner
Mixed-Signal Simulations using
Fundamentals Series
Spectre AMS Designer S1 Spectre Basics
Virtuoso Visualization and Analysis
S2 Large-Signal Analysis
Command-Line Based Mixed- S3 Small-Signal Analysis
Signal Simulations w/ Xcelium Virtuoso® ADE Explorer & Assembler Series
Use Model S4 Spectre MDL
S1 ADE Explorer & Single Test Corner Analysis
SimVision for Debugging Mixed-
Signal Simulations S2 ADE Assembler & Multi Test Corner Analysis
Design Checks and Asserts
S3 Sweeping Variables and Simulating Corners
AMS/Real Number Modeling High Performance Spectre
S4 Monte Carlo, Real-Time Tuning & Run Plans Simulation (APS, Spectre X)
Analog Modeling with Verilog-A

Virtuoso® ADE Verifier Series Spectre FX Simulator

Behavioral Modeling with S1 Setup, Run, & View Verifier Results
Verilog AMS Virtuoso ® Spectre ® Pro Series
S2 Reference Flow and Analog Coverage Using the S1 DC Algorithm
Real Modeling with Setup Library Assistant
Verilog-AMS S2 Transient Algorithm
Microwave & RF Design (AWR ®)
Real Modeling with
SystemVerilog Microwave Office for RF Designers Spectre ® RF Series
Spectre RF Shooting Newton
SystemVerilog Real Number
5G mmWave Handset System Design –
Modeling (SV-RNM) Based Spectre RF Harmonic Balance
S1 RFIC (Transceiver) Design

Advanced
Advanced

Advanced Verification

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2020 Cadence Design Systems, Inc.
 Custom IC, Analog
Learning and RF
Map Digital Design
Design Learning
and Signoff Map 2 of 2 – see prior page

IC CAD Layout Design and Advanced Nodes Layout Verification

SKILL® Language Virtuoso® Layout Design Basics Virtuoso® Layout Pro Series Quantus™
Beginner

Beginner
Pegasus
Programming T1: Env. and Basic Commands Extraction
Verification
Introduction Solution
System
T2: Create and Edit Commands Transistor-Level
SKILL Language Virtuoso Connectivity-Driven Series
Programming Layout Transition T3: Basic Commands
Physical T1: Overview
E
Verification and Technology
T4: Advanced Commands
System (PVS) Setup
SKILL Development
of Parameterized Virtuoso Abstract Generator T5: Interactive Routing
Cells
T2: Parasitic
T6: Constraint-Driven Flow
Extraction
Virtuoso Floorplanner and Power Routing
Advanced SKILL Physical
T7: Module Generator Verification
Language
and Floorplanner Language T3: Extracted
Programming
Rules-Writer View Flows
T8: Concurrent Layout Editing E
Virtuoso® Advanced-Node – ICADVM and
Advanced
Virtuoso Layout for Advanced T9: Virtuoso Design Planner E
Features
Nodes

T1: Place and Route

T2: Electromigration

Virtuoso Layout for Advanced

Nodes and Methodology
Platform E

Advanced
Advanced

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2020 Cadence Design Systems, Inc.
 Digital Design
Learning and Signoff
Map Digital DesignLearning Map
and Signoff
Synthesis and Test Implementation Silicon Signoff Equivalence Checking
Cadence® RTL-to-GDSII Flow
Beginner

Beginner
Design For Test
Fundamentals of IEEE 1801 Low- Fundamentals
Power Specification
Format Basic Static Timing Analysis
Genus™ Synthesis Solution with
Stylus Common UI
Innovus Block Implementation Tempus™ Signoff Timing Conformal® Equivalence
Genus Low-Power Synthesis with Stylus Common UI Analysis and Closure with Stylus Checking
Flow with IEEE 1801 Common UI
Innovus Hierarchical
Low-Power Synthesis Flow Implementation with Stylus Voltus™ Power Grid Analysis Conformal Low-Power
with Genus Stylus Common UI Common UI and Signoff with Stylus Common Verification
Innovus Low-Power Flow with UI
Test Synthesis with Genus Stylus Stylus Common UI
Common UI Conformal Low-Power
Verification Using IEEE1801
Advanced Synthesis with Genus Innovus Clock Concurrent
Stylus Common UI Optimization Technology with
Stylus Common UI Conformal ECO
Modus DFT Software Solution

Joules™
Power Calculator

Virtuoso® Digital Implementation

Cadence® Cerebrus™ Intelligent Chip Explorer

Advanced
Advanced

New Course Number of days for instructor-led course Online Course Available Digital Badge Available © 2020 Cadence Design Systems, Inc.
 System Design and Verification Learning Map
Simulation, Coverage and Debug
Xcelium™ Simulator

Beginnr
Beginner

Beginner
Specman® Fundamentals for
Block-Level Environment
Developers
Cadence® RTL-To-GDSII Foundations of Metric-Driven
Flow Verification

VIP Basic Building Blocks and

Usage
Xcelium Integrated
Coverage

Low-Power Simulation with

CPF
Metric-Driven Verification Using Perspec™ System Verifier -
vManager™ Basic
Low-Power Simulation with
IEEE1801 UPF

vManager Tool Usage in Batch Xcelium Fault Simulator Specman Advanced Verification
Mode

Advanced
Advanced
Advanced

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2020 Cadence Design Systems, Inc.
 System Design
Learning Mapand Verification
Digital Learning
Design and SignoffMap
Design and Verification Languages
Beginner

Beginner
Verilog Language and Application VHDL Language and C++ Language Fundamentals
Application for Design and Verification

SystemC® Language
Real Modeling with Verilog Fundamentals
AMS SystemVerilog for Design and
Verification

SystemC Synthesis
Real Modeling with with Stratus HLS
SystemVerilog
UVM
SystemVerilog Assertions
Essential SystemVerilog for UVM SystemC Transaction-Level
SystemVerilog Real Number (optional) Modeling TLM2.0
Modeling (SV-RNM) Based
Advanced Verification SystemVerilog Accelerated
Verification Using UVM Jasper® Formal
Fundamentals
Perl for EDA Engineering

Tcl Scripting for EDA SystemVerilog Advanced Register Jasper® Formal Expert
Verification Using UVM

Advanced
Advanced

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2020 Cadence Design Systems, Inc.
 Tensilica
Learning Processor
Map IP Learning
Digital Design Map
and Signoff 1 of 2 – see next page

Tensilica Xtensa LX ConnX DSP Fusion & FloatingPoint HiFi Audio DSP Vision DSP
DSP
Tensilica® Xtensa® LX
Processor Fundamentals

Tensilica Xtensa LX Tensilica ConnX Tensilica Fusion F1 DSP Tensilica Audio Codec API Tensilica Vision DSP Family
Processor Interfaces BBE16EP Baseband
Engine

Tensilica Xtensa LX Tensilica ConnX Tensilica Fusion G3 DSP Tensilica HiFi 2/EP/Mini Tensilica Xtensa Neural
Hardware Verification and BBE32EP Baseband Audio Engine ISA Network Compiler v2
EDA Engine

Tensilica HiFi 3 Audio

Tensilica Instruction Tensilica ConnX Tensilica Fusion G6 DSP Engine ISA Tensilica DNA 100
Extension Language and BBE64EP Baseband Architecture and
Design Engine Programming
Tensilica HiFi 4 DSP
Tensilica System Tensilica ConnX 110 and Tensilica FloatingPoint
Modeling using XTSC 120 DSP Family DSP Family

Tensilica HiFi 5 DSP

Tensilica Xtensa Audio

Framework

New Course Number of days for instructor-led course Online Course Available © 2020 Cadence Design Systems, Inc.
 Tensilica
Learning Processor
Map IP Learning
Digital Design Map
and Signoff 2 of 2 – see prior page

Tensilica Xtensa NX ConnX DSP Vision DSP

Tensilica® Xtensa® NX
Processor Fundamentals

Tensilica Xtensa NX Tensilica ConnX B10 Tensilica Vision DSP Family

Processor Interfaces DSP

Tensilica Xtensa NX Tensilica ConnX B20 Tensilica Xtensa Neural

Hardware Verification and DSP Network Compiler v2
EDA

Tensilica Instruction
Extension Language and
Design

Tensilica System
Modeling using XTSC

New Course Number of days for instructor-led course Online Course Available © 2020 Cadence Design Systems, Inc.
 Computational
Learning Map DigitalFluid Dynamics
Design and Signoff
Fidelity Fine
Turbomachinery Meshing Auto Aero Marine
Beginner

Beginner
Fidelity Turbo: Introduction Fidelity Automesh for Fidelity Flow Fine Marine for Beginners
Unstructured Meshing

Fine Marine for Advanced Users

Advanced
Advanced

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available © 2020 Cadence Design Systems, Inc.
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