Learning Maps

Cadence Training Services learning maps provide a comprehensive visual overview of the
learning opportunities for Cadence customers. They provide recommended course flows as well
as tool experience and knowledge levels to guide students through a complete learning plan.
Learning Maps cover all Cadence® technologies and reference courses available worldwide.
For course names, descriptions, and schedules, please select the Browse Catalog button at
https://www.cadence.com/training.
Contents
• PCB Design and Analysis • System Design and Analysis • Computational Fluid Dynamics
• Custom IC, Analog, and RF Design • IC Package Design and Analysis
• Digital Design and Signoff • Tensilica® Processor IP
 Learning Mapand
PCB Design Digital Design
Analysis and Signoff
Learning Map
Logic Design PCB Design SI/PI Analysis Library Development

Beginner
Beginner

Allegro® Design Entry Allegro Design Entry Allegro PCB Editor Basic Essential High-Speed PCB Allegro PCB Librarian
HDL Front-to-Back Using OrCAD® Techniques Design for Signal Integrity
Flow Capture
PCB Design at RF – Multi-
Allegro Design Entry OrCAD CIS Allegro PCB Editor Allegro EDM PCB Librarian
Gigabit Transmission, EMI
HDL Intermediate Techniques
Control, and PCB Materials
Basics
OrCAD Capture
Constraint Manager Allegro PCB Router Basics
Allegro System Allegro Sigrity™ SI Foundations
PCB Flow
Capture
Allegro EDM Design Allegro Sigrity PI
Entry HDL Front-to- Allegro PCB Editor Advanced
Allegro System Methodologies
Back Flow Sigrity PowerDC™ and
Architect
OptimizePI™
Allegro Team Design
Authoring Allegro High-Speed Constraint
Allegro Design Reuse Sigrity Aurora
Management
Analog Simulation
with PSpice® SystemSI for Parallel Bus and Allegro Design Entry HDL SKILL®
Allegro DesignTrue DFM Serial Link Analysis Programming Language
Analog Simulation
Allegro AMS
with PSpice ® using
Simulator Allegro Update Training Model Generation and Analysis
System Capture
using PowerSI and Broadband Allegro PCB Editor SKILL
SPICE Programming Language
Advanced

Advanced
Allegro AMS Analog Simulation Advanced Design Verification
Simulator with PSpice Clarity 3D Solver
with the RAVEL Programming
Advanced Advanced Language Celsius Thermal Solver
Analysis Analysis
New Course Number of days for instructor-led course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning Design
IC Package Map Digital Design and
and Analysis SignoffMap
Learning

Beginner
Beginner

IC Package Design SI/PI Analysis

SiP Layout Allegro Sigrity™ SI Foundations

Allegro® Package Designer Allegro Sigrity PI

Allegro FPGA System Planner Sigrity PowerDC™ and OptimizePI™

Allegro Sigrity Package Assessment and Model Extraction SystemSI for Parallel Bus and Serial Link Analysis

OrbitIO™ System Planner Model Generation and Analysis using PowerSI and Broadband SPICE

Advanced Design Verification with the RAVEL Programming Clarity 3D Solver

Language
Advanced

Advanced
Allegro Package Designer Plus Celsius Thermal Solver

New Course Number of days for instructor-led course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Custom IC,Learning
Analog,Map Digital Design
Microwave and RFand Signoff
Design Learning Map 1 of 2 – see next page

Circuit Modeling, Analog/Mixed-Signal/RF Circuit Design and Simulation

Beginner
Beginner

Mixed-Signal Simulation Virtuoso Schematic Editor Spectre ® Simulator

Mixed-Signal Simulations using
Fundamentals Series
Spectre AMS Designer S1 Spectre Basics
Virtuoso Visualization and Analysis
S2 Large-Signal Analyses
Command-Line Based Mixed- S3 Small-Signal Analyses
Signal Simulations w/ Xcelium Virtuoso® ADE Explorer & Assembler Series
Use Model S4 Spectre MDL
S1 ADE Explorer & Single Test Corner Analysis
SimVision for Debugging Mixed-
Signal Simulations S2 ADE Assembler & Multi Test Corner Analysis
Design Checks and Asserts
S3 Sweeping Variables and Simulating Corners
AMS/Real Number Modeling High-Performance Spectre
S4 Monte Carlo, Real-Time Tuning & Run Plans Simulation (APS, Spectre X)
Analog Modeling with Verilog-A

Virtuoso® ADE Verifier Series Spectre FX Simulator

Behavioral Modeling with S1 Setup, Run, & View Verifier Results
Verilog AMS Virtuoso ® Spectre ® Pro Series
S2 Reference Flow and Analog Coverage Using the S1 DC Algorithm
Real Modeling with Setup Library Assistant
Verilog-AMS S2 Transient Algorithm
Microwave & RF Design (AWR ®)
Real Modeling with
SystemVerilog Microwave Office for RF Designers Spectre ® RF Series
RF Analysis Using Shooting
Advanced

Advanced
Newton
SystemVerilog Real Number 5G mmWave Handset System Design –
Modeling (SV-RNM) Based S1 Simulation and Verification of the RFIC RF Analysis Using Harmonic
Advanced Verification (Transceiver) Balance

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning
Custom Map Digital
IC, Analog and RFDesign
Designand Signoff Map
Learning 2 of 2 – see prior page

IC CAD Physical Design and Advanced Nodes Physical Verification

Beginner
Beginner

SKILL® Language Virtuoso® Layout Design Basics Virtuoso® Layout Pro Series Pegasus Quantus™
Programming T1: Env. and Basic Commands Verification Extraction
Introduction
System Solution
T2: Create and Edit Commands Transistor-Level
SKILL Language Virtuoso Connectivity-Driven Series
Programming Layout Transition T3: Basic Commands
Physical T1: Overview
E
Verification and Technology
T4: Advanced Commands
System Setup
SKILL Development
of Parameterized Virtuoso Abstract Generator T5: Interactive Routing
Cells
T2: Parasitic
T6: Constraint-Driven Flow
Extraction
Virtuoso Floorplanner and Power Routing
Advanced SKILL Physical
T7: Module Generator Verification
Language
and Floorplanner Language T3: Extracted
Programming
Rules-Writer View Flows
T8: Concurrent Layout Editing
Virtuoso® Advanced-Node – ICADVM E
and
Advanced
Virtuoso Layout for Advanced T9: Virtuoso Design Planner E
Features
Nodes

T1: Place and Route

T2: Electromigration
Advanced

Advanced
Virtuoso Layout for Advanced
Nodes and Methodology
Platform E

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning Map Digital
Digital Design Design
and Signoff and Signoff
Learning Map
Synthesis and Test Implementation Silicon Signoff Equivalence Checking

Beginner
Beginner

Digital IC Design Fundamentals

Cadence® RTL-to-GDSII Flow
Design For Test
Fundamentals of IEEE 1801 Low- Fundamentals
Power Specification
Format
Innovus Block Implementation Basic Static Timing Analysis
Genus™ Synthesis Solution with with Stylus Common UI Conformal® Equivalence
Stylus Common UI
Tempus™ Signoff Timing Checking
Innovus Hierarchical
Genus Low-Power Synthesis
Implementation with Stylus Analysis and Closure with Stylus Conformal Low-Power
Flow with IEEE 1801
Common UI Common UI Verification
Low-Power Synthesis Flow
with Genus Stylus Common UI Innovus Low-Power Flow with Voltus™ Power Grid Analysis Conformal Low-Power
Stylus Common UI and Signoff with Stylus Common Verification Using IEEE1801
UI
Test Synthesis with Genus Stylus Innovus Clock Concurrent
Common UI Optimization Technology with Conformal ECO
Advanced Synthesis with Genus Stylus Common UI
Stylus Common UI
Modus DFT Software Solution

Joules™ Power Calculator

Advanced

Advanced
Virtuoso® Digital Implementation

Artificial Intelligence and Machine Learning Fundamentals

Cadence® Cerebrus™ Intelligent Chip Explorer

New Course Number of days for instructor-led course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 System Design and Verification Learning Map
Simulation, Coverage and Debug

Beginner
Beginner
Beginnr

Digital IC Design Fundamentals Xcelium™ Simulator

Protium™ Introduction Specman® Fundamentals for

Block-Level Environment
Developers
Cadence® RTL-To-GDSII Foundations of Metric-Driven
Flow Verification Verisium™ Debug

VIP Basic Building Blocks and

Usage
Xcelium Integrated
Coverage

Low-Power Simulation with

CPF
Metric-Driven Verification Using Perspec™ System Verifier -
vManager™ Basic
Low-Power Simulation with
IEEE1801 UPF
Advanced

vManager Tool Usage in Batch Xcelium Fault Simulator Specman Advanced Verification
Advanced

Advanced
Mode

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning
System Mapand
Design Digital Design and
Verification SignoffMap
Learning
Design and Verification Languages

Beginner
Beginner

Verilog Language and Application VHDL Language and C++ Language Fundamentals
Application for Design and Verification

SystemC® Language
Real Modeling with Verilog Fundamentals
AMS SystemVerilog for Design and
Verification

SystemC Synthesis
Real Modeling with with Stratus HLS
SystemVerilog
UVM
SystemVerilog Assertions
Essential SystemVerilog for UVM SystemC Transaction-Level
SystemVerilog Real Number (optional) Modeling TLM2.0
Modeling (SV-RNM) Based
Advanced Verification SystemVerilog Accelerated
Verification Using UVM Jasper® Formal
Fundamentals
Perl for EDA Engineering
Advanced

Advanced
Tcl Scripting for EDA SystemVerilog Advanced Register Jasper® Formal Expert
Verification Using UVM

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning
Safety and Map DigitalPlatform
Reliability Design and Signoff
Learning Map
MIDAS Safety Platform

Beginner
Beginner

MIDAS™ Safety Platform Introduction

Midas™ Safety Analysis Authoring

Xcelium Fault Simulator

Functional Safety Implementation with

Midas™
Advanced

Advanced
New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available Digital Badge Available © 2023 Cadence Design Systems, Inc.
 Learning Map
Tensilica Digital Design
Processor and Signoff
IP Learning Map 1 of 2 – see next page

Tensilica Xtensa LX ConnX DSP Fusion & FloatingPoint HiFi Audio DSP Vision DSP
DSP
Tensilica® Xtensa® LX
Processor Fundamentals

Tensilica Xtensa LX Tensilica ConnX BBE16EP Tensilica Fusion F1 DSP Tensilica Audio Codec API Tensilica Vision DSP Family
Processor Interfaces Baseband Engine

Tensilica Xtensa LX Tensilica ConnX BBE32EP Tensilica Fusion G3 DSP Tensilica HiFi 2/EP/Mini Tensilica Xtensa Neural
Hardware Verification and Baseband Engine Audio Engine ISA Network Compiler v2
EDA

Tensilica HiFi 3 Audio

Tensilica Instruction Tensilica ConnX BBE64EP Tensilica Fusion G6 DSP Engine ISA Tensilica DNA 100
Extension Language and Baseband Engine Architecture and
Design Programming
Tensilica HiFi 4 DSP
Tensilica System Tensilica ConnX 110 and Tensilica FloatingPoint
Modeling using XTSC 120 DSP Family DSP Family

Tensilica HiFi 5 DSP

Tensilica Xtensa Audio

Framework

New Course Number of days for instructor-led course Online Course Available © 2020 Cadence Design Systems, Inc.
 Learning Map
Tensilica Digital Design
Processor and Signoff
IP Learning Map 2 of 2 – see prior page

Tensilica Xtensa NX ConnX DSP Vision DSP

Tensilica® Xtensa® NX
Processor Fundamentals

Tensilica Xtensa NX Tensilica ConnX B10 Tensilica Vision DSP Family

Processor Interfaces DSP

Tensilica Xtensa NX Tensilica ConnX B20 Tensilica Xtensa Neural

Hardware Verification and DSP Network Compiler v2
EDA

Tensilica Instruction
Extension Language and
Design

Tensilica System
Modeling using XTSC

New Course Number of days for instructor-led course Online Course Available © 2020 Cadence Design Systems, Inc.
 Learning Map DigitalFluid
Computational Design and Signoff
Dynamics

Beginner
Beginner

Fidelity Fine
Turbomachinery Meshing Auto Aero Marine

Fidelity Turbo: Introduction Fidelity Automesh for Fidelity Flow Fine Marine for Beginners
Unstructured Meshing

Fine Marine for Advanced Users

Advanced

Advanced
New Course Number of days for instructor-led course Online Course Available © 2023 Cadence Design Systems, Inc.
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