Experiment 5 FIR filter

1. The output y(n) of an L tap finite impulse response (FIR) filter for an input
x(n) is given as

y(n) = a0 · x(n) + a1 · x(n − 1) + . . . aL−1 · x(n − L + 1)

where a0 , a1 . . . aL−1 are the L filter coefficients and n is the time index.
2. Draw a neat hardware architecture diagram for an 8 tap FIR filter. Use the
following information
(a) Q4.12 fixed point representation for the 16 bit input/output samples.
(b) The 8 filter coefficients are a0 = −0.0841, a1 = −0.0567, a2 = 0.1826, a3 =
0.4086, a4 = 0.4086, a5 = 0.1826, a6 = −0.0567, a7 = −0.0841
3. Implement the hardware architecture using Verilog. To perform simulation,
read the input samples from the file “input.txt” uploaded.
4. Use MATLAB / Python to plot the input and output samples and verify the
Verilog simulation output.