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    This experiment aims to familiarize students with Verilog finite state machine (FSM) abstraction by designing a sequence detector FSM in Verilog. Students will implement a detector for the 1011 bit sequence using both FSM and structural descriptions in Verilog. A testbench will verify the designs by comparing outputs of the FSM model to the structural reference model. Students will then synthesize both designs and report the area and power usage of each.

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    This experiment aims to familiarize students with Verilog finite state machine (FSM) abstraction by designing a sequence detector FSM in Verilog. Students will implement a detector for the 1011 bit sequence using both FSM and structural descriptions in Verilog. A testbench will verify the designs by comparing outputs of the FSM model to the structural reference model. Students will then synthesize both designs and report the area and power usage of each.

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    © All Rights Reserved
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    11 views1 page

    Experiment 2 PDF

    Uploaded by

    ROOHA
    This experiment aims to familiarize students with Verilog finite state machine (FSM) abstraction by designing a sequence detector FSM in Verilog. Students will implement a detector for the 1011 bit sequence using both FSM and structural descriptions in Verilog. A testbench will verify the designs by comparing outputs of the FSM model to the structural reference model. Students will then synthesize both designs and report the area and power usage of each.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    Experiment 2: Sequence Detector

    • Objective:
    1. To become familier with Verilog FSM level of abstraction
    2. To implement a simple sequence detector FSM in Verilog and verify the design
    • Experimental procedure

    1. Design an FSM to detect the sequence 1011 in the incoming one bit input stream using Verilog FSM level of
    abstraction as well as Verilog structural description.
    2. Develop a simple testbench for verifying the DUT. You can use the structural description as the golden
    reference model and FSM level of abstraction as the DUT and compare both the outputs.
    3. Synthesize your designs and report the area and power for both the designs.

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