Experiment: 3 Nth Fibonacci Generator

Objective:

• To become familiar with the control flow in Verilog.

• To implement the Nth Fibonacci Generator in Verilog and verify the design

N valid Fibo valid

N N Fibo num
Fibonacci
Clock

Figure 1: Block Diagram

Experimental Procedure:

1. Design a digital block to compute the Nth fiboncacci number (where N is the given
input number). Implement the design in Verilog and develop a simple test bench
to verify the design. Take input N to be 3-bits, allocate sufficient number of bits
for the output. Input and output busues will have qualifiers N valid and Fibo valid
respectively.