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Question 1

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1. Convert the non-recursive digital signal processing system shown in Fig. 1 into an equivalent data-broadcast implementation (with
two broadcast lines, one for x1(n) and other for x2(n)) using cutset re-timing to improve the speed of the system. Comment on the
critical path of the original and retimed architectures. (4 marks)

2. For the IIR filter shown in Fig. 2, by assuming that the addition takes 1 nsec and multiplication takes 2 nsec, find out the iteration
bound and critical path. Retime the filter such that the critical path is reduced to 2 nsec. (4 marks).

3. Design a carry save array multiplier to multiply two 4-bit unsigned integers. Clearly explain the need for carry propagate adder at
the final stage. Comment on the critical path of the architecture. (4 marks)

4. Briefly explain the following (4x1 = 4 marks)

1. Fine grain pipelining

2. Loop bound and iteration bound

3. C-slow + Retiming
4. Unfolding

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5. Consider the N-stage normalized lattice filter in Fig. 3. Let N=25, i.e., the filter has 25 modules, and assume that the addition and
multiplication take 1 u.t and 2 u.t respectively. Compute the critical path for this filter. Using 2-slow transformation, retime the filter so
that it is pipelined at the module level, i.e., each wire between modules has at least one delay. What is the clock period and sample
period of the retimed filter? (4 marks)

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