TDA7439

Three-band digitally-controlled audio processor

Features
! Input multiplexer
– four stereo inputs
– selectable input gain for optimal adaptation
to different sources
( s )
! Single stereo output

u ct
! Treble, mid-range and bass control in 2-dB
steps
o
SDIP30d
! Volume control in 1-dB steps
P r
high-quality audio applications in car-radio and
Hi-Fi systems. Selectable input gain is provided.
! Two speaker attenuators:
– two independent speaker controls in 1-dB
e t e
All the functions are controlled by serial bus.
steps for balance facility
o l
The AC signal setting is obtained by resistor

!
– independent mute function
All functions are programmable via serial bus. b s
networks and switches combined with operational
amplifiers.

O
)-
The TDA7439 employs BIPOLAR/CMOS
Description technology to provide low distortion, low noise

t ( s
The TDA7439 is a volume, tone (bass, mid-range
and DC stepping.

u c
and treble) and balance (left/right) processor for

Table 1. Device summary

o d
P r
Order code Package Packaging
TDA7439

e t e SDIP30 Tube

o l
b s
O

March 2008 Rev 11 1/23

www.st.com 23
Contents TDA7439

Contents

1 Block diagram and pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Application suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Bass, mid-range stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.2
( s )
Treble stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
ct
Pin CREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
u
3.3
d
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
o
4 P r
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
e t e
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
o l
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 b s
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
- O
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5
(s )
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.6
c t
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

d u
5
r o
I2C bus transmission examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
e P No address incrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

l e t
5.2 Address incrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

o
6

Obs I2C bus addresses and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Chip address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Sub-address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3 Data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Chip input/output circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/23
 TDA7439 Block diagram and pin out

1 Block diagram and pin out

Figure 1. Block diagram

MUXOUTL INL TREBLE(L) MIN(L) MOUT(L) BIN(L) BOUT(L)

11 15 16 27 26 25 23 24
L-IN1
100K RM RB

12
L-IN2
100K

SPKR ATT 6
13 G VOLUME TREBLE MIDDLE BASS LOUT
L-IN3 LEFT

100K

L-IN4
14

( s )
ct
100K
30
0/30dB 2
SCL
2dB STEP I CBUS DECODER + LATCHES 1

du
10 SDA
R-IN1 29
DIG_GND
100K

R-IN2
9

r o
P
100K SPKR ATT 5
G VOLUME TREBLE MIDDLE BASS ROUT
RIGHT

e
8
R-IN3

t
VREF
100K

R-IN4
7
INPUT MULTIPLEXER

ol e RM RB
SUPPLY
3
4
VS
AGND

s
100K + GAIN

17
MUXOUTR

O
INR
b 18 28
TREBLE(R)
19 20
MIN(R) MOUT(R) BIN(R)
21 22
BOUT(R) CREF
2
D95AU342B

) -
Figure 2. Pin connections

c t (s
u
od
SDA 1 30 SCL

Pr
CREF 2 29 DIG_GND
VS 3 28 TREBLE(R)

e t e AGND 4 27 TREBLE(L)

l ROUT 5 26 MIN(L)

so
LOUT 6 25 MOUT(L)

O b R-IN4
R-IN3
7
8
24
23
BOUT(L)
BIN(L)
R-IN2 9 22 BOUT(R)
R-IN1 10 21 BIN(R)
L-IN1 11 20 MOUT(R)
L-IN2 12 19 MIN(R)
L-IN3 13 18 INR
L-IN4 14 17 MUXOUTR
MUXOUTL 15 16 INL
D95AU340A

3/23
Electrical specifications TDA7439

2 Electrical specifications

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VS Operating supply voltage 10.5 V

Tamb Operating ambient temperature 0 to 70 °C
Tstg Storage temperature range -55 to 150 °C

Table 3. Thermal data

Symbol Parameter Value

( s ) Unit

ct
Rth j-pin Thermal resistance junction-pins 85 °C/W

Table 4. Quick reference data

d u
o
Pr
Symbol Parameter Min Typ Max Unit

VS Supply voltage 6 9 10.2 V

e t e V
VCL Max. input signal handling

o l 2
RMS
THD
S/N b s
Total harmonic distortion V = 1 V RMS, f = 1 kHz
Signal to noise ratio Vout = 1 V RMS (mode = OFF)
0.01
106
0.1 %
dB
SC
-
Channel separation f = 1 kHz O 90 dB

)
t(s
Input gain (in 2-dB steps) 0 30 dB

u c
Volume control (in 1-dB steps)
Treble control (in 2-dB steps)
-47
-14
0
+14
dB
dB

o d
P r
Middle control (in 2-dB steps)
Bass control (in 2-dB steps)
-14
-14
+14
+14
dB
dB

e t e Balance control (in 1-dB steps) -79 0 dB

o l Mute attenuation 100 dB

b s Table 5. shows the electrical characteristics. Refer to the test circuit in Figure 3, Tamb =
25° C, VS = 9 V, RL= 10 kΩ, generator resistance Rg = 600 Ω, all controls flat (G = 0 dB),
O unless otherwise specified.

Table 5. Electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit

Supply
VS Supply voltage 6 9 10.2 V
IS Supply current 4 7 10 mA
SVR Ripple rejection 60 90 dB

4/23
 TDA7439 Electrical specifications

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit

Input stage
RIN Input resistance 70 100 130 kΩ
V
VCL Clipping level THD = 0.3% 2 2.5
RMS
The selected input is
SIN Input separation grounded through a 2.2 µF 80 100 dB
capacitor
Gin_min Minimum input gain -1 0 1 dB

(s)
Gin_max Maximum input gain 29 30 31 dB

ct
Gstep Step resolution 1.5 2 2.5 dB
Volume control

d u
Ri Volume control input resistance

r o
20 33 50 kΩ
Crange
Av_max
Volume control range
Max. attenuation
e P 45 47 49 dB

t
45 47 49 dB
Astep Step resolution

o l e 0.5 1 1.5 dB

bs
AV = 0 to -24 dB -1.0 0 1.0 dB
EA Attenuation set error
AV = -24 to -47 dB -1.5 0 1.5 dB

- O AV = 0 to -24 dB 0 1 dB
EΤ Tracking error

( s) AV = -24 to -47 dB 0 2 dB

VDC DC step
c t adjacent attenuation steps 0 3 mV

d u from 0 dB to Av_max 0.5 mV

o
Amute Mute attenuation 80 100 dB

r
Bass control
P
(1)

e t e Gb Control range Max. boost/cut ±12.0 ±14.0 ±16.0 dB

o l Bstep Step resolution 1 2 3 dB

b s RB Internal feedback resistance

Treble control (1)
33 44 55 kΩ

O Gt
Tstep
Control range
Step resolution
Max. boost/cut ±13.0 ±14.0 ±15.0
1 2 3
dB
dB
Mid-range control (1)

Gm Control range Max. boost/cut ±12.0 ±14.0 ±16.0 dB

Mstep Step resolution 1 2 3 dB
RM Internal feedback resistance 18.75 25 31.25 kΩ

5/23
Electrical specifications TDA7439

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit

Speaker attenuators
Crange Control range 70 76 82 dB
Sstep Step resolution 0.5 1 1.5 dB
AV = 0 to -20 dB -1.5 0 1.5 dB
E
A Attenuation set error
AV = -20 to -56 dB -2 0 2 dB
VDC DC step Adjacent attenuation steps 0 3 mV
Amute Mute attenuation 80 100 dB
Audio outputs

( s )
ct
VCLIP Clipping level d = 0.3% 2.1 2.6 Vrms

du
RL Output load resistance 2 kΩ

ro
RO Output impedance 10 40 70 Ω
VOUTDC DC voltage level

e P 3.5 3.8 4.1 V

General

l e
All gains = 0 dB;t µV
ENO Output noise
o
BW = 20 Hz to 20 kHz flat
s
5 15

Et Total tracking error

O b
AV = 0 to -24 dB
AV = -24 to -47 dB
0
0
1
2
dB
dB

) - All gains 0 dB,

(s
S/N Signal to noise ratio 95 106 dB
VO = 1 V RMS
SC
c t
Channel separation, left/right 80 100 dB

u
od
d Distortion AV = 0, VI = 1 V RMS 0.01 0.08 %

VIL
r
Bus input

P Input low voltage 1 V

e
let
VIH Input high voltage 3 V
µA

s o IIN Input current VIN = 0.4 V -5 0 5

Ob VO
Output voltage SDA
acknowledge
IO = 1.6 mA 0.4 0.8 V

1. For bass, mid-range and treble response: the center frequency and the response quality can be set by the
external circuitry.

6/23
 TDA7439 Electrical specifications

Figure 3. Test circuit

2.7K 5.6K
5.6nF
18nF 22nF 100nF 100nF
2.2µF

MIN(L)
MUXOUTL INL TREBLE(L) MOUT(L) BIN(L) BOUT(L)
L-IN1 11 15 16 27 26 25 23 24

0.47µF 100K RM RB

L-IN2 12

0.47µF 100K

SPKR ATT
L-IN3 13 G VOLUME TREBLE MIDDLE BASS LOUT
LEFT 6
0.47µF 100K

L-IN4 14

0.47µF 100K
30
0/30dB 2
SCL
2dB STEP I CBUS DECODER + LATCHES 1
R-IN1 10 SDA
29
DIGGND
0.47µF 100K

R-IN2

0.47µF
9

100K SPKR ATT 5

( s )
ct
G VOLUME TREBLE MIDDLE BASS ROUT
RIGHT
R-IN3 8
VREF
0.47µF 100K

R-IN4

0.47µF
7

100K
INPUT MULTIPLEXER RM RB SUPPLY

d u 3
4
VS

o
+ GAIN
AGND

r
17 18 28 19 20 21 22 2
MUXOUTR INR TREBLE(R) MOUT(R) BIN(R) BOUT(R) CREF

MIN(R)
2.2µF
18nF

e P
22nF 100nF 100nF

t
5.6nF 10µF
2.7K 5.6K D95AU339B

o l e
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

7/23
Application suggestions TDA7439

3 Application suggestions

The first and the last stages are volume control blocks. The control range is 0 to -47 dB and
mute for the first stage and 0 to -79 dB and mute for the last one. Both control blocks have a
step resolution of 1 dB.
This very high resolution allows the implementation of systems free from any noisy
acoustical effect.
The TDA7439 audio processor provides 3 bands of tone control (bass, mid-range and
treble).

3.1 Tone control

( s )
3.1.1 Bass, mid-range stages
uct
o d
The bass and the mid-range cells have the same structure.
However, the bass cell has an internal resistor RB of typically 44 kΩ whilst the mid-range cell
P r
has an internal resistor RM of typically 25 kΩ.

e te
Several filter types can be implemented by connecting external components to the bass/mid
IN and OUT pins.
o l
Typical responses are shown in Figure 8, Figure 9 and Figure 11.
b s
Figure 4. Bass/mid-range filter implementation
- O
(s )
t
Ri internal

u c IN OUT

od
C1 C2

P r R2

e te
l
D95AU313

o
bs
Figure 4. refers to the basic T-type band-pass filter. Starting from the filter component values
(R1 (internal) and R2, C1, C2 (external)) then the centre frequency fC, the gain Av at

O maximum boost and the filter Q factor are computed as follows:

1
f C = ----------------------------------------------------------------
-
2 ⋅ π ⋅ R1 ⋅ R2 ⋅ C1 ⋅ C2

+ R2C1 + RiC1-
A V = R2C2
-----------------------------------------------------------
R2C1 + R2C2

R1 ⋅ R2 ⋅ C1 ⋅ C2
Q = -------------------------------------------------
R2C1 + R2C2

8/23
 TDA7439 Application suggestions

Transposing and solving for the external component values we get:

AV – 1
C1 = -----------------------------------------
-
2 ⋅ π ⋅ Fc ⋅ Ri ⋅ Q

2
Q ⋅ C1 -
C2 = -----------------------------
2
AV – 1 – Q
2
AV – 1 – Q
R2 = ---------------------------------------------------------------------
-
2 ⋅ π ⋅ C1 ⋅ Fc ⋅ ( A V – 1 ) ⋅ Q

3.1.2 Treble stage

( s )
ct
The treble stage is a high-pass filter whose time constant is fixed by an internal resistor
(25 kΩ typically) and an external capacitor connected between treble pins and ground.
Typical responses are shown in Figure 10 and Figure 11.
d u
r o
3.2 Pin CREF
e P
The suggested value of 10 µF for the reference capacitor (CREF), connected to pin CREF,
l e t
can be reduced to 4.7 µF if the application requires faster power-on.
s o
3.3 Electrical characteristics O
b
) -
Figure 5.
t ( s
THD vs frequency Figure 6. THD vs RLOAD

u c
o d
P r
o l ete
b s
O

9/23
 Application suggestions TDA7439

Figure 7. Channel separation vs Figure 8. Bass filter response

frequency

( s )
u ct
Figure 9. Mid-range filter response
d
Figure 10. Treble filter response

o
P r
e t e
o l
b s
- O
(s )
c t
d u
Figure 11. Typical tone response

r o
e P
l e t
s o
O b

10/23
 TDA7439 I2C bus interface

4 I2C bus interface

Data transmission from the microprocessor to the TDA7439 and vice versa takes place
through the 2-wire I2C bus interface. This consists of the data and clock lines, SDA and SCL.
Pull-up resistors to the positive supply voltage must be used (there are no internal pull-ups).

4.1 Data validity

The data on the SDA line must be stable during the high period of the clock as shown in
Figure 12. SDA is allowed to change only when SCL is low.

( s )
ct
4.2 Start and stop conditions
u
As shown in Figure 13 a start condition is a high to low transition of SDA while SCL is high.
d
o
The stop condition is a low to high transition of SDA while SCL is high.
r
e P
4.3 Byte format
l e t
s o
Every byte transferred on the SDA line must contain 8 bits. The MSB is transferred first.
There is also provision for an acknowledge bit to follow each byte to indicate that the data
has been received.
O b
) -
(s
4.4 Acknowledge

c t
The master (µP) puts a resistive high level on SDA during the acknowledge clock pulse (see

d u
Figure 14). The peripheral (audio processor) that acknowledges has to pull down (low) the
SDA line during this clock pulse.

r o
P
The audio processor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the high level during the ninth
e
l e t
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.

s o
O b
4.5 Transmission without acknowledge
Suppressing the audio processor acknowledge detection enables the µP to use a simpler
transmission: it simply waits for one clock, without checking the slave acknowledging, and
then sends the new data.
This approach has, of course, less protection from transmission errors.

11/23
I2C bus interface TDA7439

Figure 12. Timing diagram of the data on the I2C bus

SCL

SDA

Data stable Data can change

when clock high when clock low

Figure 13. Timing diagram of the start/stop

( s )
ct
SCL

d u
SDA
r o
Start
e P Stop

Figure 14. Timing diagram of the acknowledge

l e t
s o
SCL 1 2
O b 6 7 8 9

) -
SDA

c tMSB
(s
d Start u Acknowledge
from receiver

r o
4.6
e P
Interface protocol
l e t
The interface protocol comprises:
o
bs
" a start condition (S)
" a chip-address byte, containing the TDA7439 address
O "
"
a sub-address byte including an auto address-increment bit
a sequence of data bytes (N bytes + acknowledge)
" a stop condition (P).

Figure 15. SDA addressing and data

CHIP ADDRESS SUBADDRESS DATA 1 to DATA n

MSB LSB MSB LSB MSB LSB

S 1 0 0 0 1 0 0 0 ACK X X X B DATA ACK DATA ACK P
D96AU420

S = Start, ACK = Acknowledge, B = Auto increment, P = Stop

12/23
TDA7439 I2C bus transmission examples

5 I2C bus transmission examples

5.1 No address incrementing

The TDA7439 receives a start condition followed by the correct chip address, then a sub
address with the bit B = 0 (for no address increment), then the data bytes to be sent to the
sub address and finally a stop condition.

Figure 16. SDA addressing and data for B = 0

CHIP ADDRESS SUBADDRESS DATA

S
MSB
1 0 0 0 1 0 0
LSB
0 ACK
MSB
X X X
LSB
0 D3 D2 D1 D0 ACK
MSB
DATA
LSB

(
ACK
s ) P
D96AU421

c t
d u
5.2 Address incrementing r o
e P
The TDA7439 receives a start condition followed by the correct chip address, then a sub

e t
ol
address with the B = 1 for address incrementing; now it is in a loop condition with an
automatic increase of the sub address up to D[3:0] = 0x7. That is, the data for sub
addresses from D[3:0] = 1000 (binary) to 1111 are ignored.
b s
In Figure 17 below, DATA1 is directed to the sub address sent (that is, D[3:0]), DATA2 is

-
directed to the sub address incremented by 1 (that is, 1 + D[3:0]) and so forth until a stop O
condition is received to terminate the transmission.

(s )
Figure 17. SDA addressing and data for B = 1
c t
u
od
CHIP ADDRESS SUBADDRESS DATA 1 to DATA n

Pr
MSB LSB MSB LSB MSB LSB
S 1 0 0 0 1 0 0 0 ACK X X X 1 D3 D2 D1 D0 ACK DATA ACK P

e t e D96AU422

ol
bs
Table 6. Power-on-reset conditions
Parameter POR value
O Input selection IN2
Input gain 28 dB
Volume MUTE
Bass 0 dB
Mid-range 2 dB
Treble 2 dB
Speaker MUTE

13/23
 I2C bus addresses and data TDA7439

6 I2C bus addresses and data

6.1 Chip address byte

The TDA7439 chip address is 0x88.

6.2 Sub-address byte

The function is selected by the 4-bit sub address as given in Table 7. The three MSBs are
not used and bit D4 selects address incrementing (B = 1) or single data byte (B = 0).

Table 7. Function selection: sub-address byte

( s )
MSB LSB

u ct
Function
D7 D6 D5 D4 D3 D2 D1 D0

o d
X
X
X
X
X
X
B
B
0
0
0
0
0
0
0
1 P r
Input selector
Input gain
X X X B 0 0 1
e t 0 eVolume
X X X B 0 0
o
1 l 1 Bass gain
X X X B 0 1
b s 0 0 Mid-range gain
X X X B 0

- O1 0 1 Treble gain
X X X B

(s )
0 1 1 0 Speaker attenuation, R
X X X

c t
B 0 1 1 1 Speaker attenuation, L

d u
6.3 Data bytes
r o
e P
The function value is changed by the data byte as given in the following tables, Table 8 to
Table 14.

l e t
In the tables of input gain, volume and attenuation, not all values are shown. A desired

s o intermediate value is obtained by setting the three LSBs to the appropriate value.

O b Table 8. Input selector value (sub address 0x0)

MSB LSB
Input multiplexer
D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X 0 0 IN4
X X X X X X 0 1 IN3
X X X X X X 1 0 IN2
X X X X X X 1 1 IN1

14/23
TDA7439 I2C bus addresses and data

Table 9. Input gain value (sub address 0x1)

MSB LSB Input gain
D7 D6 D5 D4 D3 D2 D1 D0 2-dB steps

X X X X 0 0 0 0 0 dB
X X X X 0 0 0 1 2 dB
X X X X 0 0 1 0 4 dB
X X X X 0 0 1 1 6 dB
X X X X 0 1 0 0 8 dB
X X X X 0 1 0 1 10 dB
X X X X 0 1 1 0 12 dB
( s )
X X X X 0 1 1 1
ct
14 dB

u
X X X X 1 0 0 0

o d 16 dB

Pr
X X X X 1 0 0 1 18 dB
X X X X 1 0 1 0 20 dB
X X X X 1 0 1
e
1
t e 22 dB
X X X X 1 1 0
o l 0 24 dB
X X X X 1 1
b s0 1 26 dB

-O
X X X X 1 1 1 0 28 dB
X X X X 1 1 1 1 30 dB

( s )
ct
Table 10. Volume value (sub address 0x2)

du
MSB LSB Volume

ro
D7 D6 D5 D4 D3 D2 D1 D0 1-dB steps

e P 0 0 0 0 0 0 0 0 dB

let
X 0 0 0 0 0 0 1 -1 dB
X 0 0 0 0 0 1 0 -2 dB

s o X 0 0 0 0 0 1 1 -3 dB

Ob X 0 0 0 0 1 0 0 -4 dB
X 0 0 0 0 1 0 1 -5 dB
X 0 0 0 0 1 1 0 -6 dB
X 0 0 0 0 1 1 1 -7 dB
X 0 0 0 1 0 0 0 -8 dB
X 0 0 1 0 0 0 0 -16 dB
X 0 0 1 1 0 0 0 -24 dB
X 0 1 0 0 0 0 0 -32 dB
X 0 1 0 1 0 0 0 -40 dB
X X 1 1 1 X X X MUTE

15/23
I2C bus addresses and data TDA7439

Table 11. Bass gain value (sub address 0x3)

MSB LSB Bass gain
D7 D6 D5 D4 D3 D2 D1 D0 2-dB steps

X X X X 0 0 0 0 -14 dB
X X X X 0 0 0 1 -12 dB
X X X X 0 0 1 0 -10 dB
X X X X 0 0 1 1 -8 dB
X X X X 0 1 0 0 -6 dB
X X X X 0 1 0 1 -4 dB
X X X X 0 1 1 0 -2 dB
( s )
X X X X X 1 1 1

u
0 dB
ct
X X X X 1 1 1 0

o d 2 dB

Pr
X X X X 1 1 0 1 4 dB
X X X X 1 1 0 0 6 dB
X X X X 1 0 1
e t1e 8 dB
X X X X 1 0 1
o l 0 10 dB
X X X X 1 0
b s0 1 12 dB

-O
X X X X 1 0 0 0 14 dB

Table 12.
)
Mid-range gain value (sub address 0x4)

( s
ct
MSB LSB Mid-range gain

du
D7 D6 D5 D4 D3 D2 D1 D0 2-dB steps

X
r oX X X 0 0 0 0 -14 dB
X

e P X X X 0 0 0 1 -12 dB

l e tX
X
X
X
X
X
X
X
0
0
0
0
1
1
0
1
-10 dB
-8 dB

s o X X X X 0 1 0 0 -6 dB

Ob X X X X 0 1 0 1 -4 dB
X X X X 0 1 1 0 -2 dB
X X X X X 1 1 1 0 dB
X X X X 1 1 1 0 2 dB
X X X X 1 1 0 1 4 dB
X X X X 1 1 0 0 6 dB
X X X X 1 0 1 1 8 dB
X X X X 1 0 1 0 10 dB
X X X X 1 0 0 1 12 dB
X X X X 1 0 0 0 14 dB

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TDA7439 I2C bus addresses and data

Table 13. Treble gain value (sub address 0x5)

MSB LSB Treble gain
D7 D6 D5 D4 D3 D2 D1 D0 2-dB steps

X X X X 0 0 0 0 -14 dB
X X X X 0 0 0 1 -12 dB
X X X X 0 0 1 0 -10 dB
X X X X 0 0 1 1 -8 dB
X X X X 0 1 0 0 -6 dB
X X X X 0 1 0 1 -4 dB
X X X X 0 1 1 0 -2d B
( s )
X X X X X 1 1 1

u ct
0 dB
X X X X 1 1 1 0

o d 2 dB

Pr
X X X X 1 1 0 1 4 dB
X X X X 1 1 0 0 6 dB
X X X X 1 0 1
e
1
t e 8 dB
X X X X 1 0 1
o l 0 10 dB
X X X X 1 0
b s0 1 12 dB

-O
X X X X 1 0 0 0 14 dB

Table 14.
)
Speaker attenuation value (sub address 0x6, 0x7)

( s
ct
MSB LSB Speaker attenuation

du
D7 D6 D5 D4 D3 D2 D1 D0 1-dB steps

X
r o
0 0 0 0 0 0 0 0 dB
X

e P 0 0 0 0 0 0 1 1 dB

l e t
X
X
0
0
0
0
0
0
0
0
0
0
1
1
0
1
2 dB
3 dB

s o X 0 0 0 0 1 0 0 4 dB

Ob X 0 0 0 0 1 0 1 5 dB
X 0 0 0 0 1 1 0 6 dB
X 0 0 0 0 1 1 1 7 dB
X 0 0 0 1 0 0 0 8 dB
X 0 0 1 0 0 0 0 16 dB
X 0 0 1 1 0 0 0 24 dB
X 0 1 0 0 0 0 0 32 dB
X 0 1 0 1 0 0 0 40 dB
X 0 1 1 0 0 0 0 48 dB
X 0 1 1 1 0 0 0 56 dB

17/23
 I2C bus addresses and data TDA7439

Table 14. Speaker attenuation value (sub address 0x6, 0x7) (continued)
MSB LSB Speaker attenuation
D7 D6 D5 D4 D3 D2 D1 D0 1-dB steps

X 1 0 0 0 0 0 0 64 dB
X 1 0 0 1 0 0 0 72 dB
X 1 1 1 1 X X X MUTE

( s )
u ct
o d
P r
e t e
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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 TDA7439 Chip input/output circuits

7 Chip input/output circuits

Figure 18. Pin 2 Figure 19. Pins 5, 6

VS

VS VS

ROUT 24
20K
LOUT
CREF

20K 20µA

( s )
ct
D96AU430

D96AU434

d u
Figure 20. Pins 7, 8, 9, 10, 11, 12, 13, 14 Figure 21. Pins 15, 17
r o
e P
let
VS VS VS

so
20µA 20µA

IN
O b MIXOUT

) -
(s
100K

VREF
c t D96AU425
GND
D96AU426

d u
r o
Figure 22. Pins 20, 25 Figure 23. Pins 19, 26

e P
l e t VS VS

s o 20µA 20µA

O b
25K 25K
MOUT(L) MIN(L)
MOUT(R) D96AU431 MIN(R) D96AU431

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Chip input/output circuits TDA7439

Figure 24. Pins 21, 23 Figure 25. Pins 22, 24

VS
VS

20µA
20µA

44K
44K
BOUT(L)
BIN(L)
BOUT(R) D96AU429

)
BIN(R) D96AU428

( s
ct
Figure 26. Pins 27, 28 Figure 27. Pin 30

d u
VS

r o
20µA

e P 20µA

TREBLE(L)

l e t SCL

o
TREBLE(R)
50K

b s
-
D96AU433
O D96AU424

(s )
Figure 28. Pin 1

u ct Figure 29. Pins 16, 18

o d VS

P r 20µA
20µA

e te INL

l
SDA

o INR

bs
33K

O D96AU423

VREF
D96AU427

20/23
 TDA7439 Package information

8 Package information

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

mm inch
DIM. OUTLINE AND data
MIN. TYP. MAX. MIN. TYP. MAX.
Outline and mechanical
MECHANICAL DATA

( s )
ct
A 5.08 0.20

u
A1 0.51 0.020

A2 3.05 3.81 4.57 0.12 0.15 0.18

o d
B

B1
0.36

0.76
0.46

0.99
0.56

1.40
0.014

0.030
0.018

0.039
0.022

0.055
P r
C 0.20 0.25 0.36 0.008 0.01 0.014

e te
D 27.43 27.94 28.45 1.08 1.10 1.12

o l
E

E1
10.16

8.38
10.41

8.64
11.05

9.40
0.400

0.330
0.410

0.340
b s
0.435

0.370

e 1.778

-
0.070
O
e1

L 2.54
10.16

3.30 3.81
(s )0.10
0.400

0.13 0.15

M
c t 0°(min.), 15°(max.)
SDIP30(0.400
SDIP30 (0.400")
in.)
S

d
0.31
u 0.012

r o
e P
l e t
s o
O b

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 Revision history TDA7439

9 Revision history

Table 15. Document revision history

Date Revision Changes

Jan-2004 9 Initial release in EDOCS DMS

Jun-2004 10 Modified presentation
Updated titles to Figure 9 and Figure 10
21-Mar-2008 11
Minor updates to presentation

( s )
uct
o d
P r
e te
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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 TDA7439

Please Read Carefully:

( s )
u ct
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.

o d
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