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Abstract-Scan chain failure analysis is more difficult and used. It is very important to have ability ofscan failure diagnosis
complicated compared to memory analysis and analysis of defect because scan failure is one of the highest yield loss. [6] Since
monitoring test element group (DTEG) which has a large area is scan failure needs not only a process of extracting electrical nets
also difficult. This paper has verified that various defects of logic of electrical defect position but also tracing of position of
process sub 6Snm device are easily analyzed through Resistive
Contrast Imaging (RCI) and nanoprobe. In addition, MetalS (MS)
physical defect, ability of defect analysis by using nanoprobe
bridge defect (Short case) was detected in failure of scan ATPG and electron beam of RCI (EBAC, Hitachi) was improved on
(Automatic Test Pattern Generation) which has long failing nets this work. The purpose of this paper is to investigate EBAC
and by discovering Via4 (V4) open defect (Open case) by Unetch, condition using RCI method through tests regarding each defect
it was confirmed that it is possible to analyze high resistance Via and to find out a new failure analysis method of BEOL.
failure. And it was verified that position of Cu line void of metal7 (Back-end of Line) sub 65nm process.
(M7) can be localized at high level metal layer. It is judged that it
will be used usefully in failure analysis sub 6Snm in the future as a II. EXPERIMENTAL METHOD
technique utilizing principle of RCI and nanoprobe and also it will
make lots of contributions to improvement of yield
Measurement specimen has used scan ATPG failure
(Sample 1, Sample2), where defect was generated in
I. INTRODUCTION
combinational logic connected to scan flip-flop , and open
defect sample ofDTEG (Sample 3) as device less than 65nm. In
Recently, device failure analysis becomes difficult gradually
case of scan failure, long failing nets which was difficult to
as device scaling becomes smaller and especially, it is necessary
apply SEM inspection that was an existing failure analysis
to research on methods finding out accurately failure
method, was selected and in case ofDTEG, M7 open defect was
localization in logic circuit having complicate layout & circuit,
selected. After de-processing up to metal step which will probe
multi layer structure, long nets, and low via height. For defect
in a physical lapping method, it was probed using nanoprobe
analysis in this time, principle of RCI (Resistive Contrast
(N-6000, Hitachi) in metal level and DTEG has probed meta18
Imaging) was investigated and EBAC (Electron beam absorbed
(M8) pad. After transforming into EBAC mode for RCI,
current, Hitachi) equipment was used. RCI is a scanning
optimum condition was found out per each defect by using
electron microscopy (SEM) imaging mode that generates a
Acceleration voltage (Vacc, 0-30keV), Beam current (0-30uA),
relative resistance map between metal interconnect of CMOS
Condenser lens (0-9), and Aperture lens(1-4). After localizing
device or test structure (Fig.I) . RCI generates absorbed current
points of occurrences of defects alongside of metal line by
imaging as a current divider to visualize metal interconnecting
comparing to normal highlighted layout using EBAC reaction
LSI chip for open and resistance failure analysis. [1-5]
image and CAD navigation software, physical analysis was
carried out with SEM (S-4800, Hitachi) and TEM. (Technica,
EI. ella n Bum Amplln. r FEI)
o III. CASE STUDIES
1 GtID
A. Scan ATPG Failure (Short)
It was extracted failure analysis candidates by processing
diagnosis using ATPG tool after carrying out wafer level test.
As the result of confirming log data of failure analysis
candidates, it was confirmed that sample 1 was a systematic
defect which most of dies have same failure nets. Fig. 2 is the
result of highlighting nets using CAD navigation software and
as length of net was over 1500um and was a total of 6 metals
Fig. I Principle of open failure site detection using RCI with nanoprobe [4]
from metal 1 to meta16. SEM inspection, which is an traditional
method, was difficult and as IDS failure was not accompanied, it
Microelectronic device composes scan chains connected could not localize failure point with emission equipment.
with registers within logic block and a test method with ATPG is
Fig. 2 Layout image showing the suspected failing nets for sample I
Fig. 5 Layout image showing the suspected failing net for sample2
Fig. 3 EBAC reaction image of the failing net for samplel . Unexpected net
connected to the suspected failing net
Fig. 6 EBAC reaction image of the failing net for sample2
Fig. 4 SEM picture showing Metal bridge at metal5 . Fig. 7 TEM cross-section picture showing Via open at Via4
Fig. 8 EBAC reaction image of the DTEG for sample3 Fig. II SEM picture showing Metal Oxide Bridge at MI.
IV. CONCLUSION