EOS/ESD in IC Manufacturing Process of GQFN 64L

Devices

Bernard Chin (1), L.H. Koh (2)

(1) UTAC Headquarters Pte Ltd, 22 Ang Mo Kio Industrial Park 2, Singapore 569506.
Phone: (65) 6213-6153, Fax (65) 6551-1222 Email: bernard_chin@utacgroup.com
(2) Everfeed Technology Pte Ltd, 2 Tuas Link 1, Singapore 638590
Phone: +65 68631488, Fax: +65 68630488 Email: marcus_koh@everfeed.com.sg

50 Words Abstract – This paper presents a case study of ESD/EOS events causing low yield in trial lots prior to
the release of volume production. The use of line ESD audits to check for static charge, grounding and CDM
events, voltage spike check and split-lot testing were used to determine the root cause.

I. Introduction both region C and region D are both in high probability

of immediately damage, which will lead the analysis as
Low yield lots were found in Grid Array Quad Flat No- EIPD. Only if there was objective evidence(s)
Lead (GQFN) 64L trial lots manufactured prior to determining the root cause(s), then the quantitative
release to volume production. Failure analysis of the analysis will change from EIPD to EOS.
failing parts showed different failure modes ranging
from parts showing no visual defect (NVD), to parts
A split-lot assessment was then finally implemented to
indicating ESD-related damage (ESD) and to parts
determine and confirm the root cause of the failures [3].
showing electrical over-stress (EOS) like damage or
electrically induced physical damage (EIPD).

An ESD audit was then conducted on the equipment

and electrostatic discharge protected areas (EPAs) used
in this manufacturing process to determine if static
voltages were in compliance with guidelines specified
by the customer and ANSI/ESD S20.20 standards [1].
The compliance verification for proper grounding and
ESD control materials related to the pick and place
processes were also carried out to determine if there Figure 1 Absolute maximum rating against probability of
were any deviations from requirements that could immediate damage
cause ESD/EOS events, as per ANSI/ESD SP10.1
automated handling equipment. II. Measurement Techniques
A. General Observations
As test voltages above the absolute maximum voltage
These were nine failure analytic techniques applied in
ratings (AMR) could also potentially lead to EOS the process leading to objective evidence analysis in
events that result in damage on the dies. Hence, voltage
bin 3 and bin 4 with ten devices each. The failure
spike measurements were also carried out to assess if analysis techniques include automated test equipment
there were any voltage spikes anomalies. Figure 1 from (ATE) testing, external visual inspection (EVI), X-ray,
Industry Council white paper 4, showed the ESD
C-model scanning acoustic microscopy (CSAM),
sensitive devices (ESDSs) to have entered region C curve tracer, internal visual, liquid crystal analysis
(exceeding absolute maximum rating with high risk of
(LCA), emission microscopy (EMMI) and de-process,
latent damage) and region D (immediate damage) with as shown in Table 1 and Table 2.
high probability of immediate damage [2]. Note that

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 a. No visual defect (NVD)
B. ANSI/ESD S20.20 ESD Audit b. ESD failures
The fundamental principles of ANSI/ESD S20.20 were c. EIPD / EOS failures
applied in the factory by combing through all the ESD
sensitive devices (ESDS) critical paths in the process
to identify resistance to ground, electrostatic voltage of B. Procedure Manufacturing Process
ESDS and within 12” vicinity of ESDS work bench (6” Audit
within automated handling equipment), charges on
ESDS (both static and dynamic) and ESD events. The
A detailed ANSI/ESD S20.20 compliance
product qualification of EPA technical elements were verification and ESD audit was performed on the
studied and checked against ANSI/ESD S20.20 manufacturing process, as illustrated in Figure 2.
technical requirements.

Finally, all compliance verification records in file were

reviewed and validated via a detailed ESD audit on the
manufacturing process.

C. AMR Testing
The AMR of an ESDS is the maximum limits for
voltage, current and allowed power. Hence, AMR is the
point where beyond the ESDS has high probability of
immediate damage, as shown in Figure 1. Hence, the
ESDS samples under test were put in the ATE to study
objectively at each pin, if there were voltage spikes at
or exceeding AMR.

D. Split Lot Test Evaluation

Though there were some literature written by vendors
on the challenges in assessing charge in deionized
water (DI) operationally, the ESD team was not fully
convinced if the reported measurement techniques
would be helpful for the assessment. Hence, a manual
experiment was designed and setup to aid the
assessment objectively, named split lot test evaluation.
Two levels of DI water resistivity were pre-determined
so that two different lots of ESDS samples can be
assessed in different time sequence. Then the nine
different failure analysis techniques described in II(A)
were applied to determine which DI water resistivity
level yielded better results.

III. Failure Analysis Results

Failure analysis was performed on the failing ESDS
units. The following results were obtained from the 20
units that were analyzed:
Figure 2 Analysis of the manufacturing process flow
A. Failure Analysis Results
From the results obtained, it was found that there were
From the results obtained, there was a mix of failure some processes that needed further investigation.
modes. The failure modes were: Though some technical elements in the processes had

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high static voltage levels and did not meet ANSI/ESD
S20.20 without ionization, these processes were under
control as ionization had already been implemented
with rigorous compliance verification.
The results of the manufacturing process audit
indicated that the electrical test program required an
analysis for voltage spikes. The Wash Process after
package singulation also required further investigation
C. Voltage spike test
As test voltages above the AMR ratings could also
potentially cause damage to the die and result in EOS
events, voltage spike measurements were done to
assess if there were any voltage spikes induced by the
test program during ATE testing.
Figure 3 Voltage spike showing voltage spike exceeding AMR for
the device
It was found that voltage spikes that exceeded the AMR
for this device were present up to 15.3 volts, as shown
in Figure 3. The results were fed back to the customer
and a new revision of the test program was introduced.
Though the test yield improved, it was erratic and still
did not meet the target test yield requirement that was
set. Further investigation had to be done.
D. Split Lot Test Evaluation
As the wash process was the only process in the whole
manufacturing line that the ESD audit team could not
measure the static voltage dynamically, a split lot test
evaluation was done by running two lots using two
different resistivity of deionized (DI) water.
The test yield results of the evaluation indicated that
ESDS units processed with DI water at a lower
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resistivity produced a better test yield than the units
processed under a higher water resistivity. It was then
postulated that a higher water resistivity could
potentially cause ESD damage to the devices.
IV. Discussion of Results
The ANSI/ESD S20.20 ESD audit had identified some
technical elements and EPA issues within the ESDS
critical paths, which required some mitigation.
However, these were minor issues which has low
probability attributing to the EIPD issues. The results
of the mitigation effective closed ESD audit findings.
The results of the audit on the manufacturing process,
voltage spike test and split lot test evaluation indicated
that the units could possibly be damaged during the
washing process. Damaged units were then further
subjected to further electrical stress during ATE testing
which resulted in ESD or EIPD failures, depending on
the initial damage experienced during the wash
process. The nine different failure analysis techniques
in II(A) assisted in making objective evidences of
ESDS failure. Hence, the ESDS samples under test
were leading the conclusion from EIPD to EOS
damage.
A. Corrective Action and
Verification
A re-design was done on the lead frame of the device
so that all leads would still be connected together, like
a guard ring, during the washing process. The guard
ring would provide an equi-potential bonding for all
leads and mitigate ESD events in the preliminary
process steps. The leads of the device would then be
trimmed and formed at a subsequent process.
A verification test was then implemented using DI
water with the original water resistivity. Results from
the verification test indicated good test yields could be
obtained from the devices using the new lead frame
design.
V. Conclusion
This paper has presented a case where ESDS failures
caused by the same root cause could manifest in
multiple failure modes (NVD, ESD and EIPD). The
failure mode depended on the severity of the initial
damage to the device during the washing process which
was then exacerbated during ATE testing due to [2] I. C. Members, "Industry Council white paper 4
voltage spikes. revision 1.2, August 2016," Industry
Council2016.
Customer responsiveness to improve on the test [3] ASM Handbook Volume 11: Failure Analysis and
program resulted in the elimination of voltage spikes, Prevention, 2002.
and this was part of the corrective action plan in this
case.

Figure 4 Modified manufacturing process flow

A re-design of the lead frame to ensure equi-potential

bonding on the leads of the device was also introduced
and then tested, as shown in Figure 4. It was found to
be a suitable solution to resolve the ESD/EOS failures
without changing the manufacturing process
parameters.

In the absences of objective evidence in the failure

analysis, the ESDS failure should be classified as
EIPD. If and only if there is objective evidence(s)
identifying the root cause(s), then the ESDS failure can
be classified as EOS damage.

Acknowledgements
We would like to acknowledge the following people
for their assistance:
• Ekalak Klubkong, Chakrit Homnan & the
UTAC Thailand teams for carrying out the
experiments and verification runs
• Jeremy Ong for conducting the manufacturing
process audit and summarizing the results
• UTAC Headquarters FA team for performing
the failure analysis

References
[1] ANSI/ESD S20.20-2014, 2014.

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 Table 1. Summary of Failure Analysis results of 10 Bin 3 units analysed

Table 2. Summary of Failure Analysis results of 10 Bin 4 units analysed

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