Discussion Question:

In CSC340L, we are learning a new design tool along with a

hardware design language – Verilog. Our weekly discussion
topics therefore are designed to be a series of tutorials: each
week, you will be given a list of specific aspects of the ISE
Design Suite or Verilog, out of which you will choose 1 to focus
on and write a 250 – 500 word summary/tutorial to share with
the class.  In your reply posting, you will choose one of the
initial postings from our class to provide a 125 – 250 word
feedback (i.e., how easy it is to follow the postings, any missing
steps, how it helps you to understand the materials better, etc.)

For this week, please choose from the following topics:

1. Design a testbench for a 3 input XOR gate a xor b xor c,

explain what is to be expected in the test bench waveform.

2. Explain the syntax of always and initial blocks in details and

give an example of each.

3. Similarity and differences between Verilog and a software

programming language such as C.

ANSWER:

My Week-3 Discussion topic is the: “Similarity and

differences between Verilog and a software programming
language such as C.” As we learned in Week-1, Verilog is a
language the enables our design and verification of digital
circuits. With that, there are similarities and differences.
The biggest difference between the two is: Verilog is
established as a “hardware description” language; whereas, “C”
is more of a high level GP (general purpose) programming
language. Additionally, Verilog is used to describe hardware
component behavior that is executed in a digital circuit; and C is
only executed via computer (or on a processor). Finally, it
seems a lot harder to trouble-shot bugs in Verilog coding versus
C code (mainly due to more complex testing with that digital
circuit’s behavior).
In terms of the key similarities, there are at least three. First,
Verilog and C are both used to support broad area of data types.
That includes things like arrays, floating-point numbers and
integers. Second, Common Literals and Structures are available
for both languages. Third, both Verilog and C have elements to
connect to an operating system and assign tasks.
The bottom-line here is that although they share similarities
(above), they are fundamentally different. Those differences are
clear when we see that in C or C++ we have basic data
structures (i.e., an array, integer, string, etc.); however, in
Verilog, we see Flip Flops, Switches, and Gates. That means we
use the two languages based on need: the requirement or task
will determine use.
Best,
Dan