COMPUTER ARCHITECTURE

Dr. Nguyen Hong Son

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 Opening words
 Plan
 Requirements
 Resources
 Contact information

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 Textbooks
1.William Stallings, Computer Organization and Architecture:
Designing for Performance, 10th Edition, Prentice Hall International,
Inc, 2016
2. Miles Murdocca and Vincent Heuring, Principles of Computer
Architecture, Prentice Hall; US Ed edition, 2000

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 Lesson 1
INTRODUCTION

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 Organization and Architecture
Two terms for describing computers:
 Computer architecture refers to those attributes of a
system visible to a programmer, those attributes that have
a direct impact on the logical execution of a program
(Instruction set, number of bits of data type, I/O
mechanisms, addressing)
 Computer organization refers to the operational units and
their interconnections that realize the architectural
specifications (hardware details, control signals,
interfaces, memory technology)
 Example: to build the multiply instruction
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 Structure and Function
 Contemporary computers contain millions of elementary
electronic components.
 Structure: The way in which the components are
interrelated.
 Function: The operation of each individual component as
part of the structure.

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Main Functions
 Data processing
 Data storage
 Data movement (I/O, peripheral, communication)
 Control

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 External environment

Data movement
apparatus

Control
mechanism

Data storage Data processing

facility facility

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 Main structural components
There are four main structural components:
■ Central processing unit (CPU)
■ Main memory
■ I/O
■ System interconnection

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 Computer

Communication lines

CPU
Peripherals Main
memory
System
Interconnection

Computer
I/O

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Main structural components…
 A computers may have multiple CPU
 The size of memory can be changed
 I/O mechanisms depend on requirements

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 Main structural components…
The most complex component is CPU


 Control unit
ALU (Arithmetic and Logic Unit)
Register
CPU Interconnection

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 Control
unit
CPU

Sequencing
Control unit
ALU logic Control Unit
Regisers
CPU bus vaø Decoders

Conrol
Registers
memory

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A brief history of computers

3000 BC
4000 BC
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 A brief history of computers …
 The first generation of computers :
 Used vacuum tubes for digital logic elements and
memory
 ENIAC
 Von Neumann/ Alan Turing

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ENIAC Computer 17
 A brief history of computers: ENIAC
-ENIAC(Electronic Numerical Integrator And Computer): the world’s first
general purpose electronic digital computer.
-Designed and constructed at the University of Pennsylvania by Professors
John Mauchly and John Eckert, start 1943, done 1946, ended 1955.
-30 tons;1500 square feet of floor space; 18,000+ vacuum tubes; 140kwh;
capable of 5000 additions per second
-The ENIAC was a decimal rather than a binary machine
-The major drawback of the ENIAC was that it had to be programmed
manually by setting switches and plugging and unplugging cables
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 A brief history of computers…
 The Second Generation
 Transistor
 Multiplexor

 High-level programming

languages, system software

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Mouse (1964)

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A brief history of computers…
 The Third Generation
 Integrated Circuits
 SSI, MSI
 Microelectronics
 IBM/360, PDP-8( fisrt minicomputer, using bus)
 Moore’s law
Ref 12/2022: https://www.intel.com/content/www/us/en/history/virtual-
vault/articles/moores-law.html

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 A brief history of computers…
 Later Generations:
 LSI, VLSI, ULSI
 Semiconductor Memory
 Microprocessor

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Evolution of Intel Microprocessors

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Evolution of Intel Microprocessors…

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Transistor innovations over time

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Package innovations over time

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Pentium®III architecture

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Pentium®IV

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Intel Core 2 Dual

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Chip Technology

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Design for performance
 Microprocessor speed
 Branch prediction
 Data flow analysis
 Speculative execution
 Performance Balance
 Improvements in Chip Organization and
Architecture.

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Processor Trend

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Typical I/O Device Data Rates

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 Lesson 2
GENERAL-PURPOSE COMPUTER
and STORED-PROGRAM

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 General-Purpose Hardware
 A small set of basic logic components can be
combined in various ways to store binary data and
perform arithmetic and logical operations on that
data.
 A configuration of logic components designed
specifically for a computation could be constructed.
 The process of connecting the various components in
the desired configuration as a form of programming

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 Hardware is built from basic logic
components for a specific computation

Sequence of
Data arithmetic and logic Results
functions

Hardwired programming
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 General-Purpose Hardware
 Hardwired program: inconvenience

 Idea: building a general-purpose hardware

 GP hardware works based on sets of control signals

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 General-Purpose Computer (GPC)

Instruction codes

Instruction
interpreter

Control signals

General-purpose
Data arithmetic Results
and logic
functions
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 Generating control signals
 The entire program is a multi-step sequence.
 Each step requires a certain number of arithmetic and
logical operations.
 Each step requires a corresponding set of control signals
 An instruction code for each signal set accepted by GPC
 GPC was designed for accepting specific sets of control
signals

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 Generating control signals…
 Programming: no longer wired for hardware, instead, a
sequence of codes for new programs is written
 Each code is an instruction that is passed to the interpreter for
generating a corresponding signal set.
 The sequence of codes is software

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 Stored-program concept
 ENIAC: The task of entering and altering programs was
extremely tedious.
 Idea:
 The programming process could be facilitated if the
program could be represented in a form suitable for
storing in memory alongside the data.
 Then, a computer could get its instructions by reading
them from memory, and a program could be set or
altered by setting the values of a portion of memory.
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 Stored-program concept…
 Data and instruction are stored in the same memory that
can be read and written.
 The content stored in memory is located by the storage
location, no matter what the data type is.
 The program is executed sequentially, from one
instruction to the next according to the logic of the
program.

What is the important thing behind the stored-program concept?

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 Lesson 3

JOHN VON NEUMANN ARCHITECTURE

AND HARVARD ARCHITECTURE

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 JOHN VON NEUMANN ARCHITECTURE

 ENIAC (Electronic Numerical Integrator And Computer) was the

first general-purpose computer.
 The task of entering and altering programs for the ENIAC was
extremely tedious
 Based on the idea stored-program concept, 1946 John von Neumann
began to design a new stored-program computer, referred to as the
IAS computer (at the Princeton Institute for Advanced Studies),
completed in 1952.
 IAS is the prototype of all subsequent general-purpose computers.

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45
 Structure of the IAS computer
Central Processing Unit (CPU)

ALU

Main I/O
Memory
Program
Control
Unit (PCU)

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 Structure of the IAS computer
 A main memory, which stores both data and instructions
 An arithmetic and logic unit (ALU) capable of operating on binary data
 A control unit, which interprets the instructions in memory and causes
them to be executed
 Input and output (I/O) equipment operated by the control unit

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 IAS computer architecture…
 The memory of the IAS consists of 1000 storage locations, called words,
of 40 binary digits (bits) each
 Numbers are represented in binary form, and each instruction is a binary
code
 Each number is represented by a sign bit and a 39-bit value.
 A word may also contain two 20-bit instructions,
 An instruction consisting of an 8-bit operation code (opcode) specifying
the operation to be performed and a 12-bit address designating one of
the words in memory (numbered from 0 to 999)

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 IAS computer architecture…

0 1 39
Value
Sign
Number word
bit

Left instruction Right instruction

0 7 8 19 20 28 39

Op code addr Op code addr

Instruction word

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 Central Processing Unit
Expanded Structure of IAS Computer
ALU
AC MQ

Arithmetic-logic
circuits
I/O

MBR

MBR (Memory Buffer Register)

Instructions and Data
MAR(Memory Address Register)

IBR PC IR (Instruction Register)

Main IBR (Instruction Buffer Register)
memory
PC (Program Counter)
IR MAR
AC&MQ(Accumulation&

Multiplier-Quotient)
Address
Control
circuits : control signals

Program Control Unit

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 IAS computer architecture…
 The control unit operates the IAS by fetching instructions from
memory and executing them one at a time.
 Both the control unit and the ALU contain storage locations, called
registers, defined as follows:
 MBR (Memory Buffer Register)
 MAR (Memory Address Register)
 IR (Instruction Register)
 IBR (Instruction Buffer Register)
 PC (Program Counter)
 AC&MQ (Accumulation & Multiplier-Quotient)

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Principle of auto program execution
 What is the core of program execution?
 A program is loaded into a memory space before running
 Each instruction code occupies a memory location with a
specific address
 PC is filled with the address of the first instruction code
 Auto running

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 start

y Is next n
instruction MAR PC
in IBR?

MBRM(MAR)

Fetch
IBRMBR(20:39)
cycle IRIBR(0:7) IRMBR(20:27) n Left y IRMBR(0:7)
MARIBR(8:19) MARMBR(28:39)
instruction MARMBR(8:19)
required?

PCPC+1
Decode instruction in IR
ACM(X) Goto M(X,0:19) then
If AC 0 ACAC+M(X)
goto M(X,0:19

AC0?
y
Execution
cycle MBRM(MAR) PCMAR MBRM(MAR)
n
ACMBR ACAC+MBR

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The IAS Instruction Set

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 Harvard Architecture
 Harvard architecture consists of Arithmetic Logic Unit, Control Unit, Data
memory, Instruction memory, and Input/Output.
 It adopts stored-program concept
 It has separate memory and separate buses (signal path) for data and
instructions.
 Instructions are used in read-only memory and, data are used in read-
write memory.
 CPU can access instructions and read/write data at the same time.
 The instruction bus width can be dynamically changed to optimize for a
particular device. The data bus is usually 8 bits or 16 bits wide.

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Structure of the Harvard computer

Address
Data memory
PC
Data

Address CPU
Instruction memory
Instruction

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 Pros and Cons
 A long word instruction occupies a storage location only
 Single-word instructions can speed up the execution owing to
opcode and related data contained in one word.
 DSP(Digital Signal Processor) uses Harvard architecture
 Multiple CPUs use a fusion of the two architectures, inside the core
use Harvard architecture.
 The core has been cached from an external bus by a high-speed
cache and a cache controller.
 For improvement of performance, inside the core has a separate bus
for data and instructions and a separate cache for each bus.
 No self-modifying code

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The End

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