CHAPTER ONE

1. NUMBER SYSTEMS
This is a mathematical notation for representing numbers of a given set using digits or
other symbols in a consistent manner. Digital refers to a process that is achieved using a
discrete unit. Digital systems information such as data, address and instructions are
represented using numbers. In number systems, there are different symbols used and each
symbol has an integer value and a fractional value. The base or radix of a number system
is the number of different digits which can occur in each position in the number system.
The generalized form of a decimal point is known as radix point. In any number system
(N), the radix point divides the integer and the fractional part as shown.
N = [Integer part . Fractional part]

Radix point

Types of Number Systems

There are four types of number system namely
i). Decimal Number system
ii). Binary Number System
iii). Octal Number System
iv). Hexadecimal Number System

1.1 Decimal Number System

This is the standard system for denoting integer and non-integer numbers. This system
uses ten unique numbers: 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9. The base for this system is 10. It is
a positional weighted system and the value attached to each number depends on its
location with respect to the decimal point. The weighting structure for this system is as
shown
10n-1……….103 102 101 100. 10-1 10-2 10-3 10-4………………10n

For example:
9256.26 = 9 x 103 + 2 x 102 + 5 x 101 + 6 x 100 + 2 x 10-1 + 6 x 10-2

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1.2 Binary Number System
This system uses only two digits “0” and “1” called the binary digits (bits). The binary
point separates the integer and the fractional parts. It is a positional weighted system with
a base of two and its weighting structure is as shown

2n-1……….23 22 21 20. 2-1 2-2 2-3 2-4………………2n

(MSB) (LSB)
Binary point

Conversion from Decimal to Binary System

For integer numbers, divide the number continuously by two until it becomes zero then
read the remainders of the division upwards to write down the binary digits, while for
fractional numbers, multiply the number continuously by two until the fractional parts
becomes zero then read the integer parts resulting from multiplication downwards to
write down the equivalent binary number.

Examples
Convert the following to binary
a) 5210
b) 57.2510

Solution
(a)
2 52 Remainder
2 26 0 (LSB)
2 13 0
2 6 1
2 3 0
2 1 1
0 1 (MSB)

Therefore; 5210 = 1101002

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(b)
2 57 Remainder
2 28 1 (LSB)
2 14 0
2 7 0 Fractional Part
2 3 1 0.25x2 = 0 .5 0
2 1 1 0.5x2 = 1 .0 1
0 1 (MSB)

Therefore; 5710 = 1110012 Therefore, 0.2510 = 0.012

Combining the two, we get 57.2510 = 111001.012

Conversion from Binary to Decimal System

Multiply each binary digit by its corresponding weight then add to get the decimal
number.
Examples
Convert the following to decimal system
a) 101101112
b) 11011.10112
Solution
a) 101101112, the corresponding positional weights are: 27 26 25 24 23 22 21 20
Therefore, product is

b) 11011.10112 Corresponding positional weights are: 24 23 22 21 20 2-1 2-2 2-3 2-4

Resulting to

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Binary Coded Decimal (BCD) System
This is a type of binary where each decimal number is represented by group of four
binary digits (bits). The bits used here ranges from 0000 to 1001 only corresponding to
decimal numbers 0 to 9 respectively. The binary coded system is also called the 8421
code system. For a single digit decimal number, its BCD is the four binary digits, while
for other decimal numbers more than one digit, their BCDs are respective four bits for
each digit.

Conversion from Binary to BCD

Steps
i). Convert binary to decimal
ii). Convert each decimal digit to four bits using long division
iii). Add zeros to the left hand side if the resultant bits from division are less than four

Example
Convert 111012 to BCD
Solution
111012 = 2910
2910 = 210 = 0010, and 910 = 1001
Therefore; 111012 = 00101001BCD

Conversion from BCD to Binary

Steps
i). Convert each group of four bits (counting from right hand side) to decimal
ii). Convert the resulting decimal number to binary using long division

Example
Convert 00110011BCD to binary

Solution
00110011BCD = 3310

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 2 33 Remainder
2 16 1 (LSB)
2 8 0
2 4 0
2 2 0
2 1 0
0 1 (MSB)

Therefore; 00110011BCD = 1000012

1.3 Octal System

This system uses eight numbers: 0, 1, 2, 3, 4, 5, 6 and 7. The base for this system is 8. It
is a positional weighted system and its base is 8 = 23, every 3- bit group of binary can be
represented by an octal digit. The weighting structure for this system is as shown

8n-1……….83 82 81 80. 8-1 8-2 8-3 8-4………………8-n

(MSD) (LSD)
Point

Conversion from Decimal to Octal System

The procedure used in decimal to binary conversion is applied, only that 8 is used as a
divisor or multiplier.
Examples
Convert the following to octal system
a) 5510
b) 67.12510
Solution
a)
8 55 Remainder
8 6 7 (LSD)
0 6 (MSD)

Therefore; 5510 = 678

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 Fractional Part
b) 8 67 Remainder
0.125x8 = 1 .0 1
8 8 3 (LSD)
8 1 0
0 1 (MSD)

Therefore; 6710 = 1038 Therefore; 0.12510 = 0.18

Combining the two, we get 67.12510 = 103.18

Conversion from Octal to Decimal System

Multiply each octal digit by its corresponding weight then add to get the decimal number.
Examples
Convert the following to decimal system
a) 235.28
b) 45.148
Solution
a) 235.28, the corresponding positional weights are: 82 81 80 8-1
Therefore, product is

b) 45.148 Corresponding positional weights are: 81 80 8-1 8-2

Resulting to

1.4 Hexadecimal System

This system uses 16 characters consisting of numbers 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 then letters
A, B, C, D, E and F corresponding to numbers 10, 11, 12, 13, 14 and 15. The base for this
system therefore is 16. The numbers in this system are denoted using 16 or hex as a base
or simply putting capital letter (H) after the number. Thus, number 25 in hexadecimal
system is written as 2516 or 25hex or 25H. Since the base for the system is 16 = 24, every

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group of four bits in binary can be represented by hexadecimal digit. The hexadecimal
number system is a positional weighted system and its weighting structure is as shown.

16n-1……….163 162 161 160. 16-1 16-2 16-3 16-4………………16-n

(MSD) (LSD)
Point

The counting sequence in this system is as follows:

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B,
1C, 1D, 1E, 1F, 20, 21, …………29, 2A, ………2F, 30, 31, ……….39, 3A, ……3F etc

Conversion from Decimal to Hexadecimal System

The procedure used in decimal to binary conversion is applied, only that 16 is used as a
divisor or multiplier.

Examples
Convert the following to hexadecimal system
a) 50510
b) 687.62510

Solution
a)
16 505 Remainder
16 31 9 (LSD)
16 1 15 (F)
0 1 (MSD)

Therefore; 50510 = 1F916

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 Fractional Part
b) 16 687 Remainder
0.625x16 = 10 .0 10(A)
16 42 15(F) (LSD)
16 2 10(A)
0 2 (MSD)

Therefore; 68710 = 2AF16 Therefore; 0.62510 = 0.A16

Combining the two, we get 687.62510 = 2AF.A16

Conversion from Hexadecimal to Decimal System

Multiply each hexadecimal digit by its corresponding weight then add to get the decimal
number.

Examples
Convert the following to decimal system
a) 65.416
b) 805.4816

Solution
a) 65.416, the corresponding positional weights are: 161 160 16-1
Therefore, product is

b) 805.4816 Corresponding positional weights are: 162 161 160 16-1 16-2
Resulting to

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Exercises
1. Perform the following number system operations
i). 100011012 - 001101012
ii). FAB16 – 34C16
2. Convert the following to hexadecimal system
i). 110110112
ii). 10101.01012
3. Convert the following to octal system
i). 202210
ii). 3FA.4416
4. Convert the following to BCD
i). 101110012
ii). 001100102

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CHAPTER TWO
2. FUNDAMENTALS OF BOOLEAN ALGEBRA AND FUNCTIONS
2.1 Boolean Algebra
Boolean algebra is an algebra that deals with binary variables and logic operations. It is a
logical algebra where symbols are used to represent logic levels. The symbols that are
used to represent the two levels of a two valued logical system are “1” and “0”. The
symbol “1” may represent a closed switch, a true statement, an ON lamp or a HIGH
voltage, while “0” may represent an open switch, a false statement, an OFF lamp or a
LOW voltage. Boolean functions can be expressed algebraically with binary variables,
logic operation symbols, brackets and equal sign. Alphabetical letters are usually used to
represent variables in Boolean algebra and these variables can either be “1” or “0”.
Boolean algebra has only two mathematical operations / algebraic symbols used namely;
addition (+) and multiplication (.). Boolean algebra consists of seven postulates and ten
theorems.

a) Postulates (Assumptions)
A postulate is a preposition which is taken to be true. In Boolean algebra, these are:
i). Input variable, X = 0 or 1
ii). 0.0 = 0
iii). 1+1 = 1
iv). 0+0 = 0
v). 1.1 = 1
vi). 1.0 = 0
vii). 1+0 = 1
b) Theorems
A theorem in Boolean algebra is a rule concerning fundamental relation between the
Boolean variables. Boolean theorems are described by two parts for addition (+) and
multiplication (.) operations. These theorems are:
1. Commutative Law
(a) A+B = B+A
(b) A.B = B.A

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2. Associative Law
(a) (A+B)+C = A+(B+C)
(b) (A.B).C = A.(B.C)
3. Distributive Law
(a) A.(B+C) = A.B+A.C
(b) A+(B.C) = (A+B).(A+C)
4. Identity Law
(a) A+A = A
(b) A.A = A
5. Complement (Negation) Law
(a) :Note;
(b)
6. Redundancy (Absorption) Law
(a) A+A.B = A
(b) A.(A+B) = A
7. Zero and Unit Laws
Zero Law
(a) 0+A = A
(b) 0.A = 0
Unit Law
(a) 1+A = A
(b) 1.A = A
8. (a)
(b)
9. (a)
(b)

10. De-Morgan’s Theorem

(a)
(b)

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c) Applications of Boolean Theorems
Boolean theorems are used to simplify and manipulate logic functions.
Examples
1. Use Boolean theorems to simplify the given logic functions
(a)
(b)
2. Complement the given logic functions
(a)
(b)

Solutions
1.
(a) From

Applying De-Morgan’s theorem, we have

(A+B+C).C+(A+B+C)+D……………………(i)
Factoring out (A+B+C), we get
(A+B+C)(C+1)+D……………………………(ii)
(C+1)=1
Thus (ii) reduces to;
A+B+C+D

(b) From

Factoring out , we get

……………………….(i)
……………………..……(ii)
Thus (ii) reduces to;
…………………………….(iii)
Using theorem (9), equation (iii) reduces to;

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2.
(a) From

Complementing, we have

Applying De-Morgan’s theorem, we get

(b) From

Complementing, we have
……………(i)
Applying De-Morgan’s theorem, we get
………………….(ii)
Expanding, equation (ii) becomes;
……………….(iii)
Opening the brackets, equation (iii) becomes
……………..(iv)
This reduces to;

2.2 Truth Tables and their Applications

This is a listing of all possible input combinations and the resulting output of a logic
function in form of a table. The number of possible input combination is given by 2n
where “n” is equal to the number of input variables.

Uses of Truth Tables

i). To test if logic functions are same or not
ii). To test if Boolean theorems are correct

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Examples
1. Use a truth table to test if;

2. Use a truth table to test redundancy theorem of Boolean algebra

Solutions
1. From

Inputs are two; X and Y, thus truth table is

Inputs Outputs
X Y

0 0 1 1
0 1 1 1
1 0 0 0
1 1 1 1

The outputs are same; hence the logic function is similar

2. The redundancy theorem of Boolean algebra is

(a) A+A.B = A
(b) A.(A+B) = A
The truth table is
(a) (b)

Inputs Outputs Inputs Outputs

A B A+A.B A A B A.(A+B) A

0 0 0 0 0 0 0 0

0 1 0 0 0 1 0 0

1 0 1 1 1 0 1 1

1 1 1 1 1 1 1 1

The outputs are same; hence the theorem is correct

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CHAPTER THREE
3. BASIC LOGIC GATES AND THEIR LOGIC OPERATIONS
Logic gates are electronic devices with one or more inputs but only one output and do not
require any clock pulse for their operations. The relationship between the input and the
output is based on certain logic operations. Logic operations are classified as true or false
usually represented by Boolean variables, “1” or “0” respectively.

3.1 Types of Basic Logic Gates

There are eight basic types of logic gates:

(a) NOT gate

This has only one input and one output. Its algebraic symbol is a bar (-) or a prime (,)
above the input variable. Its logic circuit symbol is shown in Figure 3.1(a)

Figure 3.1 (a): Logic circuit symbol of NOT gate

Its logic equation is

Thus, its output is a complement of the input variable.

(b) AND gate

This has two or more inputs, but only one output. Its algebraic symbol is a dot (.) between
the input variables. Its logic circuit symbol is shown in Figure 3.1 (b)

Figure 3.1 (b): Logic circuit symbol of AND gate

Its logic equation is

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Its output is always zero, unless all its inputs are “1”. This operation can be shown using
a truth table.

(c) OR gate
This has two or more inputs, but only one output. Its algebraic symbol is a plus (+)
between the input variables. Its logic circuit symbol is shown in Figure 3.1 (c)

Figure 3.1 (c): Logic circuit symbol of OR gate

Its logic equation is

Its output is always “1”, unless all its inputs are “0”. This operation can be shown using a
truth table.

(d) NAND gate

This has two or more inputs, but only one output. It is similar to AND gate followed by a
NOT gate, therefore, it performs the opposite of an AND gate. Its logic circuit symbol is
shown in Figure 3.1 (d)

Figure 3.1 (d): Logic circuit symbol of NAND gate

Its logic equation is

Therefore, its output is always “1”, unless all its inputs are “1”

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 (e) NOR gate
This has two or more inputs, but only one output. It is similar to OR gate followed by a
NOT gate, therefore, it performs the opposite of an OR gate. Its logic circuit symbol is
shown in Figure 3.1 (e)

Figure 3.1 (e): Logic Circuit Symbol of NOR gate

Its logic equation is

Therefore, its output is always “0”, unless all its inputs are “0”

(f) XOR (Exclusive OR) gate

This logic gate has only two inputs and one output. Its logic circuit symbol is shown in
Figure 3.1 (f)

Figure 3.1 (e): Logic circuit symbol of XOR gate

Its logic equation is

Therefore, its output is always “1”, when its inputs are opposite

(g) XNOR (Exclusive NOR) gate

This logic gate has only two inputs also and one output. It is similar to XOR gate
followed by a NOT gate, therefore, it performs the opposite of XOR gate. Its logic circuit
symbol is shown in Figure 3.1 (g)

Figure 3.1 (g): Logic circuit symbol of XNOR gate

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Its logic equation is

Therefore, its output is always “1”, when its inputs are similar

(h) Buffer gate

This is a basic logic gate that has one input and one output and passes its input,
unchanged, to its output. Its behavior is the opposite to that of a NOT gate. The main
purpose of a buffer is to regenerate the input, usually using a strong high and a strong
low. The logic circuit symbol of a buffer gate is shown in Figure 3.1 (h).

Figure 3.1 (h): Logic circuit symbol of Buffer gate

Its logic equation is

Therefore, its output is always equals to its input in terms of logic level. Buffers are
mainly used for power amplification to drive other gates that require large amount of
power. The power input to a buffer is usually much less than the power produced at its
output.

NOTE:
The NAND and NOR gates are universal logic gates, therefore they can be used to
implement any logic functions

Exercises
Develop the truth tables of NAND and XNOR gates

3.2 Combinational Logic Circuits

These are circuits whose output depends only on the present condition of input variables.
These circuits are designed using logic gates.

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a) Designing Combinational Logic Circuits
i). From Boolean Expressions
Design combinational logic circuits to implement the given logic functions
(a)
(b)

Solutions
(a) From the given function

Combinational logic circuit is;

A
B
C

ii). Obtaining Boolean Functions from Combinational Logic Circuits

Consider the combinational circuit given in Figure 3.2 (a)

B Y

Figure 3.2 (a)

(a) Obtain the unsimplified logic expression for this circuit
(b) Using Boolean theorems, simplify the logic expression in (a)
(c) Draw a combinational logic circuit for the resulting function in (b)

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Solutions
(a)
(b) Applying De-Morgan’s theorem to (a), we get;
(A+B).C + (A+B)
Factoring out (A+B), we get;
(A+B)(C+1)
(C+1) = 1, thus the expression reduces to;
Y=A+B

(c) Circuit is a two input OR gate

A Y
B

iii). Using NAND and NOR gates Only as Universal Logic gates
Universal logic gate is one which can be used to implement any logic function. NAND
and NOR gates are universal logic gates. A NOT gate can be made from NAND or NOR
gates by connecting all the inputs together to create a single input line as shown in Figure
3.2 (b) and (c) respectively.

Figure 3.2 (b): NOT gate using NAND gate

In this case, the logic equation for the output (Y) is given by

Similarly, using the NOR, gate the NOT function can be implemented by joing all its
inputs together as given in Figure 3.2 (c)

Figure 3.2 (c): NOT gate using NOR gate

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The logic equation for the output (Y) is given by

Exercise
Draw a logic circuit diagram showing how an OR and an AND function can be
implemented using;
(a) NAND gates only
(b) NOR gates only

NOTE:
When circuits become more complex, the following systematic procedure can be applied
for NAND and NOR gates implementations

NAND gates Implementation

Steps:
i) Manipulate the given logic function into a form in which all the terms are
ORed (sum of products)
ii) Double negate the resulting expression so that the expression is not changed
iii) Apply De-Morgan’s theorem to the inner negation sign so as to affect the
algebraic symbols (additions) only leaving each term as it is
iv) The resultant function in (iii) is a NAND form function, which can be
implemented using NAND gates only
Example
Consider the given logic expression

(a) Manipulate the above expression into a form which can be implemented using
NAND gates only
(b) Draw the combinational logic circuit for the resulting expression in (a)

Solution
(a) From

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Opening the brackets we get ORed function i.e.

Double negating the function we have;

Applying De-Morgan’s to the inner negation sign so as to affect the algebraic signs only
we get;

This is a NAND function

(b) Combinational logic circuit is

C Y

Exercise
Consider the given logic expressions
i)
ii)
(a) Manipulate the above expressions into a form which can be implemented using
NAND gates only
(b) Draw the combinational logic circuits for the resulting expressions in (a)

NOR gates Implementation

Steps:
i) Manipulate the given logic function into a form in which all the terms are
ANDed (product of sums)
ii) Double negate the resulting expression so that the expression is not changed

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 iii) Apply De-Morgan’s theorem to the inner negation sign so as to affect the
algebraic symbols (products) only leaving each term as it is
iv) The resultant function in (iii) is a NOR form function, which can be
implemented using NOR gates only
Example
Consider the given logic expression

(a) Manipulate the above expression into form which can be implemented using NOR
gates only
(b) Draw the combinational logic circuit for the resulting expression in (a)

Solution
(a) From

The truth table for the function is

From the table, the output is “0”, when

Thus, to get “1”, we negate the above function as follows;

Applying De-Morgan’s theorem we get

These terms are ANDed, thus double negating we have

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Applying the inner negation sign leaving each term as it is results to;

This is a NOR function

(b) Combinational logic circuit is

Y
B

Exercise
1. Consider the given logic expressions
i).
ii).
(a) Manipulate the above expressions into forms which can be implemented using
NOR gates only
(b) Draw the combinational logic circuits for the resulting expressions in (a)

2. Design and draw a combinational logic circuit to provide a HIGH output

whenever any two of its three inputs are HIGH

3.3 Karnaugh Maps

A K-map is an array of cells in which each cell represents a binary value of the input
variables.

Uses of K-Maps
i). To test if logic functions are similar or not
ii). To simplify (minimize) logic functions

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Simplification of logic functions using K-maps is done by grouping cells with adjacent
logic 1s. Grouping of cells is done horizontally or vertically in powers of two, namely; 2,
4, 8, 16…. by starting with the largest possible group with adjacent logic 1s. The number
of cells in a K-map is equal to the number of possible input combinations and given by
2n, where “n” equals the number of input variables. Each cell in a K-map represents an
AND term of the input variables. K-maps with three inputs and more are considered like
spheres, therefore, cells with logic 1s on extreme ends are adjacent and hence should be
grouped together. In a K-map, normally, logic 1 is only indicated in the map and an
empty cell represents absence of the corresponding variable term in the logic function.

Types of K-Maps
a) Two input variable K-Map
This is an array of four cells from the relation 22 = 4 designed as follows;

This K-map can also be designed in terms of the decimal equivalent values of the binary
combinations of row and column as follows;

In this type of K-map,

i). A single cell represent the AND term of the two input variables
ii). A group of two cells with adjacent logic 1s represent a single variable term that is
consistent (same) within the group
iii). Different loops of grouped adjacent logic 1s are ORed (summed) to get the
resulting simplified function

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Examples
Use K-maps to simplify the given logic functions
(a)
(b)
(c)

Solutions
(a)
K-map is

Therefore the simplified function is

(b)
K-map is

(c)
K-map is

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Therefore the simplified function is

b) Three input variable K-Map

This is an array of eight cells from the relation 23 = 8 designed as follows;

This K-map can also be designed in terms of the decimal equivalent values of the binary
combinations of row and column as follows;

For this type of K-map;

i). A single cell represents a three variable AND term
ii). A group of two cells with adjacent logic 1s represents a two variable AND term
that is consistent (same) within the group
iii). A group of four cells with adjacent logic 1s represents a single variable term that
is consistent (same) within the group
iv). The binary values for the columns BC should always follow the sequence; 00, 01,
11 and 10, which allows simplification by grouping

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Examples
Use K-maps to simplify the given logic functions
(a)
(b)

Solutions
From
(a)
K-map is

Therefore, the resulting simplified function is;

(b) Given

We have binary values as: 0=000, 2=010, 4=100, 5=101, and 6=110
K-map is;

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Therefore, the simplified function is;

c) Four input variable K-Map

This is an array of eight cells from the relation 24 = 16 designed as follows;

This K-map can also be designed in terms of the decimal equivalent values of the binary
combinations of row and column as follows;

For this type of K-map;

i). A single cell represents a four variable AND term
ii). A group of two cells with adjacent logic 1s represents a three variable AND term
that is consistent (same) within the group
iii). A group of four cells with adjacent logic 1s represents a two variable AND term
that is consistent (same) within the group

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iv). A group of eight cells with adjacent logic 1s represents a single variable term that
is consistent (same) within the group
v). The binary values for the columns rows AB and columns CD should always
follow the sequence; 00, 01, 11 and 10, which allows simplification by grouping

Examples
Use K-maps to simplify the given logic functions
(a)
(b)

Solutions
(a) Form

K-map is;

Therefore, the resulting simplified function is;

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 (b) Form

We have binary values as: 0=0000, 1=0001, 6=0110, 7=0111, 8=1000, 9=1001,
14=1110, and 15=1111

K-map is;

Therefore, the resulting simplified function is;

Exercises
Use K-Maps to simplify the given logic functions
(a)
(b)
(c)

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CHAPTER FOUR
4. FLIP-FLOPS
Flip flops are circuits of binary cells capable of storing one bit of information. All flip
flops have two outputs namely; (Q), for normal value and for the complement value
of the bit stored. Flip flops are bi-stable in nature, thus they have two stable states
namely; “0” and “1”. Since flip flops can store information bit, they are the basic units of
memory devices.

Types of Flip Flops

There are four types of flip flops namely;
(a) RS flip-flop
(b) D flip-flop
(c) JK flip-flop
(d) T flip-flop

(a) The RS flip-flop

This has two inputs namely; R (reset) and S (set) and two outputs (Q) and . The logic
circuit diagram of RS flip-flop is as shown in Figure 4.1 (a)

Figure 4.1 (a): Logic Circuit diagram of RS flip-flop

The next output state (Qn+1) depends on the present output state (Qn) and the inputs R and
S.

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Operation of RS flip-flop
i). If R = S = 0, the output (Q) remains in the same state of without changing
ii). If R = 0 and S = 1, the output (Q) is “1”, that is, the flip-flop sets
iii). If R = 1 and S = 0, the output (Q) is “0”, that is, the flip-flop resets
iv). If R = S = 1, the output (Q), can be in either state, that is, “0” or “1”, hence is
undetermined and is an invalid input condition usually not allowed for RS flip-
flop
The above characteristic operations of RS flip-flop can be represented using the truth
table given in Table 4.1 (a)

Inputs Present Output Next Output Remarks

S R (Qn) (Qn+1)
0 0 0 0 No change
0 0 1 1
0 1 0 0 Resets
0 1 1 0
1 0 0 1 Sets
1 0 1 1
1 1 0 x Invalid
1 1 1 x

Table 4.1 (a): Operation of RS flip-flop

From the table, the logic equation giving the next output state of RS flip-flop is given by;

The Clock (CK) Input

A clock is a square wave input pulse that is used to synchronize (time) the operations of a
circuit system. The output of a clocked system does not change according to the changes
of the input conditions but only changes when a clocked pulse is applied. A clock pulse
signal shape is as shown in Figure 4.1 (b)

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Figure 4.1 (b): Clock Signal Pulse

Rising edge (positive going) is the edge of the clock signal pulse when the output is
increasing from low (0) to high (1) while falling edge (negative going) is the edge of the
clock signal pulse when the output is decreasing from high (1) to low (0).
Clock Width
This is the time during which the clock signal is maximum (high) or “1”
Clock Period
This is the time between successive clock signal transitions in the same direction
Clock Frequency
This is the reciprocal of the clock period
Clock Duty Cycle
This is the ration of the clock width to the clock period
A clock signal is active high if the circuit system output changes occur during the clock’s
rising edge; otherwise, it is active low. A clocked flip-flop whose output responds to
inputs when the clock signal is high is called a latch. The circuit symbol of RS flip-flop is
as shown in Figure 4.1 (c).

Figure 4.1 (c): Circuit Symbol of RS flip-flop

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 (b) The D flip-flop
This is made from RS flip-flop by marking R the complement of S, i.e.: therefore,
a NOT gate is connected between inputs R and S so that S is the only input point, called
input “D”, so called because of the flip-flops ability to hold “data”. The logic circuit
diagram for D flip-flop is as shown in Figure 4.1 (d)

Figure 4.1 (d): Logic Circuit diagram of D flip-flop

The logic equation giving the next output state of D flip-flop is given by;

The operation of D flip-flop is explained using its truth table given in Table 4.1 (b)

Table 4.1 (b): Truth table of D flip-flop

The circuit symbol of D flip-flop is shown in Figure 4.1 (e)

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Figure 4.1 (e): Circuit Symbol of D flip-flop

(c) The JK flip-flop

The JK flip flop was developed to overcome the invalid condition of RS flip-flop that
occur when both inputs S and R are equal to logic level “1”. The JK flip-flop therefore
allows all possible input conditions to be applied. The logic circuit diagram of JK flip-
flop is as shown in Figure 4.1 (f)

Figure 4.1 (f): Logic Circuit diagram of JK flip-flop

The JK flip-flop reverses its output states on every application of clock pulse as long as
J=K=1. This reversal of the output states under this condition is called the toggling state
and the JK behaves like a toggle switch. The toggling behavior of the JK can be shown
using a truth table developed from its logic equation given by;

The truth table of JK flip-flop is given in Table 4.1 (c)

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Table 4.1 (c): Truth table of JK flip-flop

The logic circuit symbol of JK flip-flop is as shown in Figure 4.1 (g)

Figure 4.1 (g): Logic Circuit Symbol of JK flip-flop

(d) The T flip-flop

This is a single input version of JK flip-flop. It is obtained from JK by joining its two
inputs together so that there is only one input called the “T” input, so called because this
flip-flop also toggles for every input clock pulse as long as input T=1. The logic circuit
diagram of T flip-flop is as shown in Figure 4.1 (h).

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Figure 4.1 (h): Logic Circuit diagram of T flip-flop

The logic circuit symbol of T flip-flop is as shown in Figure 4.1 (i)

Figure 4.1 (i): Logic Circuit Symbol of T flip-flop

The logic equation of T flip-flop is given by;

Exercise
Develop the truth table of T flip-flop

Applications of Flip Flops

Flip-flops have two main applications, namely;
(a) Designing Shift Registers
(b) Designing Counters

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 (a) Designing Shift Registers
A shift register is a group of flip-flops with a common clock connection connected in a
chair so that the output from one flip-flop becomes the input to the next flip-flop and
allows data to pass from one flip-flop to the next. Shift registers are designed using D-
flip-flops. The storage capacity of a shift register is determined by the number of flip-
flops used and is given by;

Where n=number of flip-flops.

Therefore, n-bit shift register is designed using n-flip-flops.

Types of Shift Registers

There are four types of shift registers namely;
i). Serial-In Serial-Out (SISO) shift register
ii). Serial-In Parallel-Out (SIPO) shift register
iii). Parallel-In Serial-Out (PISO) shift register
iv). Parallel-In Parallel-Out (PIPO) shift register

i) Serial-In Serial-Out ((SISO) Shift Register

This accepts data one bit at a time and also produces stored data one bit at a time at the
output line as shown in Figure 4.2 (a)

Figure 4.2 (a): Block diagram of SISO shift register

ii) Serial-In Parallel-Out (SIPO) Shift Register

Data is entered one bit at a time and once stored all the data bits are available
simultaneously on their respective output lines as shown in Figure 4.2 (b).

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Figure 4.2 (b): Block diagram of SIPO shift register

iii) Parallel-In Serial-Out (PISO) shift register

Data is entered all bits at once and obtained one bit at a time at the output line as shown
in Figure 4.2 (c).

Figure 4.2 (c): Block diagram of PISO shift register

The circuit uses D flip-flops and NAND gates for entering data (i.e writing) to the
register.

iv) Parallel-In Parallel-Out (PIPO) shift register

Data is entered all bits at once and also produces simultaneously at the respective output
lines as shown in Figure 4.2 (d).

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Figure 4.2 (d): Block diagram of PIPO shift register

Applications of Shift Registers

i). To convert data from one format to another i.e. from serial to parallel and vice
versa
ii). To produce time delays
iii). To perform simple binary multiplication and division

(b) Designing Counters

These are circuits that follow a predetermined sequence of states when clock pulses are
applied at their inputs. Counters are mainly used to keep track of events. Counters are
designed using JK flip-flops because, JK flip-flops allows all the possible input
conditions to be applied.

Types of Counters
There are two types, namely;
(a) Asynchronous (Ripple) Counter
(b) Synchronous Counter

(a) Asynchronous Counter

This is where the flip-flops are wired in series with the Q-output of one flip-flop
connected the clock input of the next flip-flop. The output of these counters is free from
the clock signal. Because the flip flops in asynchronous counters are not switched on
simultaneously the counter states ripples as each flip-flop is switched on in succession,

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and hence a delay in producing output. The number of output states of a counter is called
“Modulus” or “MOD” of the counter and given by the relation;

Where n=the number of flip-flops used in designing the counter. Figure 4.2 (e) shows a
block diagram of mod 16 asynchronous counter.

Figure 4.2 (e): Block diagram of Mod 16 Asynchronous Counter

(b) Synchronous Counter

This is where all the flip-flops in the counter are switched on simultaneously by use of
additional logic gates and an external common clock eliminating the ripple effect. In
synchronous counter, the clock input across all the flip-flops use the same source and
creates the same clock signal at the same time. Figure 4.2 (f) shows a block diagram of
mod 16 synchronous counter.

Figure 4.2 (f): Block diagram of Mod 16 Asynchronous Counter

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4.3 Sequential Circuits Design
Sequential circuits are circuits whose present output is a function of the present as well as
the previous sequence of inputs. Such circuits are designed using flip flops and logic gate.
The operations of sequential circuits depend on the internal state or condition of the
circuit system and follow a particular sequence. A sequence of internal states is produced
by a sequence of inputs, with each internal state characterized by a set of successive
states.
Definition of Terms
a) State
This is a unique configuration of information in a circuit system. A state of a system is
usually represented by a circle with binary numbers inside the circle.

b) State Diagram
This is a graphical representation of the internal state of a circuit system. It is used to
represent the behavior of the circuit system. In state diagrams, circles are used to
represent the state and transitions between the states are represented by directed lines.
The binary number inside each circle identifies the state the circle represents. The
directed lines are labeled with two binary numbers separated by a slash (/). The input
value that causes the state transition is labeled first. The number after the slash symbol (/)
gives the value of the output. Figure 4.3a shows an example of a state diagram

Figure 4.3a: State diagram of a system with four states

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In Figure 4.3a, the directed line from state 00 to 01 is labeled 1/0, meaning that, if the
sequential circuit is in a present state (00) and the input is 1, then the next state is (01)
and the output is 0. A directed line connecting a circle with itself indicates that no change
of state occurs thus, if it is in a present state (00) and the input is 0, it will remain in the
same state. The state diagram provides exactly the same information as the state table and
is obtained directly from the state table.

c) State Table
This is a complete representation of sequential circuit consisting of present state, next
state and the output for given input variables in form of a table. The present state shows
the state of the elements of the circuit before the application of the input pulse, the next
state shows the circuit state on the application of the input pulse while the output lists the
output variables for given present state and inputs.

Example
Consider a sequential circuit shown in Figure 4.3b, with one input (X), one output (Z)
and two present state variables Q1Q2

Figure 4.3b

a) Write down the Boolean expressions which can be used to determine the behavior
of this circuit

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 b) From the Boolean expressions in (a), develop the state table for the circuit
c) From the state table in (b), draw the state diagram for the circuit

Solutions
a) Since the circuit has two present states, Q1Q2, it therefore has four possible present
states 00, 01, 10, 11
D1D2, will give the next state for the circuit. The input (X), can either be 0 or 1. The
behavior of the circuit is determined by the following Boolean expressions:

b) The state table for the circuit is obtained as follows: We let the present state (i.e.
Q1Q2) = 00 and input X = 0. Under these conditions, we get Z = 0, D1 = 1, and D2
= 1. Thus the next state of the circuit D1D2 = 11, and this will be the next state
after the clock pulse has been applied. The output of the circuit corresponding to
the present state Q1Q2 = 00 and X = 1 is Z = 0. Similarly, the next states and
outputs for other present states and inputs can be obtained and the state table for
the circuit is as shown in Table 4.3

Table 4.3: State table for the sequential circuit

c) The state diagram for the sequential circuit is as shown in Figure 4.3c.

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 Figure 4.3c: State diagram for the sequential circuit

4.4 Classifications of Sequential Circuits

Sequential circuits are classified into two, namely;
i). Asynchronous (un-clocked) sequential circuits
ii). Synchronous (clocked) sequential circuits

Asynchronous Sequential Circuits

These are sequential circuits whose behavior depends only on the order in which the
input signals change and can be affected at any instant of time. These circuits do not have
any timing (clock) associated with them, but they have feedback circuits to provide
information about the internal states of the circuit. Block diagram of asynchronous
sequential circuit is shown in Figure 4.4a

Figure 4.4a: Block diagram of Asynchronous sequential circuit

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Synchronous Sequential Circuits
These are sequential circuits where the changes in the inputs do not cause an immediate
change in the outputs but the output change is only initiated on the arrival of input clock
pulse. The operations of these circuits are synchronized (timed) with the clock pulse.
Block diagram of synchronous sequential circuit is shown in Figure 4.4b

Figure 4.4b: Block diagram of Synchronous sequential circuit

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