Introduction To Computers (II) ICE Group: Lesson 6: Memorization Elements

14/02/2023
ITC
Introduction to Computers (II)
ICE Group
Lesson 6: Memorization elements
Couse 2022-2023
Engineering Introduction to Computers Lesson 6 Pag. 1
Introduction
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Introduction Output variables only depend on the
values of the different input variables
Combinational
system all of the time  they do not have
memory.
Combinational Systems
(Semester 1)
Digital
systems
SYNCHRONOUS
Sequential Systems
(Semester 2)
ASINCHRONOUS
the outputs are dependent on not only
Sequential their current inputs (as in combinational
system circuits), but also on all their past inputs 
they contain memory elements.

Introduction
The memorization is done by connecting the output of a logic gate back to the input of
that same gate  feedback loop circuit.
Feedback loop
Combinational Sequential
Systems Systems
How can we build a circuit capable of memorizing one bit of information?
IDEA: Using two inverters connected so the
output of the first inverter is the input of the
second one.
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Classification of
sequential systems
Lesson 6: Classification of sequential systems

Basic concepts
SÍNCRONOS
The output depends on a
synchronization signal.
ASÍNCRONOS
The output is not dependent on a
synchronization signal.
In the case of synchronous digital systems, the signal that time (or synchronize) its
evolution is called clock.
‘1’ logic
‘0’ logic
Oscillators
SÍNCRONOS
CLOCK signal
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Lesson 6: Classification of sequential systems

Basic concepts
The clock signals have two differentiated levels:
High: 5 volts = “1” logic.
Low: 0 volts = “0” logic.
The synchronism is often named clock (T). It is only a periodic signal that toggles its value,
so its frequency determines the frequency of the digital system :
Rising edge (positive edge): low‐to‐high transition.
Falling edge (negative edge): high‐to‐low transition.
Memory elements in digital systems:
A one bit of memory  BISTABLES
A group of bistables (group of bits) REGISTERS
A group of registers (data)  MEMORIES
Lesson 6: Classification of sequential systems System
Basic concepts
Example 1‐ ASINCHRONOUS: Let us assume a non‐synchronous sequential system with
two inputs A and B, and a single output Z. All these variables are initially equal to zero.
Let us suppose the following operation:
The variable Z is set to one when A and B are set to one.
The variable Z is set to zero when A and B are set to zero.
For both cases, if only one variable change, Z keeps whatever value it had.
Assuming the following inputs A and B and since the sequential system is asynchronous,
the timing diagram of Z would be :
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Basic concepts
Example 1‐ ASINCHRONOUS: Let us assume a non‐synchronous sequential system with
two inputs A and B, and a single output Z. All these variables are initially equal to zero.
Assuming the following inputs A and B and since the sequential system is asynchronous,
Basic concepts
Example 2‐ SINCHRONOUS: Let us assume a synchronous sequential system with two
inputs A and B, and a single output Z. All these variables are initially equal to zero.
Assuming the following inputs A and B and since the sequential system is synchronous,
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Basic concepts
Basic concepts
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BISTABLES
Memory elements in digital systems:
A one bit of memory  BISTABLES
A group of bistables (group of bits) REGISTERS
A group of registers (data)  MEMORIES
Within the group of bistables, there are different classes:
SR bistable (bistable asynchronous  latch).
D flip‐flop (bistable synchronous  flip‐flop).
JK bistable (bistable synchronous). (Not covered)
D‐SR bistable (synchronous with asynchronous combination).

BISTABLES
D‐SR bistable
SR bistable D bistable (Synchronous /
(Asynchronous) (Synchronous) Asynchronous)
SR D D‐SR
bistable bistable bistable
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SR bistable
Lesson 6: SR Bistable
SR bistable (Asynchronous)
Inputs:
 It has two inputs that allow you to control the value
to be memorized. These inputs are called Set (S)
and Reset (R).
 It works by level.
Outputs:
 It has two outputs Q y in which a binary value is
Q
memorized according to the asynchronous inputs S
y R (level sensitive).
If RESET/SET is NOT activated  the previous value is maintained

If RESET is activated  Q = 0 (if SET = 0)
If SET is activated  Q =1 (if RESET = 0)
If RESET/SET are activated (forbidden) undetermined
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Truth table: SR circuit:
Timing diagram
Truth table: SR circuit:
Timing diagram
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SR bistable (Asynchronous) (negative logic)
Truth table SR Circuit
SR
bistable
Timing diagram
Class exercise
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Class exercise (Solution)
D bistable
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Lesson 6: D Bistable
D bistable (Synchronous)
Technical features:
 It is a synchronous bistable. That means, the output is
updated according to an input named trigger (clock).
 It works by edge detection.
 For this case, every time there is a rising edge, the value
of input D is passed to output Q.
Truth table:
without
Special case:
 What happens when the rising edge of the clock signal
coincides with the falling edge of the D signal?
 Don’t panic!! The clock is considered to be always faster,
so at the output we have Dt‐1.
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D Circuit:
Although the external appearance
looks like an RS bistable, the internal
implementation is more complex.
D bistable (Synchronous) (negative logic)
Truth table:
D
bistable
without
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Class exercise
Class exercise (solution)
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D-SR bistable
Lesson 6: D-SR Bistable

D‐SR Synchronous/Asynchronous
Technical features:
 It combines the edge‐detecting properties of a D bistable
with the level‐operating properties of a SR bistable.
 Therefore, its response is synchronous and
asynchronous depending on which inputs are activated.
 Shows the typical outputs Q and Q
Inputs:
 R, if it is activated  the output Q is zero.
 S, if it is activated  the output Q is one.
 D, it is the value which update Q when a rising edge is produced in T.
 T or synchronism signal (clock).
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Technical features:
 It combines the edge‐detecting properties of a D bistable
with the level‐operating properties of a SR bistable.
 Therefore, its response is synchronous and
asynchronous depending on which inputs are activated.
 Shows the typical outputs Q and Q
IMPORTANT: the inputs S and R
Inputs: have priority over T (clock) and D
 R, if it is activated  the output Q is zero.
 S, if it is activated  the output Q is one.
 D, it is the value which update Q when a rising edge is produced in T.
 T or synchronism signal.

D‐SR circuit:
The complexity is higher since it
is necessary to add a pair of
NAND gates on the internal S‐R
signals.
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Truth table:
without
Remember that the
inputs S and R have
priority over T (clock)
and D.

Exercise 1: Bistable outputs
Draw the value of the output signal Q
(mark the timing diagram well). (eStudy PDFs)
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EXERCISE 1: Bistable outputs (solution)
Draw the value of the output signal Q
(mark the timing diagram well).
Design of circuits
with multiple
bistables
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Lesson 6: Design of circuits with multiple bistables
Example 1: timing diagram analysis for Q1, Q2 and Q3
D‐SR SR D‐SR
Steps:
 Analyse the influence of external signals (in this case R and T)
 See how those changes affect the outputs of each bistable
D‐SR SR D‐SR
Steps:
 Analyse the influence of external signals (in this case R and T)
 See how those changes affect the outputs of each bistable
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D‐SR SR D‐SR
D‐SR SR D‐SR
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D‐SR SR D‐SR
D‐SR SR D‐SR
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D‐SR SR D‐SR
Synchronous and Asynchronous
D‐SR SR D‐SR
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Synchronous and Asynchronous
D‐SR SR D‐SR
Example 2: draw the signal A
We have to take into account the
signal T (clock) and the feedback D. D‐SR
bistable
A t
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bistable
bistable
This produces a change in the output
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Example 3: analysis A, B and C
The most important
characteristics must be evaluated
first and then the evolution of
outputs A, B and C.
IMPORTANT: take into account the
negative logic.
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A t
B t
C t
This produces a change in the
output
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output
output
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Example 4: analysis Y1, Y2, Y3 and Y4
Example 4: analysis Y1, Y2, Y3
and Y4
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and Y4
and Y4
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and Y4
and Y4
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and Y4

Exercise 2: Bistable outputs
Draw the timing diagram Y1 ,
Y1 , Y1 and Y4, but now using
negative edges for T (15
minutes. Only PDFs are
accepted).
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Bistables in VHDL
Lesson 6: Bistables in VHDL
Introduction
The Quartus Prime has some bistable implementations:
 RS bistable: norltch, nandltch.
 D‐SR Bistable: DFF, DFF2.
 Commercial bistables: 7474,…
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Introduction
We can also define our own bistables: using schematics or in VHDL.
As support material, you have available several bistables in VHDL on the
eStudy platform:
 SR bistable: RS_FF.
 D bistable: D_FF.
 D‐SR bistables: DRS_FF
SR bistable in VHDL
SR
bistable
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D bistable in VHDL
D
bistable
D‐SR bistable in VHDL
D‐SR
bistable
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Introduction
We can also define our own bistables: using schematics or in VHDL.
As support material, you have available several bistables in VHDL on the
eStudy platform:
TO WORK WITH THE BISTABLES AVAILABLE IN ESTUDY:
 SR bistable: RS_FF.
You have to: (i) copy the .vhdl
D bistable: D_FF. file(s) to the project folder, (ii) add it to the project, (iii) select it
(compile), (iv) define a symbol for the bistable, and (v) use it in any schematic project.
 D‐SR bistables: DRS_FF
Simulation of circuits
with bistables
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Lesson 6: Simulation of circuits with bistables
SR bistable: theory vs practice
Circuit to simulate
Theoretical outputs
Circuit to simulate
In the simulation, the University Program VWF sometimes does not give the
expected results with undetermined values in the in outputs. Furthermore, R=S=1
cannot be synthesized in reality and the value will depend on the specific
implementation of the circuit.
Theoretical outputs
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D‐SR bistable: theory vs practice
Circuit to simulate
Theoretical outputs
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D‐SR bistable: theory vs practice
QUARTUS: simulation
of circuits with
bistables
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QUARTUS: Example 1
QUARTUS: Example 1
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QUARTUS: Example 1
40

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14/02/2023

Engineering Introduction to Computers Lesson 6 Pag. 1

Engineering Introduction to Computers Lesson 6 Pag. 2

Lesson 6: Memorization elements

Lesson 6: Memorization elements

Engineering Introduction to Computers Lesson 6 Pag. 4

Engineering Introduction to Computers Lesson 6 Pag. 5

Lesson 6: Classification of sequential systems

Engineering Introduction to Computers Lesson 6 Pag. 6

Lesson 6: Classification of sequential systems

Engineering Introduction to Computers Lesson 6 Pag. 7

Lesson 6: Classification of sequential systems System

Engineering Introduction to Computers Lesson 6 Pag. 8

Lesson 6: Classification of sequential systems System

Engineering Introduction to Computers Lesson 6 Pag. 9

Lesson 6: Classification of sequential systems System

Engineering Introduction to Computers Lesson 6 Pag. 10

Lesson 6: Classification of sequential systems System

Engineering Introduction to Computers Lesson 6 Pag. 11

Lesson 6: Classification of sequential systems System

Engineering Introduction to Computers Lesson 6 Pag. 12

Lesson 6: Memorization elements

Engineering Introduction to Computers Lesson 6 Pag. 13

Lesson 6: Memorization elements

Engineering Introduction to Computers Lesson 6 Pag. 14

Engineering Introduction to Computers Lesson 6 Pag. 15

If RESET/SET is NOT activated  the previous value is maintained

Engineering Introduction to Computers Lesson 6 Pag. 16

Engineering Introduction to Computers Lesson 6 Pag. 17

Engineering Introduction to Computers Lesson 6 Pag. 18

Engineering Introduction to Computers Lesson 6 Pag. 20

Engineering Introduction to Computers Lesson 6 Pag. 21

Engineering Introduction to Computers Lesson 6 Pag. 22

Engineering Introduction to Computers Lesson 6 Pag. 23

Engineering Introduction to Computers Lesson 6 Pag. 24

Engineering Introduction to Computers Lesson 6 Pag. 25

Engineering Introduction to Computers Lesson 6 Pag. 26

Engineering Introduction to Computers Lesson 6 Pag. 27

Engineering Introduction to Computers Lesson 6 Pag. 28

Engineering Introduction to Computers Lesson 6 Pag. 29

Engineering Introduction to Computers Lesson 6 Pag. 30

Lesson 6: D-SR Bistable

Engineering Introduction to Computers Lesson 6 Pag. 31

Lesson 6: D-SR Bistable

Engineering Introduction to Computers Lesson 6 Pag. 32

Lesson 6: D-SR Bistable

Engineering Introduction to Computers Lesson 6 Pag. 33

Lesson 6: D-SR Bistable

Engineering Introduction to Computers Lesson 6 Pag. 34

Lesson 6: Memorization elements

Engineering Introduction to Computers Lesson 6 Pag. 35

Lesson 6: Memorization elements

Engineering Introduction to Computers Lesson 6 Pag. 36

Engineering Introduction to Computers Lesson 6 Pag. 37

Lesson 6: Design of circuits with multiple bistables

Engineering Introduction to Computers Lesson 6 Pag. 38

Lesson 6: Design of circuits with multiple bistables

Engineering Introduction to Computers Lesson 6 Pag. 39

Lesson 6: Design of circuits with multiple bistables

Engineering Introduction to Computers Lesson 6 Pag. 40

Lesson 6: Design of circuits with multiple bistables

Engineering Introduction to Computers Lesson 6 Pag. 41

Lesson 6: Design of circuits with multiple bistables