MODULE 2

Generation of FSK
Different types of digital carrier modulator are ASK (Amplitude Shift
keying), FSK (Frequency Shift Keying), and PSK (Phase shift
keying).

 The system consists of 2 oscillators that generate high and low

frequency signal separately. A binary message signal is provided to
the transmitter circuitry. The carrier wave from the 2 oscillators
and binary modulating signal operates the switch.

 In the case when the modulating signal bit is high ie, 1 the switch
gets closed forming a path for a high frequency wave to get
transmitter that is generated by oscillator 1. Thus, a high frequency
signal is achieved in case of bit 1 of the message signal.

 As against when the input bit is level low, ie, low frequency carrier
(f2) get transmitter f2 is generated by oscillator.
 In order to eliminate phase discontinuities of the signal at the
output, an internal clock is provided to the oscillator.

COHERENT DETECTION OF BFSK

 It consists of 2 separate mixers followed by the integrators that

form the two correlators in the circuit. The output of this correlator
is then fed to the decision device. This decision device generates
the binary signal which is the original modulating signal.
 The output of the 2 separate integrators is then compared by the
decision-making device. When the output of integrators 1 is more
than that of the integrators 2 then the frequency of the carrier
associated with correlators 1 generates the bit symbol. Assume, it
to be high frequency carrier than a logic high is generated at the
output.
 Similarly, when the output of the integrator 2 exceeds integrator 1
then the carrier frequency associated with correlator 2 generates
 symbol in favour of that frequency. Let us assume conversely that
it is a low frequency wave then symbol o is achieved at the output.

BPSK MODULATOR
The block diagram of Binary Phase keying consists of the blance
modulator which has the carrier sine wave as one input and the binary
sequence as the other input. Following is the diagrammatic
representation.

QPSK (QUADRATURE PHASE SHIFT KEYING)

 The QPSK is a variation of BPSK, which sends two bits of
digital information at a time, called as bigits.
 Instead of the conversion of digital bits into a series of digital
stream, it converts them into bit pairs. This decreases the data
bit pairs. This decreases the data bit rate to half, which allows
space for the other users.
QPSK MODULATOR

At the modulators input, the message signal’s even bits (ie, 2nd bit,
4th bit, 8th bit, etc) and odd bits(ie, 1st bit, 3rd bit, 5th bit etc) are
separated by the bits splitter and are multiplied with the same
carrier to generate odd BPSK (called as PSKI) and even BPSK
(called as PSKQ).The PSKQ signal is anyhow phase shifted by 90.
Before being modulated.
The PKSI signal and PSKQ signals are combined in an adder
component and thus QPSK modulated signal is formed.
MSK(MINIMUM SHIFT KEYING)
 Consider a continuous – phase frequency shift keying (CPFSK)
Signal, which is defined for the interval O < t < Tb as follows.

 Eb is the transmitted signal energy per bit.

 Tb is the bit duration.
 The phase Q co), denoting the value of the phase at time t=0.

MSK TRANSMITTER

 Two inputs cosine waves, cos 2πfct and cos πt/2tb are first
applied to a product modulator.
 This produces two phase coherent cosine waves at frequencies
f1 and f2.
 These two cosine waves separated form each other by two
narrow band filters one cantered at f1 and other at f2.
 The resulting filter output are linearly combined to produce the
pair of quadrature carriers.
 Finally, θ1(t) and θ2(t) are multiplied with two binary waves
a1(t) and a2(t).
 The two binary waves a1(t) and a2(t) extracted from the
incoming binary sequence.
 Two multiplies outputs are summed to get the MSK signal
output.
MSK RECEIVER

 The received signal x(t) is correlated with signal θ1(t) and θ2(t).
 The output of in phase and quadrature signal is then integrated.
 The resulting and in phase and quadrature channel correlator
output x1 and x2 are each compared with threshold of zero.
 Finally, these phase decisions are interleaved so as to
reconstruct the original input binary sequence.